[mirror_ubuntu-bionic-kernel.git] / arch / blackfin / mm / isram-driver.c

/*
 * Instruction SRAM accessor functions for the Blackfin
 *
 * Copyright 2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later
 */

#define pr_fmt(fmt) "isram: " fmt

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>

#include <asm/blackfin.h>
#include <asm/dma.h>

/*
 * IMPORTANT WARNING ABOUT THESE FUNCTIONS
 *
 * The emulator will not function correctly if a write command is left in
 * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
 * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
 * and DTEST_COMMAND are zero when exiting these functions.
 */


/*
 * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
 * be accessed by a normal core load, so we need to go through a few hoops to
 * read/write it.
 * To try to make it easier - we export a memcpy interface, where either src or
 * dest can be in this special L1 memory area.
 * The low level read/write functions should not be exposed to the rest of the
 * kernel, since they operate on 64-bit data, and need specific address alignment
 */

static DEFINE_SPINLOCK(dtest_lock);

/* Takes a void pointer */
#define IADDR2DTEST(x) \
	({ unsigned long __addr = (unsigned long)(x); \
		((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1)   */ \
		(1 << 24)                           | /* instruction access = 1    */ \
		((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank)   */ \
		((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
		(__addr & 0x47F8)                   | /* addr bits 14 & 10:3       */ \
		(1 << 2);                             /* data array = 1            */ \
	})

/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)

/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)

static void isram_write(const void *addr, uint64_t data)
{
	uint32_t cmd;
	unsigned long flags;

	if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)))
		return;

	cmd = IADDR2DTEST(addr) | 2;             /* write */

	/*
	 * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	 * While in exception context - atomicity is guaranteed or double fault
	 */
	spin_lock_irqsave(&dtest_lock, flags);

	bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
	bfin_write_DTEST_DATA1(data >> 32);

	/* use the builtin, since interrupts are already turned off */
	__builtin_bfin_csync();
	bfin_write_DTEST_COMMAND(cmd);
	__builtin_bfin_csync();

	bfin_write_DTEST_COMMAND(0);
	__builtin_bfin_csync();

	spin_unlock_irqrestore(&dtest_lock, flags);
}

static uint64_t isram_read(const void *addr)
{
	uint32_t cmd;
	unsigned long flags;
	uint64_t ret;

	if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)))
		return 0;

	cmd = IADDR2DTEST(addr) | 0;              /* read */

	/*
	 * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	 * While in exception context - atomicity is guaranteed or double fault
	 */
	spin_lock_irqsave(&dtest_lock, flags);
	/* use the builtin, since interrupts are already turned off */
	__builtin_bfin_csync();
	bfin_write_DTEST_COMMAND(cmd);
	__builtin_bfin_csync();
	ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);

	bfin_write_DTEST_COMMAND(0);
	__builtin_bfin_csync();
	spin_unlock_irqrestore(&dtest_lock, flags);

	return ret;
}

static bool isram_check_addr(const void *addr, size_t n)
{
	if ((addr >= (void *)L1_CODE_START) &&
	    (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
		if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
			show_stack(NULL, NULL);
			pr_err("copy involving %p length (%zu) too long\n", addr, n);
		}
		return true;
	}
	return false;
}

/*
 * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
 * The isram_memcpy() function returns a pointer to dest.
 * Either dest or src can be in L1 instruction sram.
 */
void *isram_memcpy(void *dest, const void *src, size_t n)
{
	uint64_t data_in = 0, data_out = 0;
	size_t count;
	bool dest_in_l1, src_in_l1, need_data, put_data;
	unsigned char byte, *src_byte, *dest_byte;

	src_byte = (unsigned char *)src;
	dest_byte = (unsigned char *)dest;

	dest_in_l1 = isram_check_addr(dest, n);
	src_in_l1 = isram_check_addr(src, n);

	need_data = true;
	put_data = true;
	for (count = 0; count < n; count++) {
		if (src_in_l1) {
			if (need_data) {
				data_in = isram_read(src + count);
				need_data = false;
			}

			if (ADDR2LAST(src + count))
				need_data = true;

			byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);

		} else {
			/* src is in L2 or L3 - so just dereference*/
			byte = src_byte[count];
		}

		if (dest_in_l1) {
			if (put_data) {
				data_out = isram_read(dest + count);
				put_data = false;
			}

			data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
			data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));

			if (ADDR2LAST(dest + count)) {
				put_data = true;
				isram_write(dest + count, data_out);
			}
		} else {
			/* dest in L2 or L3 - so just dereference */
			dest_byte[count] = byte;
		}
	}

	/* make sure we dump the last byte if necessary */
	if (dest_in_l1 && !put_data)
		isram_write(dest + count, data_out);

	return dest;
}
EXPORT_SYMBOL(isram_memcpy);

#ifdef CONFIG_BFIN_ISRAM_SELF_TEST

static int test_len = 0x20000;

static __init void hex_dump(unsigned char *buf, int len)
{
	while (len--)
		pr_cont("%02x", *buf++);
}

static __init int isram_read_test(char *sdram, void *l1inst)
{
	int i, ret = 0;
	uint64_t data1, data2;

	pr_info("INFO: running isram_read tests\n");

	/* setup some different data to play with */
	for (i = 0; i < test_len; ++i)
		sdram[i] = i % 255;
	dma_memcpy(l1inst, sdram, test_len);

	/* make sure we can read the L1 inst */
	for (i = 0; i < test_len; i += sizeof(uint64_t)) {
		data1 = isram_read(l1inst + i);
		memcpy(&data2, sdram + i, sizeof(data2));
		if (data1 != data2) {
			pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
				l1inst + i, data1, data2);
			++ret;
		}
	}

	return ret;
}

static __init int isram_write_test(char *sdram, void *l1inst)
{
	int i, ret = 0;
	uint64_t data1, data2;

	pr_info("INFO: running isram_write tests\n");

	/* setup some different data to play with */
	memset(sdram, 0, test_len * 2);
	dma_memcpy(l1inst, sdram, test_len);
	for (i = 0; i < test_len; ++i)
		sdram[i] = i % 255;

	/* make sure we can write the L1 inst */
	for (i = 0; i < test_len; i += sizeof(uint64_t)) {
		memcpy(&data1, sdram + i, sizeof(data1));
		isram_write(l1inst + i, data1);
		data2 = isram_read(l1inst + i);
		if (data1 != data2) {
			pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
				l1inst + i, data1, data2);
			++ret;
		}
	}

	dma_memcpy(sdram + test_len, l1inst, test_len);
	if (memcmp(sdram, sdram + test_len, test_len)) {
		pr_err("FAIL: isram_write() did not work properly\n");
		++ret;
	}

	return ret;
}

static __init int
_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
                   void *(*fmemcpy)(void *, const void *, size_t))
{
	memset(sdram, pattern, test_len);
	fmemcpy(l1inst, sdram, test_len);
	fmemcpy(sdram + test_len, l1inst, test_len);
	if (memcmp(sdram, sdram + test_len, test_len)) {
		pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
			smemcpy, l1inst, sdram, test_len, pattern);
		return 1;
	}
	return 0;
}
#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)

static __init int isram_memcpy_test(char *sdram, void *l1inst)
{
	int i, j, thisret, ret = 0;

	/* check broad isram_memcpy() */
	pr_info("INFO: running broad isram_memcpy tests\n");
	for (i = 0xf; i >= 0; --i)
		ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);

	/* check read of small, unaligned, and hardware 64bit limits */
	pr_info("INFO: running isram_memcpy (read) tests\n");

	/* setup some different data to play with */
	for (i = 0; i < test_len; ++i)
		sdram[i] = i % 255;
	dma_memcpy(l1inst, sdram, test_len);

	thisret = 0;
	for (i = 0; i < test_len - 32; ++i) {
		unsigned char cmp[32];
		for (j = 1; j <= 32; ++j) {
			memset(cmp, 0, sizeof(cmp));
			isram_memcpy(cmp, l1inst + i, j);
			if (memcmp(cmp, sdram + i, j)) {
				pr_err("FAIL: %p:", l1inst + 1);
				hex_dump(cmp, j);
				pr_cont(" SDRAM:");
				hex_dump(sdram + i, j);
				pr_cont("\n");
				if (++thisret > 20) {
					pr_err("FAIL: skipping remaining series\n");
					i = test_len;
					break;
				}
			}
		}
	}
	ret += thisret;

	/* check write of small, unaligned, and hardware 64bit limits */
	pr_info("INFO: running isram_memcpy (write) tests\n");

	memset(sdram + test_len, 0, test_len);
	dma_memcpy(l1inst, sdram + test_len, test_len);

	thisret = 0;
	for (i = 0; i < test_len - 32; ++i) {
		unsigned char cmp[32];
		for (j = 1; j <= 32; ++j) {
			isram_memcpy(l1inst + i, sdram + i, j);
			dma_memcpy(cmp, l1inst + i, j);
			if (memcmp(cmp, sdram + i, j)) {
				pr_err("FAIL: %p:", l1inst + i);
				hex_dump(cmp, j);
				pr_cont(" SDRAM:");
				hex_dump(sdram + i, j);
				pr_cont("\n");
				if (++thisret > 20) {
					pr_err("FAIL: skipping remaining series\n");
					i = test_len;
					break;
				}
			}
		}
	}
	ret += thisret;

	return ret;
}

static __init int isram_test_init(void)
{
	int ret;
	char *sdram;
	void *l1inst;

	/* Try to test as much of L1SRAM as possible */
	while (test_len) {
		test_len >>= 1;
		l1inst = l1_inst_sram_alloc(test_len);
		if (l1inst)
			break;
	}
	if (!l1inst) {
		pr_warning("SKIP: could not allocate L1 inst\n");
		return 0;
	}
	pr_info("INFO: testing %#x bytes (%p - %p)\n",
	        test_len, l1inst, l1inst + test_len);

	sdram = kmalloc(test_len * 2, GFP_KERNEL);
	if (!sdram) {
		sram_free(l1inst);
		pr_warning("SKIP: could not allocate sdram\n");
		return 0;
	}

	/* sanity check initial L1 inst state */
	ret = 1;
	pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
	if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
		goto abort;
	if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
		goto abort;

	ret = 0;
	ret += isram_read_test(sdram, l1inst);
	ret += isram_write_test(sdram, l1inst);
	ret += isram_memcpy_test(sdram, l1inst);

 abort:
	sram_free(l1inst);
	kfree(sdram);

	if (ret)
		return -EIO;

	pr_info("PASS: all tests worked !\n");
	return 0;
}
late_initcall(isram_test_init);

static __exit void isram_test_exit(void)
{
	/* stub to allow unloading */
}
module_exit(isram_test_exit);

#endif
Commit	Line	Data
9df10281	1	/*
96f1050d	2	* Instruction SRAM accessor functions for the Blackfin
9df10281 RG	3	*
	4	* Copyright 2008 Analog Devices Inc.
	5	*
96f1050d	6	* Licensed under the GPL-2 or later
9df10281 RG	7	*/
9df10281 RG	8
c40cdb2c MF	9	#define pr_fmt(fmt) "isram: " fmt
c40cdb2c MF	10
9df10281 RG	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
5a0e3ad6	14	#include <linux/slab.h>
9df10281 RG	15	#include <linux/spinlock.h>
9df10281 RG	16	#include <linux/sched.h>
b17b0153	17	#include <linux/sched/debug.h>
9df10281 RG	18
9df10281 RG	19	#include <asm/blackfin.h>
c40cdb2c	20	#include <asm/dma.h>
9df10281 RG	21
	22	/*
	23	* IMPORTANT WARNING ABOUT THESE FUNCTIONS
	24	*
	25	* The emulator will not function correctly if a write command is left in
	26	* ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
	27	* the emulator. To avoid such problems, ensure that both ITEST_COMMAND
	28	* and DTEST_COMMAND are zero when exiting these functions.
	29	*/
	30
	31
	32	/*
	33	* On the Blackfin, L1 instruction sram (which operates at core speeds) can not
	34	* be accessed by a normal core load, so we need to go through a few hoops to
	35	* read/write it.
	36	* To try to make it easier - we export a memcpy interface, where either src or
	37	* dest can be in this special L1 memory area.
	38	* The low level read/write functions should not be exposed to the rest of the
	39	* kernel, since they operate on 64-bit data, and need specific address alignment
	40	*/
	41
	42	static DEFINE_SPINLOCK(dtest_lock);
	43
	44	/* Takes a void pointer */
	45	#define IADDR2DTEST(x) \
	46	({ unsigned long __addr = (unsigned long)(x); \
c70dcabc MF	47	((__addr & (1 << 11)) << (26 - 11)) \| /* addr bit 11 (Way0/Way1) */ \
	48	(1 << 24) \| /* instruction access = 1 */ \
	49	((__addr & (1 << 15)) << (23 - 15)) \| /* addr bit 15 (Data Bank) */ \
	50	((__addr & (3 << 12)) << (16 - 12)) \| /* addr bits 13:12 (Subbank) */ \
	51	(__addr & 0x47F8) \| /* addr bits 14 & 10:3 */ \
	52	(1 << 2); /* data array = 1 */ \
9df10281 RG	53	})
	54
	55	/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
	56	#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
	57
	58	/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
	59	#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
	60
	61	static void isram_write(const void *addr, uint64_t data)
	62	{
	63	uint32_t cmd;
	64	unsigned long flags;
	65
f05ede3a	66	if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)))
9df10281 RG	67	return;
9df10281 RG	68
774b8022	69	cmd = IADDR2DTEST(addr) \| 2; /* write */
9df10281 RG	70
	71	/*
	72	* Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	73	* While in exception context - atomicity is guaranteed or double fault
	74	*/
	75	spin_lock_irqsave(&dtest_lock, flags);
	76
	77	bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
	78	bfin_write_DTEST_DATA1(data >> 32);
	79
	80	/* use the builtin, since interrupts are already turned off */
	81	__builtin_bfin_csync();
	82	bfin_write_DTEST_COMMAND(cmd);
	83	__builtin_bfin_csync();
	84
	85	bfin_write_DTEST_COMMAND(0);
	86	__builtin_bfin_csync();
	87
	88	spin_unlock_irqrestore(&dtest_lock, flags);
	89	}
	90
	91	static uint64_t isram_read(const void *addr)
	92	{
	93	uint32_t cmd;
	94	unsigned long flags;
	95	uint64_t ret;
	96
f05ede3a	97	if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)))
9df10281 RG	98	return 0;
	99
	100	cmd = IADDR2DTEST(addr) \| 0; /* read */
	101
	102	/*
	103	* Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	104	* While in exception context - atomicity is guaranteed or double fault
	105	*/
	106	spin_lock_irqsave(&dtest_lock, flags);
	107	/* use the builtin, since interrupts are already turned off */
	108	__builtin_bfin_csync();
	109	bfin_write_DTEST_COMMAND(cmd);
	110	__builtin_bfin_csync();
	111	ret = bfin_read_DTEST_DATA0() \| ((uint64_t)bfin_read_DTEST_DATA1() << 32);
	112
	113	bfin_write_DTEST_COMMAND(0);
	114	__builtin_bfin_csync();
	115	spin_unlock_irqrestore(&dtest_lock, flags);
	116
	117	return ret;
	118	}
	119
	120	static bool isram_check_addr(const void *addr, size_t n)
	121	{
	122	if ((addr >= (void *)L1_CODE_START) &&
	123	(addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
f05ede3a	124	if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
9df10281	125	show_stack(NULL, NULL);
c40cdb2c	126	pr_err("copy involving %p length (%zu) too long\n", addr, n);
9df10281 RG	127	}
	128	return true;
	129	}
	130	return false;
	131	}
	132
	133	/*
	134	* The isram_memcpy() function copies n bytes from memory area src to memory area dest.
	135	* The isram_memcpy() function returns a pointer to dest.
	136	* Either dest or src can be in L1 instruction sram.
	137	*/
	138	void isram_memcpy(void dest, const void *src, size_t n)
	139	{
	140	uint64_t data_in = 0, data_out = 0;
	141	size_t count;
	142	bool dest_in_l1, src_in_l1, need_data, put_data;
	143	unsigned char byte, src_byte, dest_byte;
	144
	145	src_byte = (unsigned char *)src;
	146	dest_byte = (unsigned char *)dest;
	147
	148	dest_in_l1 = isram_check_addr(dest, n);
	149	src_in_l1 = isram_check_addr(src, n);
	150
	151	need_data = true;
	152	put_data = true;
	153	for (count = 0; count < n; count++) {
	154	if (src_in_l1) {
	155	if (need_data) {
	156	data_in = isram_read(src + count);
	157	need_data = false;
	158	}
	159
	160	if (ADDR2LAST(src + count))
	161	need_data = true;
	162
	163	byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
	164
	165	} else {
	166	/* src is in L2 or L3 - so just dereference*/
	167	byte = src_byte[count];
	168	}
	169
	170	if (dest_in_l1) {
	171	if (put_data) {
	172	data_out = isram_read(dest + count);
	173	put_data = false;
	174	}
	175
	176	data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
	177	data_out \|= ((uint64_t)byte << ADDR2OFFSET(dest + count));
	178
	179	if (ADDR2LAST(dest + count)) {
	180	put_data = true;
	181	isram_write(dest + count, data_out);
	182	}
	183	} else {
	184	/* dest in L2 or L3 - so just dereference */
	185	dest_byte[count] = byte;
	186	}
	187	}
	188
	189	/* make sure we dump the last byte if necessary */
	190	if (dest_in_l1 && !put_data)
191	isram_write(dest + count, data_out);
192
193	return dest;
194	}
195	EXPORT_SYMBOL(isram_memcpy);
196
c40cdb2c MF	197	#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
c40cdb2c MF	198
c70dcabc	199	static int test_len = 0x20000;
c40cdb2c MF	200
	201	static __init void hex_dump(unsigned char *buf, int len)
	202	{
	203	while (len--)
	204	pr_cont("%02x", *buf++);
	205	}
	206
	207	static __init int isram_read_test(char sdram, void l1inst)
	208	{
	209	int i, ret = 0;
	210	uint64_t data1, data2;
	211
	212	pr_info("INFO: running isram_read tests\n");
	213
	214	/* setup some different data to play with */
c70dcabc MF	215	for (i = 0; i < test_len; ++i)
	216	sdram[i] = i % 255;
	217	dma_memcpy(l1inst, sdram, test_len);
c40cdb2c MF	218
c40cdb2c MF	219	/* make sure we can read the L1 inst */
c70dcabc	220	for (i = 0; i < test_len; i += sizeof(uint64_t)) {
c40cdb2c MF	221	data1 = isram_read(l1inst + i);
c40cdb2c MF	222	memcpy(&data2, sdram + i, sizeof(data2));
c70dcabc	223	if (data1 != data2) {
c40cdb2c MF	224	pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
	225	l1inst + i, data1, data2);
	226	++ret;
	227	}
	228	}
	229
	230	return ret;
	231	}
	232
	233	static __init int isram_write_test(char sdram, void l1inst)
	234	{
	235	int i, ret = 0;
	236	uint64_t data1, data2;
	237
	238	pr_info("INFO: running isram_write tests\n");
	239
	240	/* setup some different data to play with */
c70dcabc MF	241	memset(sdram, 0, test_len * 2);
	242	dma_memcpy(l1inst, sdram, test_len);
	243	for (i = 0; i < test_len; ++i)
	244	sdram[i] = i % 255;
c40cdb2c MF	245
c40cdb2c MF	246	/* make sure we can write the L1 inst */
c70dcabc	247	for (i = 0; i < test_len; i += sizeof(uint64_t)) {
c40cdb2c MF	248	memcpy(&data1, sdram + i, sizeof(data1));
	249	isram_write(l1inst + i, data1);
	250	data2 = isram_read(l1inst + i);
c70dcabc	251	if (data1 != data2) {
c40cdb2c MF	252	pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
	253	l1inst + i, data1, data2);
	254	++ret;
	255	}
	256	}
	257
c70dcabc MF	258	dma_memcpy(sdram + test_len, l1inst, test_len);
c70dcabc MF	259	if (memcmp(sdram, sdram + test_len, test_len)) {
c40cdb2c MF	260	pr_err("FAIL: isram_write() did not work properly\n");
	261	++ret;
	262	}
	263
	264	return ret;
	265	}
	266
	267	static __init int
	268	_isram_memcpy_test(char pattern, void sdram, void l1inst, const char *smemcpy,
	269	void (fmemcpy)(void , const void , size_t))
	270	{
c70dcabc MF	271	memset(sdram, pattern, test_len);
	272	fmemcpy(l1inst, sdram, test_len);
	273	fmemcpy(sdram + test_len, l1inst, test_len);
	274	if (memcmp(sdram, sdram + test_len, test_len)) {
c40cdb2c	275	pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
c70dcabc	276	smemcpy, l1inst, sdram, test_len, pattern);
c40cdb2c MF	277	return 1;
	278	}
	279	return 0;
	280	}
	281	#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
	282
	283	static __init int isram_memcpy_test(char sdram, void l1inst)
	284	{
	285	int i, j, thisret, ret = 0;
	286
	287	/* check broad isram_memcpy() */
	288	pr_info("INFO: running broad isram_memcpy tests\n");
	289	for (i = 0xf; i >= 0; --i)
	290	ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
	291
	292	/* check read of small, unaligned, and hardware 64bit limits */
	293	pr_info("INFO: running isram_memcpy (read) tests\n");
	294
c70dcabc MF	295	/* setup some different data to play with */
	296	for (i = 0; i < test_len; ++i)
	297	sdram[i] = i % 255;
	298	dma_memcpy(l1inst, sdram, test_len);
c40cdb2c MF	299
c40cdb2c MF	300	thisret = 0;
c70dcabc	301	for (i = 0; i < test_len - 32; ++i) {
c40cdb2c MF	302	unsigned char cmp[32];
	303	for (j = 1; j <= 32; ++j) {
	304	memset(cmp, 0, sizeof(cmp));
	305	isram_memcpy(cmp, l1inst + i, j);
	306	if (memcmp(cmp, sdram + i, j)) {
	307	pr_err("FAIL: %p:", l1inst + 1);
	308	hex_dump(cmp, j);
	309	pr_cont(" SDRAM:");
	310	hex_dump(sdram + i, j);
	311	pr_cont("\n");
	312	if (++thisret > 20) {
	313	pr_err("FAIL: skipping remaining series\n");
c70dcabc	314	i = test_len;
c40cdb2c MF	315	break;
	316	}
	317	}
	318	}
	319	}
	320	ret += thisret;
	321
	322	/* check write of small, unaligned, and hardware 64bit limits */
	323	pr_info("INFO: running isram_memcpy (write) tests\n");
	324
c70dcabc MF	325	memset(sdram + test_len, 0, test_len);
c70dcabc MF	326	dma_memcpy(l1inst, sdram + test_len, test_len);
c40cdb2c MF	327
c40cdb2c MF	328	thisret = 0;
c70dcabc	329	for (i = 0; i < test_len - 32; ++i) {
c40cdb2c MF	330	unsigned char cmp[32];
	331	for (j = 1; j <= 32; ++j) {
	332	isram_memcpy(l1inst + i, sdram + i, j);
	333	dma_memcpy(cmp, l1inst + i, j);
	334	if (memcmp(cmp, sdram + i, j)) {
	335	pr_err("FAIL: %p:", l1inst + i);
	336	hex_dump(cmp, j);
	337	pr_cont(" SDRAM:");
	338	hex_dump(sdram + i, j);
	339	pr_cont("\n");
	340	if (++thisret > 20) {
	341	pr_err("FAIL: skipping remaining series\n");
c70dcabc	342	i = test_len;
c40cdb2c MF	343	break;
	344	}
	345	}
	346	}
	347	}
	348	ret += thisret;
	349
	350	return ret;
	351	}
	352
	353	static __init int isram_test_init(void)
	354	{
	355	int ret;
	356	char *sdram;
	357	void *l1inst;
	358
c70dcabc MF	359	/* Try to test as much of L1SRAM as possible */
	360	while (test_len) {
	361	test_len >>= 1;
	362	l1inst = l1_inst_sram_alloc(test_len);
	363	if (l1inst)
	364	break;
c40cdb2c	365	}
c40cdb2c	366	if (!l1inst) {
c40cdb2c MF	367	pr_warning("SKIP: could not allocate L1 inst\n");
	368	return 0;
	369	}
c70dcabc MF	370	pr_info("INFO: testing %#x bytes (%p - %p)\n",
	371	test_len, l1inst, l1inst + test_len);
	372
	373	sdram = kmalloc(test_len * 2, GFP_KERNEL);
	374	if (!sdram) {
	375	sram_free(l1inst);
	376	pr_warning("SKIP: could not allocate sdram\n");
	377	return 0;
	378	}
c40cdb2c MF	379
	380	/* sanity check initial L1 inst state */
	381	ret = 1;
c70dcabc	382	pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
c40cdb2c MF	383	if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
	384	goto abort;
	385	if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
	386	goto abort;
	387
	388	ret = 0;
	389	ret += isram_read_test(sdram, l1inst);
	390	ret += isram_write_test(sdram, l1inst);
	391	ret += isram_memcpy_test(sdram, l1inst);
	392
	393	abort:
	394	sram_free(l1inst);
	395	kfree(sdram);
	396
	397	if (ret)
	398	return -EIO;
	399
	400	pr_info("PASS: all tests worked !\n");
	401	return 0;
	402	}
	403	late_initcall(isram_test_init);
	404
	405	static __exit void isram_test_exit(void)
	406	{
	407	/* stub to allow unloading */
	408	}
	409	module_exit(isram_test_exit);
	410
	411	#endif