projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 784bdcd0 AJ |
2 | /* |
| 3 | * Port on Texas Instruments TMS320C6x architecture | |
| 4 | * | |
| 6330c790 | 5 | * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated |
| 784bdcd0 | 6 | * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) |
| 784bdcd0 AJ |
7 | */ |
| 8 | #ifndef _ASM_C6X_CACHE_H | |
| 9 | #define _ASM_C6X_CACHE_H | |
| 10 | ||
| 11 | #include <linux/irqflags.h> | |
| ae72758f | 12 | #include <linux/init.h> |
| 784bdcd0 AJ |
13 | |
| 14 | /* | |
| 15 | * Cache line size | |
| 16 | */ | |
| 6330c790 MS |
17 | #define L1D_CACHE_SHIFT 6 |
| 18 | #define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) | |
| 19 | ||
| 20 | #define L1P_CACHE_SHIFT 5 | |
| 21 | #define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) | |
| 22 | ||
| 23 | #define L2_CACHE_SHIFT 7 | |
| 24 | #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) | |
| 784bdcd0 AJ |
25 | |
| 26 | /* | |
| 27 | * L2 used as cache | |
| 28 | */ | |
| 29 | #define L2MODE_SIZE L2MODE_256K_CACHE | |
| 30 | ||
| 31 | /* | |
| 32 | * For practical reasons the L1_CACHE_BYTES defines should not be smaller than | |
| 33 | * the L2 line size | |
| 34 | */ | |
| 6330c790 MS |
35 | #define L1_CACHE_SHIFT L2_CACHE_SHIFT |
| 36 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
| 784bdcd0 AJ |
37 | |
| 38 | #define L2_CACHE_ALIGN_LOW(x) \ | |
| 39 | (((x) & ~(L2_CACHE_BYTES - 1))) | |
| 40 | #define L2_CACHE_ALIGN_UP(x) \ | |
| 41 | (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1)) | |
| 42 | #define L2_CACHE_ALIGN_CNT(x) \ | |
| 43 | (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1)) | |
| 44 | ||
| 45 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES | |
| 46 | #define ARCH_SLAB_MINALIGN L1_CACHE_BYTES | |
| 47 | ||
| 48 | /* | |
| 49 | * This is the granularity of hardware cacheability control. | |
| 50 | */ | |
| 51 | #define CACHEABILITY_ALIGN 0x01000000 | |
| 52 | ||
| 53 | /* | |
| 54 | * Align a physical address to MAR regions | |
| 55 | */ | |
| 56 | #define CACHE_REGION_START(v) \ | |
| 57 | (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1)) | |
| 58 | #define CACHE_REGION_END(v) \ | |
| 59 | (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1)) | |
| 60 | ||
| 61 | extern void __init c6x_cache_init(void); | |
| 62 | ||
| 63 | extern void enable_caching(unsigned long start, unsigned long end); | |
| 64 | extern void disable_caching(unsigned long start, unsigned long end); | |
| 65 | ||
| 66 | extern void L1_cache_off(void); | |
| 67 | extern void L1_cache_on(void); | |
| 68 | ||
| 69 | extern void L1P_cache_global_invalidate(void); | |
| 70 | extern void L1D_cache_global_invalidate(void); | |
| 71 | extern void L1D_cache_global_writeback(void); | |
| 72 | extern void L1D_cache_global_writeback_invalidate(void); | |
| 73 | extern void L2_cache_set_mode(unsigned int mode); | |
| 74 | extern void L2_cache_global_writeback_invalidate(void); | |
| 75 | extern void L2_cache_global_writeback(void); | |
| 76 | ||
| 77 | extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end); | |
| 78 | extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end); | |
| 79 | extern void L1D_cache_block_writeback_invalidate(unsigned int start, | |
| 80 | unsigned int end); | |
| 81 | extern void L1D_cache_block_writeback(unsigned int start, unsigned int end); | |
| 82 | extern void L2_cache_block_invalidate(unsigned int start, unsigned int end); | |
| 83 | extern void L2_cache_block_writeback(unsigned int start, unsigned int end); | |
| 84 | extern void L2_cache_block_writeback_invalidate(unsigned int start, | |
| 85 | unsigned int end); | |
| 86 | extern void L2_cache_block_invalidate_nowait(unsigned int start, | |
| 87 | unsigned int end); | |
| 88 | extern void L2_cache_block_writeback_nowait(unsigned int start, | |
| 89 | unsigned int end); | |
| 90 | ||
| 91 | extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start, | |
| 92 | unsigned int end); | |
| 93 | ||
| 94 | #endif /* _ASM_C6X_CACHE_H */ |