projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| c1a144d7 AJ |
1 | ; |
| 2 | ; Port on Texas Instruments TMS320C6x architecture | |
| 3 | ; | |
| 4 | ; Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated | |
| 5 | ; Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) | |
| 6 | ; | |
| 7 | ; This program is free software; you can redistribute it and/or modify | |
| 8 | ; it under the terms of the GNU General Public License version 2 as | |
| 9 | ; published by the Free Software Foundation. | |
| 10 | ; | |
| 11 | ; This section handles all the interrupt vector routines. | |
| 12 | ; At RESET the processor sets up the DRAM timing parameters and | |
| 13 | ; branches to the label _c_int00 which handles initialization for the C code. | |
| 14 | ; | |
| 15 | ||
| 16 | #define ALIGNMENT 5 | |
| 17 | ||
| 18 | .macro IRQVEC name, handler | |
| 19 | .align ALIGNMENT | |
| 20 | .hidden \name | |
| 21 | .global \name | |
| 22 | \name: | |
| 23 | #ifdef CONFIG_C6X_BIG_KERNEL | |
| 24 | STW .D2T1 A0,*B15--[2] | |
| 25 | || MVKL .S1 \handler,A0 | |
| 26 | MVKH .S1 \handler,A0 | |
| 27 | B .S2X A0 | |
| 28 | LDW .D2T1 *++B15[2],A0 | |
| 29 | NOP 4 | |
| 30 | NOP | |
| 31 | NOP | |
| 32 | .endm | |
| 33 | #else /* CONFIG_C6X_BIG_KERNEL */ | |
| 34 | B .S2 \handler | |
| 35 | NOP | |
| 36 | NOP | |
| 37 | NOP | |
| 38 | NOP | |
| 39 | NOP | |
| 40 | NOP | |
| 41 | NOP | |
| 42 | .endm | |
| 43 | #endif /* CONFIG_C6X_BIG_KERNEL */ | |
| 44 | ||
| 45 | .sect ".vectors","ax" | |
| 46 | .align ALIGNMENT | |
| 47 | .global RESET | |
| 48 | .hidden RESET | |
| 49 | RESET: | |
| 50 | #ifdef CONFIG_C6X_BIG_KERNEL | |
| 51 | MVKL .S1 _c_int00,A0 ; branch to _c_int00 | |
| 52 | MVKH .S1 _c_int00,A0 | |
| 53 | B .S2X A0 | |
| 54 | #else | |
| 55 | B .S2 _c_int00 | |
| 56 | NOP | |
| 57 | NOP | |
| 58 | #endif | |
| 59 | NOP | |
| 60 | NOP | |
| 61 | NOP | |
| 62 | NOP | |
| 63 | NOP | |
| 64 | ||
| 65 | ||
| 66 | IRQVEC NMI,_nmi_handler ; NMI interrupt | |
| 67 | IRQVEC AINT,_bad_interrupt ; reserved | |
| 68 | IRQVEC MSGINT,_bad_interrupt ; reserved | |
| 69 | ||
| 70 | IRQVEC INT4,_int4_handler | |
| 71 | IRQVEC INT5,_int5_handler | |
| 72 | IRQVEC INT6,_int6_handler | |
| 73 | IRQVEC INT7,_int7_handler | |
| 74 | IRQVEC INT8,_int8_handler | |
| 75 | IRQVEC INT9,_int9_handler | |
| 76 | IRQVEC INT10,_int10_handler | |
| 77 | IRQVEC INT11,_int11_handler | |
| 78 | IRQVEC INT12,_int12_handler | |
| 79 | IRQVEC INT13,_int13_handler | |
| 80 | IRQVEC INT14,_int14_handler | |
| 81 | IRQVEC INT15,_int15_handler |