[mirror_ubuntu-hirsute-kernel.git] / arch / cris / arch-v10 / kernel / time.c

/*
 *  linux/arch/cris/arch-v10/kernel/time.c
 *
 *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
 *  Copyright (C) 1999-2002 Axis Communications AB
 *
 */

#include <linux/timex.h>
#include <linux/time.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/swap.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <arch/svinto.h>
#include <asm/types.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/rtc.h>
#include <asm/irq_regs.h>

/* define this if you need to use print_timestamp */
/* it will make jiffies at 96 hz instead of 100 hz though */
#undef USE_CASCADE_TIMERS

extern int set_rtc_mmss(unsigned long nowtime);
extern int have_rtc;

unsigned long get_ns_in_jiffie(void)
{
	unsigned char timer_count, t1;
	unsigned short presc_count;
	unsigned long ns;
	unsigned long flags;

	local_irq_save(flags);
	timer_count = *R_TIMER0_DATA;
	presc_count = *R_TIM_PRESC_STATUS;  
	/* presc_count might be wrapped */
	t1 = *R_TIMER0_DATA;

	if (timer_count != t1){
		/* it wrapped, read prescaler again...  */
		presc_count = *R_TIM_PRESC_STATUS;
		timer_count = t1;
	}
	local_irq_restore(flags);
	if (presc_count >= PRESCALE_VALUE/2 ){
		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	} else {
		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	}

	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + 
	     ( (presc_count) * (1000000000/PRESCALE_FREQ));
	return ns;
}

unsigned long do_slow_gettimeoffset(void)
{
	unsigned long count, t1;
	unsigned long usec_count = 0;
	unsigned short presc_count;

	static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
	static unsigned long jiffies_p = 0;

	/*
	 * cache volatile jiffies temporarily; we have IRQs turned off. 
	 */
	unsigned long jiffies_t;

	/* The timer interrupt comes from Etrax timer 0. In order to get
	 * better precision, we check the current value. It might have
	 * underflowed already though.
	 */

#ifndef CONFIG_SVINTO_SIM
	/* Not available in the xsim simulator. */
	count = *R_TIMER0_DATA;
	presc_count = *R_TIM_PRESC_STATUS;  
	/* presc_count might be wrapped */
	t1 = *R_TIMER0_DATA;
	if (count != t1){
		/* it wrapped, read prescaler again...  */
		presc_count = *R_TIM_PRESC_STATUS;
		count = t1;
	}
#else
	count = 0;
	presc_count = 0;
#endif

 	jiffies_t = jiffies;

	/*
	 * avoiding timer inconsistencies (they are rare, but they happen)...
	 * there are one problem that must be avoided here:
	 *  1. the timer counter underflows
	 */
	if( jiffies_t == jiffies_p ) {
		if( count > count_p ) {
			/* Timer wrapped, use new count and prescale 
			 * increase the time corresponding to one jiffie
			 */
			usec_count = 1000000/HZ;
		}
	} else
		jiffies_p = jiffies_t;
        count_p = count;
	if (presc_count >= PRESCALE_VALUE/2 ){
		presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	} else {
		presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	}
	/* Convert timer value to usec */
	usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
	              (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);

	return usec_count;
}

/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 *
 * 3.10.4 Watchdog timer

 * When the watchdog timer is started, it generates an NMI if the watchdog
 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 * stopped after an additional 3.3 ms, the watchdog resets the chip.
 * The watchdog timer is stopped after reset. The watchdog timer is controlled
 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 * described in the table below:
 * 
 *   Watchdog    Value written:
 *   state:      To enable:  To key:      Operation:
 *   --------    ----------  -------      ----------
 *   stopped         0         X          No effect.
 *   stopped         1       key_val      Start watchdog with key = key_val.
 *   started         0       ~key         Stop watchdog
 *   started         1       ~key         Restart watchdog with key = ~key.
 *   started         X       new_key_val  Change key to new_key_val.
 * 
 * Note: '~' is the bitwise NOT operator.
 * 
 */

/* right now, starting the watchdog is the same as resetting it */
#define start_watchdog reset_watchdog

#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
static int watchdog_key = 0;  /* arbitrary number */
#endif

/* number of pages to consider "out of memory". it is normal that the memory
 * is used though, so put this really low.
 */

#define WATCHDOG_MIN_FREE_PAGES 8

void
reset_watchdog(void)
{
#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	/* only keep watchdog happy as long as we have memory left! */
	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
		/* reset the watchdog with the inverse of the old key */
		watchdog_key ^= 0x7; /* invert key, which is 3 bits */
		*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
			IO_STATE(R_WATCHDOG, enable, start);
	}
#endif
}

/* stop the watchdog - we still need the correct key */

void 
stop_watchdog(void)
{
#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
		IO_STATE(R_WATCHDOG, enable, stop);
#endif	
}


/*
 * timer_interrupt() needs to keep up the real-time clock,
 * as well as call the "do_timer()" routine every clocktick
 */

//static unsigned short myjiff; /* used by our debug routine print_timestamp */

extern void cris_do_profile(struct pt_regs *regs);

static inline irqreturn_t
timer_interrupt(int irq, void *dev_id)
{
	struct pt_regs *regs = get_irq_regs();
	/* acknowledge the timer irq */

#ifdef USE_CASCADE_TIMERS
	*R_TIMER_CTRL =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, clr) |
		IO_STATE( R_TIMER_CTRL, tm1, run) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, clr) |
		IO_STATE( R_TIMER_CTRL, tm0, run) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
	*R_TIMER_CTRL = r_timer_ctrl_shadow | 
		IO_STATE(R_TIMER_CTRL, i0, clr);
#endif

	/* reset watchdog otherwise it resets us! */
	reset_watchdog();
	
	/* Update statistics. */
	update_process_times(user_mode(regs));

	/* call the real timer interrupt handler */

	do_timer(1);
	
        cris_do_profile(regs); /* Save profiling information */
        return IRQ_HANDLED;
}

/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 * it needs to be IRQF_DISABLED to make the jiffies update work properly
 */

static struct irqaction irq2  = {
	.handler = timer_interrupt,
	.flags = IRQF_SHARED | IRQF_DISABLED,
	.name = "timer",
};

void __init
time_init(void)
{	
	/* probe for the RTC and read it if it exists 
	 * Before the RTC can be probed the loops_per_usec variable needs 
	 * to be initialized to make usleep work. A better value for 
	 * loops_per_usec is calculated by the kernel later once the 
	 * clock has started.  
	 */
	loops_per_usec = 50;

	if(RTC_INIT() < 0)
		have_rtc = 0;
	else
		have_rtc = 1;

	/* Setup the etrax timers
	 * Base frequency is 25000 hz, divider 250 -> 100 HZ
	 * In normal mode, we use timer0, so timer1 is free. In cascade
	 * mode (which we sometimes use for debugging) both timers are used.
	 * Remember that linux/timex.h contains #defines that rely on the
	 * timer settings below (hz and divide factor) !!!
	 */
	
#ifdef USE_CASCADE_TIMERS
	*R_TIMER_CTRL =
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, nop) |
		IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, nop) |
		IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	
	*R_TIMER_CTRL = r_timer_ctrl_shadow = 
		IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
		IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
		IO_STATE( R_TIMER_CTRL, i1, nop) |
		IO_STATE( R_TIMER_CTRL, tm1, run) |
		IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
		IO_STATE( R_TIMER_CTRL, i0, nop) |
		IO_STATE( R_TIMER_CTRL, tm0, run) |
		IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
#else
	*R_TIMER_CTRL = 
		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
		IO_STATE(R_TIMER_CTRL, i1,        nop)      | 
		IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
	
	*R_TIMER_CTRL = r_timer_ctrl_shadow =
		IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
		IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
		IO_STATE(R_TIMER_CTRL, i1,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm1,       run)      |
		IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
		IO_STATE(R_TIMER_CTRL, i0,        nop)      |
		IO_STATE(R_TIMER_CTRL, tm0,       run)      |
		IO_STATE(R_TIMER_CTRL, clksel0,   flexible);

	*R_TIMER_PRESCALE = PRESCALE_VALUE;
#endif

	*R_IRQ_MASK0_SET =
		IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
	
	/* now actually register the timer irq handler that calls timer_interrupt() */
	
	setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */

	/* enable watchdog if we should use one */

#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	printk("Enabling watchdog...\n");
	start_watchdog();

	/* If we use the hardware watchdog, we want to trap it as an NMI
	   and dump registers before it resets us.  For this to happen, we
	   must set the "m" NMI enable flag (which once set, is unset only
	   when an NMI is taken).

	   The same goes for the external NMI, but that doesn't have any
	   driver or infrastructure support yet.  */
	asm ("setf m");

	*R_IRQ_MASK0_SET =
		IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
	*R_VECT_MASK_SET =
		IO_STATE(R_VECT_MASK_SET, nmi, set);
#endif
}
Commit	Line	Data
3244c77b	1	/*
1da177e4 LT	2	* linux/arch/cris/arch-v10/kernel/time.c
	3	*
	4	* Copyright (C) 1991, 1992, 1995 Linus Torvalds
	5	* Copyright (C) 1999-2002 Axis Communications AB
	6	*
	7	*/
	8
1da177e4 LT	9	#include <linux/timex.h>
	10	#include <linux/time.h>
	11	#include <linux/jiffies.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/swap.h>
	14	#include <linux/sched.h>
	15	#include <linux/init.h>
a1056873	16	#include <linux/mm.h>
556dcee7	17	#include <arch/svinto.h>
1da177e4 LT	18	#include <asm/types.h>
	19	#include <asm/signal.h>
	20	#include <asm/io.h>
	21	#include <asm/delay.h>
	22	#include <asm/rtc.h>
3244c77b	23	#include <asm/irq_regs.h>
1da177e4 LT	24
	25	/* define this if you need to use print_timestamp */
	26	/* it will make jiffies at 96 hz instead of 100 hz though */
	27	#undef USE_CASCADE_TIMERS
	28
1da177e4	29	extern int set_rtc_mmss(unsigned long nowtime);
1da177e4 LT	30	extern int have_rtc;
	31
	32	unsigned long get_ns_in_jiffie(void)
	33	{
	34	unsigned char timer_count, t1;
	35	unsigned short presc_count;
	36	unsigned long ns;
	37	unsigned long flags;
	38
	39	local_irq_save(flags);
1da177e4 LT	40	timer_count = *R_TIMER0_DATA;
	41	presc_count = *R_TIM_PRESC_STATUS;
	42	/* presc_count might be wrapped */
	43	t1 = *R_TIMER0_DATA;
	44
	45	if (timer_count != t1){
	46	/* it wrapped, read prescaler again... */
	47	presc_count = *R_TIM_PRESC_STATUS;
	48	timer_count = t1;
	49	}
	50	local_irq_restore(flags);
	51	if (presc_count >= PRESCALE_VALUE/2 ){
	52	presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
	53	} else {
	54	presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
	55	}
	56
	57	ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
	58	( (presc_count) * (1000000000/PRESCALE_FREQ));
	59	return ns;
	60	}
	61
	62	unsigned long do_slow_gettimeoffset(void)
	63	{
	64	unsigned long count, t1;
	65	unsigned long usec_count = 0;
	66	unsigned short presc_count;
	67
	68	static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
	69	static unsigned long jiffies_p = 0;
	70
	71	/*
	72	* cache volatile jiffies temporarily; we have IRQs turned off.
	73	*/
	74	unsigned long jiffies_t;
	75
	76	/* The timer interrupt comes from Etrax timer 0. In order to get
	77	* better precision, we check the current value. It might have
	78	* underflowed already though.
	79	*/
	80
	81	#ifndef CONFIG_SVINTO_SIM
	82	/* Not available in the xsim simulator. */
	83	count = *R_TIMER0_DATA;
	84	presc_count = *R_TIM_PRESC_STATUS;
	85	/* presc_count might be wrapped */
	86	t1 = *R_TIMER0_DATA;
	87	if (count != t1){
	88	/* it wrapped, read prescaler again... */
	89	presc_count = *R_TIM_PRESC_STATUS;
	90	count = t1;
	91	}
	92	#else
	93	count = 0;
	94	presc_count = 0;
	95	#endif
	96
	97	jiffies_t = jiffies;
	98
	99	/*
	100	* avoiding timer inconsistencies (they are rare, but they happen)...
	101	* there are one problem that must be avoided here:
	102	* 1. the timer counter underflows
	103	*/
104	if( jiffies_t == jiffies_p ) {
105	if( count > count_p ) {
106	/* Timer wrapped, use new count and prescale
107	* increase the time corresponding to one jiffie
108	*/
109	usec_count = 1000000/HZ;
110	}
111	} else
112	jiffies_p = jiffies_t;
113	count_p = count;
114	if (presc_count >= PRESCALE_VALUE/2 ){
115	presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
116	} else {
117	presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
118	}
119	/* Convert timer value to usec */
120	usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
121	(( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
122
123	return usec_count;
124	}
125
126	/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
127	*
128	* 3.10.4 Watchdog timer
129
130	* When the watchdog timer is started, it generates an NMI if the watchdog
131	* isn't restarted or stopped within 0.1 s. If it still isn't restarted or
132	* stopped after an additional 3.3 ms, the watchdog resets the chip.
133	* The watchdog timer is stopped after reset. The watchdog timer is controlled
134	* by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
135	* and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
136	* described in the table below:
137	*
138	* Watchdog Value written:
139	* state: To enable: To key: Operation:
140	* -------- ---------- ------- ----------
141	* stopped 0 X No effect.
142	* stopped 1 key_val Start watchdog with key = key_val.
143	* started 0 ~key Stop watchdog
144	* started 1 ~key Restart watchdog with key = ~key.
145	* started X new_key_val Change key to new_key_val.
146	*
147	* Note: '~' is the bitwise NOT operator.
148	*
149	*/
150
151	/* right now, starting the watchdog is the same as resetting it */
152	#define start_watchdog reset_watchdog
153
154	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
155	static int watchdog_key = 0; /* arbitrary number */
156	#endif
157
158	/* number of pages to consider "out of memory". it is normal that the memory
159	* is used though, so put this really low.
160	*/
161
162	#define WATCHDOG_MIN_FREE_PAGES 8
163
164	void
165	reset_watchdog(void)
166	{
167	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
168	/* only keep watchdog happy as long as we have memory left! */
169	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
170	/* reset the watchdog with the inverse of the old key */
171	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
172	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) \|
173	IO_STATE(R_WATCHDOG, enable, start);
174	}
175	#endif
176	}
177
178	/* stop the watchdog - we still need the correct key */
179
180	void
181	stop_watchdog(void)
182	{
183	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
184	watchdog_key ^= 0x7; /* invert key, which is 3 bits */
185	*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) \|
186	IO_STATE(R_WATCHDOG, enable, stop);
187	#endif
188	}
189
1da177e4 LT	190
	191	/*
	192	* timer_interrupt() needs to keep up the real-time clock,
	193	* as well as call the "do_timer()" routine every clocktick
	194	*/
	195
	196	//static unsigned short myjiff; /* used by our debug routine print_timestamp */
	197
	198	extern void cris_do_profile(struct pt_regs *regs);
	199
	200	static inline irqreturn_t
3244c77b	201	timer_interrupt(int irq, void *dev_id)
1da177e4	202	{
3244c77b	203	struct pt_regs *regs = get_irq_regs();
1da177e4 LT	204	/* acknowledge the timer irq */
	205
	206	#ifdef USE_CASCADE_TIMERS
	207	*R_TIMER_CTRL =
	208	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	209	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	210	IO_STATE( R_TIMER_CTRL, i1, clr) \|
	211	IO_STATE( R_TIMER_CTRL, tm1, run) \|
	212	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	213	IO_STATE( R_TIMER_CTRL, i0, clr) \|
	214	IO_STATE( R_TIMER_CTRL, tm0, run) \|
	215	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	216	#else
	217	*R_TIMER_CTRL = r_timer_ctrl_shadow \|
	218	IO_STATE(R_TIMER_CTRL, i0, clr);
	219	#endif
	220
	221	/* reset watchdog otherwise it resets us! */
1da177e4 LT	222	reset_watchdog();
1da177e4 LT	223
3244c77b JN	224	/* Update statistics. */
	225	update_process_times(user_mode(regs));
	226
1da177e4 LT	227	/* call the real timer interrupt handler */
1da177e4 LT	228
3171a030	229	do_timer(1);
1da177e4 LT	230
1da177e4 LT	231	cris_do_profile(regs); /* Save profiling information */
1da177e4 LT	232	return IRQ_HANDLED;
	233	}
	234
aa7135ff TG	235	/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
aa7135ff TG	236	* it needs to be IRQF_DISABLED to make the jiffies update work properly
1da177e4 LT	237	*/
1da177e4 LT	238
e5f71781 TG	239	static struct irqaction irq2 = {
	240	.handler = timer_interrupt,
	241	.flags = IRQF_SHARED \| IRQF_DISABLED,
e5f71781 TG	242	.name = "timer",
e5f71781 TG	243	};
1da177e4 LT	244
	245	void __init
	246	time_init(void)
	247	{
	248	/* probe for the RTC and read it if it exists
	249	* Before the RTC can be probed the loops_per_usec variable needs
	250	* to be initialized to make usleep work. A better value for
	251	* loops_per_usec is calculated by the kernel later once the
	252	* clock has started.
	253	*/
	254	loops_per_usec = 50;
	255
8eff8a5c	256	if(RTC_INIT() < 0)
1da177e4	257	have_rtc = 0;
8eff8a5c	258	else
1da177e4	259	have_rtc = 1;
1da177e4 LT	260
	261	/* Setup the etrax timers
	262	* Base frequency is 25000 hz, divider 250 -> 100 HZ
	263	* In normal mode, we use timer0, so timer1 is free. In cascade
	264	* mode (which we sometimes use for debugging) both timers are used.
	265	* Remember that linux/timex.h contains #defines that rely on the
	266	* timer settings below (hz and divide factor) !!!
	267	*/
	268
	269	#ifdef USE_CASCADE_TIMERS
	270	*R_TIMER_CTRL =
	271	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	272	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	273	IO_STATE( R_TIMER_CTRL, i1, nop) \|
	274	IO_STATE( R_TIMER_CTRL, tm1, stop_ld) \|
	275	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	276	IO_STATE( R_TIMER_CTRL, i0, nop) \|
	277	IO_STATE( R_TIMER_CTRL, tm0, stop_ld) \|
	278	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	279
	280	*R_TIMER_CTRL = r_timer_ctrl_shadow =
	281	IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) \|
	282	IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) \|
	283	IO_STATE( R_TIMER_CTRL, i1, nop) \|
	284	IO_STATE( R_TIMER_CTRL, tm1, run) \|
	285	IO_STATE( R_TIMER_CTRL, clksel1, cascade0) \|
	286	IO_STATE( R_TIMER_CTRL, i0, nop) \|
	287	IO_STATE( R_TIMER_CTRL, tm0, run) \|
	288	IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
	289	#else
	290	*R_TIMER_CTRL =
	291	IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) \|
	292	IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) \|
	293	IO_STATE(R_TIMER_CTRL, i1, nop) \|
	294	IO_STATE(R_TIMER_CTRL, tm1, stop_ld) \|
	295	IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) \|
	296	IO_STATE(R_TIMER_CTRL, i0, nop) \|
	297	IO_STATE(R_TIMER_CTRL, tm0, stop_ld) \|
	298	IO_STATE(R_TIMER_CTRL, clksel0, flexible);
	299
	300	*R_TIMER_CTRL = r_timer_ctrl_shadow =
	301	IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) \|
	302	IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) \|
	303	IO_STATE(R_TIMER_CTRL, i1, nop) \|
	304	IO_STATE(R_TIMER_CTRL, tm1, run) \|
	305	IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) \|
	306	IO_STATE(R_TIMER_CTRL, i0, nop) \|
	307	IO_STATE(R_TIMER_CTRL, tm0, run) \|
	308	IO_STATE(R_TIMER_CTRL, clksel0, flexible);
	309
	310	*R_TIMER_PRESCALE = PRESCALE_VALUE;
	311	#endif
	312
	313	*R_IRQ_MASK0_SET =
	314	IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
	315
	316	/* now actually register the timer irq handler that calls timer_interrupt() */
	317
	318	setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
	319
	320	/* enable watchdog if we should use one */
	321
	322	#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
	323	printk("Enabling watchdog...\n");
324	start_watchdog();
325
326	/* If we use the hardware watchdog, we want to trap it as an NMI
327	and dump registers before it resets us. For this to happen, we
328	must set the "m" NMI enable flag (which once set, is unset only
329	when an NMI is taken).
330
331	The same goes for the external NMI, but that doesn't have any
332	driver or infrastructure support yet. */
333	asm ("setf m");
334
335	*R_IRQ_MASK0_SET =
336	IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
337	*R_VECT_MASK_SET =
338	IO_STATE(R_VECT_MASK_SET, nmi, set);
339	#endif
340	}