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51533b61 MS |
1 | /* $Id: gpio.c,v 1.16 2005/06/19 17:06:49 starvik Exp $ |
2 | * | |
3 | * ETRAX CRISv32 general port I/O device | |
4 | * | |
5 | * Copyright (c) 1999, 2000, 2001, 2002, 2003 Axis Communications AB | |
6 | * | |
7 | * Authors: Bjorn Wesen (initial version) | |
8 | * Ola Knutsson (LED handling) | |
9 | * Johan Adolfsson (read/set directions, write, port G, | |
10 | * port to ETRAX FS. | |
11 | * | |
12 | * $Log: gpio.c,v $ | |
13 | * Revision 1.16 2005/06/19 17:06:49 starvik | |
14 | * Merge of Linux 2.6.12. | |
15 | * | |
16 | * Revision 1.15 2005/05/25 08:22:20 starvik | |
17 | * Changed GPIO port order to fit packages/devices/axis-2.4. | |
18 | * | |
19 | * Revision 1.14 2005/04/24 18:35:08 starvik | |
20 | * Updated with final register headers. | |
21 | * | |
22 | * Revision 1.13 2005/03/15 15:43:00 starvik | |
23 | * dev_id needs to be supplied for shared IRQs. | |
24 | * | |
25 | * Revision 1.12 2005/03/10 17:12:00 starvik | |
26 | * Protect alarm list with spinlock. | |
27 | * | |
28 | * Revision 1.11 2005/01/05 06:08:59 starvik | |
29 | * No need to do local_irq_disable after local_irq_save. | |
30 | * | |
31 | * Revision 1.10 2004/11/19 08:38:31 starvik | |
32 | * Removed old crap. | |
33 | * | |
34 | * Revision 1.9 2004/05/14 07:58:02 starvik | |
35 | * Merge of changes from 2.4 | |
36 | * | |
37 | * Revision 1.8 2003/09/11 07:29:50 starvik | |
38 | * Merge of Linux 2.6.0-test5 | |
39 | * | |
40 | * Revision 1.7 2003/07/10 13:25:46 starvik | |
41 | * Compiles for 2.5.74 | |
42 | * Lindented ethernet.c | |
43 | * | |
44 | * Revision 1.6 2003/07/04 08:27:46 starvik | |
45 | * Merge of Linux 2.5.74 | |
46 | * | |
47 | * Revision 1.5 2003/06/10 08:26:37 johana | |
48 | * Etrax -> ETRAX CRISv32 | |
49 | * | |
50 | * Revision 1.4 2003/06/05 14:22:48 johana | |
51 | * Initialise some_alarms. | |
52 | * | |
53 | * Revision 1.3 2003/06/05 10:15:46 johana | |
54 | * New INTR_VECT macros. | |
55 | * Enable interrupts in global config. | |
56 | * | |
57 | * Revision 1.2 2003/06/03 15:52:50 johana | |
58 | * Initial CRIS v32 version. | |
59 | * | |
60 | * Revision 1.1 2003/06/03 08:53:15 johana | |
61 | * Copy of os/lx25/arch/cris/arch-v10/drivers/gpio.c version 1.7. | |
62 | * | |
63 | */ | |
64 | ||
51533b61 MS |
65 | |
66 | #include <linux/module.h> | |
67 | #include <linux/sched.h> | |
68 | #include <linux/slab.h> | |
69 | #include <linux/ioport.h> | |
70 | #include <linux/errno.h> | |
71 | #include <linux/kernel.h> | |
72 | #include <linux/fs.h> | |
73 | #include <linux/string.h> | |
74 | #include <linux/poll.h> | |
75 | #include <linux/init.h> | |
76 | #include <linux/interrupt.h> | |
77 | #include <linux/spinlock.h> | |
78 | ||
79 | #include <asm/etraxgpio.h> | |
80 | #include <asm/arch/hwregs/reg_map.h> | |
81 | #include <asm/arch/hwregs/reg_rdwr.h> | |
82 | #include <asm/arch/hwregs/gio_defs.h> | |
83 | #include <asm/arch/hwregs/intr_vect_defs.h> | |
84 | #include <asm/io.h> | |
85 | #include <asm/system.h> | |
86 | #include <asm/irq.h> | |
87 | ||
88 | /* The following gio ports on ETRAX FS is available: | |
89 | * pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge | |
90 | * pb 18 bits | |
91 | * pc 18 bits | |
92 | * pd 18 bits | |
93 | * pe 18 bits | |
94 | * each port has a rw_px_dout, r_px_din and rw_px_oe register. | |
95 | */ | |
96 | ||
97 | #define GPIO_MAJOR 120 /* experimental MAJOR number */ | |
98 | ||
99 | #define D(x) | |
100 | ||
101 | #if 0 | |
102 | static int dp_cnt; | |
103 | #define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0) | |
104 | #else | |
105 | #define DP(x) | |
106 | #endif | |
107 | ||
108 | static char gpio_name[] = "etrax gpio"; | |
109 | ||
110 | #if 0 | |
111 | static wait_queue_head_t *gpio_wq; | |
112 | #endif | |
113 | ||
114 | static int gpio_ioctl(struct inode *inode, struct file *file, | |
115 | unsigned int cmd, unsigned long arg); | |
116 | static ssize_t gpio_write(struct file * file, const char * buf, size_t count, | |
117 | loff_t *off); | |
118 | static int gpio_open(struct inode *inode, struct file *filp); | |
119 | static int gpio_release(struct inode *inode, struct file *filp); | |
120 | static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait); | |
121 | ||
122 | /* private data per open() of this driver */ | |
123 | ||
124 | struct gpio_private { | |
125 | struct gpio_private *next; | |
126 | /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */ | |
127 | unsigned char clk_mask; | |
128 | unsigned char data_mask; | |
129 | unsigned char write_msb; | |
130 | unsigned char pad1; | |
131 | /* These fields are generic */ | |
132 | unsigned long highalarm, lowalarm; | |
133 | wait_queue_head_t alarm_wq; | |
134 | int minor; | |
135 | }; | |
136 | ||
137 | /* linked list of alarms to check for */ | |
138 | ||
139 | static struct gpio_private *alarmlist = 0; | |
140 | ||
141 | static int gpio_some_alarms = 0; /* Set if someone uses alarm */ | |
142 | static unsigned long gpio_pa_high_alarms = 0; | |
143 | static unsigned long gpio_pa_low_alarms = 0; | |
144 | ||
145 | static DEFINE_SPINLOCK(alarm_lock); | |
146 | ||
147 | #define NUM_PORTS (GPIO_MINOR_LAST+1) | |
148 | #define GIO_REG_RD_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg ) | |
149 | #define GIO_REG_WR_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg ) | |
150 | unsigned long led_dummy; | |
151 | ||
152 | static volatile unsigned long *data_out[NUM_PORTS] = { | |
153 | GIO_REG_WR_ADDR(rw_pa_dout), | |
154 | GIO_REG_WR_ADDR(rw_pb_dout), | |
155 | &led_dummy, | |
156 | GIO_REG_WR_ADDR(rw_pc_dout), | |
157 | GIO_REG_WR_ADDR(rw_pd_dout), | |
158 | GIO_REG_WR_ADDR(rw_pe_dout), | |
159 | }; | |
160 | ||
161 | static volatile unsigned long *data_in[NUM_PORTS] = { | |
162 | GIO_REG_RD_ADDR(r_pa_din), | |
163 | GIO_REG_RD_ADDR(r_pb_din), | |
164 | &led_dummy, | |
165 | GIO_REG_RD_ADDR(r_pc_din), | |
166 | GIO_REG_RD_ADDR(r_pd_din), | |
167 | GIO_REG_RD_ADDR(r_pe_din), | |
168 | }; | |
169 | ||
170 | static unsigned long changeable_dir[NUM_PORTS] = { | |
171 | CONFIG_ETRAX_PA_CHANGEABLE_DIR, | |
172 | CONFIG_ETRAX_PB_CHANGEABLE_DIR, | |
173 | 0, | |
174 | CONFIG_ETRAX_PC_CHANGEABLE_DIR, | |
175 | CONFIG_ETRAX_PD_CHANGEABLE_DIR, | |
176 | CONFIG_ETRAX_PE_CHANGEABLE_DIR, | |
177 | }; | |
178 | ||
179 | static unsigned long changeable_bits[NUM_PORTS] = { | |
180 | CONFIG_ETRAX_PA_CHANGEABLE_BITS, | |
181 | CONFIG_ETRAX_PB_CHANGEABLE_BITS, | |
182 | 0, | |
183 | CONFIG_ETRAX_PC_CHANGEABLE_BITS, | |
184 | CONFIG_ETRAX_PD_CHANGEABLE_BITS, | |
185 | CONFIG_ETRAX_PE_CHANGEABLE_BITS, | |
186 | }; | |
187 | ||
188 | static volatile unsigned long *dir_oe[NUM_PORTS] = { | |
189 | GIO_REG_WR_ADDR(rw_pa_oe), | |
190 | GIO_REG_WR_ADDR(rw_pb_oe), | |
191 | &led_dummy, | |
192 | GIO_REG_WR_ADDR(rw_pc_oe), | |
193 | GIO_REG_WR_ADDR(rw_pd_oe), | |
194 | GIO_REG_WR_ADDR(rw_pe_oe), | |
195 | }; | |
196 | ||
197 | ||
198 | ||
199 | static unsigned int | |
200 | gpio_poll(struct file *file, | |
201 | poll_table *wait) | |
202 | { | |
203 | unsigned int mask = 0; | |
204 | struct gpio_private *priv = (struct gpio_private *)file->private_data; | |
205 | unsigned long data; | |
206 | poll_wait(file, &priv->alarm_wq, wait); | |
207 | if (priv->minor == GPIO_MINOR_A) { | |
208 | reg_gio_rw_intr_cfg intr_cfg; | |
209 | unsigned long tmp; | |
210 | unsigned long flags; | |
211 | ||
212 | local_irq_save(flags); | |
213 | data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din, REG_RD(gio, regi_gio, r_pa_din)); | |
214 | /* PA has support for interrupt | |
215 | * lets activate high for those low and with highalarm set | |
216 | */ | |
217 | intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg); | |
218 | ||
219 | tmp = ~data & priv->highalarm & 0xFF; | |
220 | if (tmp & (1 << 0)) { | |
221 | intr_cfg.pa0 = regk_gio_hi; | |
222 | } | |
223 | if (tmp & (1 << 1)) { | |
224 | intr_cfg.pa1 = regk_gio_hi; | |
225 | } | |
226 | if (tmp & (1 << 2)) { | |
227 | intr_cfg.pa2 = regk_gio_hi; | |
228 | } | |
229 | if (tmp & (1 << 3)) { | |
230 | intr_cfg.pa3 = regk_gio_hi; | |
231 | } | |
232 | if (tmp & (1 << 4)) { | |
233 | intr_cfg.pa4 = regk_gio_hi; | |
234 | } | |
235 | if (tmp & (1 << 5)) { | |
236 | intr_cfg.pa5 = regk_gio_hi; | |
237 | } | |
238 | if (tmp & (1 << 6)) { | |
239 | intr_cfg.pa6 = regk_gio_hi; | |
240 | } | |
241 | if (tmp & (1 << 7)) { | |
242 | intr_cfg.pa7 = regk_gio_hi; | |
243 | } | |
244 | /* | |
245 | * lets activate low for those high and with lowalarm set | |
246 | */ | |
247 | tmp = data & priv->lowalarm & 0xFF; | |
248 | if (tmp & (1 << 0)) { | |
249 | intr_cfg.pa0 = regk_gio_lo; | |
250 | } | |
251 | if (tmp & (1 << 1)) { | |
252 | intr_cfg.pa1 = regk_gio_lo; | |
253 | } | |
254 | if (tmp & (1 << 2)) { | |
255 | intr_cfg.pa2 = regk_gio_lo; | |
256 | } | |
257 | if (tmp & (1 << 3)) { | |
258 | intr_cfg.pa3 = regk_gio_lo; | |
259 | } | |
260 | if (tmp & (1 << 4)) { | |
261 | intr_cfg.pa4 = regk_gio_lo; | |
262 | } | |
263 | if (tmp & (1 << 5)) { | |
264 | intr_cfg.pa5 = regk_gio_lo; | |
265 | } | |
266 | if (tmp & (1 << 6)) { | |
267 | intr_cfg.pa6 = regk_gio_lo; | |
268 | } | |
269 | if (tmp & (1 << 7)) { | |
270 | intr_cfg.pa7 = regk_gio_lo; | |
271 | } | |
272 | ||
273 | REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); | |
274 | local_irq_restore(flags); | |
275 | } else if (priv->minor <= GPIO_MINOR_E) | |
276 | data = *data_in[priv->minor]; | |
277 | else | |
278 | return 0; | |
279 | ||
280 | if ((data & priv->highalarm) || | |
281 | (~data & priv->lowalarm)) { | |
282 | mask = POLLIN|POLLRDNORM; | |
283 | } | |
284 | ||
285 | DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); | |
286 | return mask; | |
287 | } | |
288 | ||
289 | int etrax_gpio_wake_up_check(void) | |
290 | { | |
291 | struct gpio_private *priv = alarmlist; | |
292 | unsigned long data = 0; | |
293 | int ret = 0; | |
294 | while (priv) { | |
295 | data = *data_in[priv->minor]; | |
296 | if ((data & priv->highalarm) || | |
297 | (~data & priv->lowalarm)) { | |
298 | DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); | |
299 | wake_up_interruptible(&priv->alarm_wq); | |
300 | ret = 1; | |
301 | } | |
302 | priv = priv->next; | |
303 | } | |
304 | return ret; | |
305 | } | |
306 | ||
307 | static irqreturn_t | |
308 | gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
309 | { | |
310 | if (gpio_some_alarms) { | |
311 | return IRQ_RETVAL(etrax_gpio_wake_up_check()); | |
312 | } | |
313 | return IRQ_NONE; | |
314 | } | |
315 | ||
316 | static irqreturn_t | |
317 | gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
318 | { | |
319 | reg_gio_rw_intr_mask intr_mask; | |
320 | reg_gio_r_masked_intr masked_intr; | |
321 | reg_gio_rw_ack_intr ack_intr; | |
322 | unsigned long tmp; | |
323 | unsigned long tmp2; | |
324 | ||
325 | /* Find what PA interrupts are active */ | |
326 | masked_intr = REG_RD(gio, regi_gio, r_masked_intr); | |
327 | tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr); | |
328 | ||
329 | /* Find those that we have enabled */ | |
330 | spin_lock(&alarm_lock); | |
331 | tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms); | |
332 | spin_unlock(&alarm_lock); | |
333 | ||
334 | /* Ack them */ | |
335 | ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp); | |
336 | REG_WR(gio, regi_gio, rw_ack_intr, ack_intr); | |
337 | ||
338 | /* Disable those interrupts.. */ | |
339 | intr_mask = REG_RD(gio, regi_gio, rw_intr_mask); | |
340 | tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask); | |
341 | tmp2 &= ~tmp; | |
342 | intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2); | |
343 | REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); | |
344 | ||
345 | if (gpio_some_alarms) { | |
346 | return IRQ_RETVAL(etrax_gpio_wake_up_check()); | |
347 | } | |
348 | return IRQ_NONE; | |
349 | } | |
350 | ||
351 | ||
352 | static ssize_t gpio_write(struct file * file, const char * buf, size_t count, | |
353 | loff_t *off) | |
354 | { | |
355 | struct gpio_private *priv = (struct gpio_private *)file->private_data; | |
356 | unsigned char data, clk_mask, data_mask, write_msb; | |
357 | unsigned long flags; | |
358 | unsigned long shadow; | |
359 | volatile unsigned long *port; | |
360 | ssize_t retval = count; | |
361 | /* Only bits 0-7 may be used for write operations but allow all | |
362 | devices except leds... */ | |
363 | if (priv->minor == GPIO_MINOR_LEDS) { | |
364 | return -EFAULT; | |
365 | } | |
366 | ||
367 | if (!access_ok(VERIFY_READ, buf, count)) { | |
368 | return -EFAULT; | |
369 | } | |
370 | clk_mask = priv->clk_mask; | |
371 | data_mask = priv->data_mask; | |
372 | /* It must have been configured using the IO_CFG_WRITE_MODE */ | |
373 | /* Perhaps a better error code? */ | |
374 | if (clk_mask == 0 || data_mask == 0) { | |
375 | return -EPERM; | |
376 | } | |
377 | write_msb = priv->write_msb; | |
378 | D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb)); | |
379 | port = data_out[priv->minor]; | |
380 | ||
381 | while (count--) { | |
382 | int i; | |
383 | data = *buf++; | |
384 | if (priv->write_msb) { | |
385 | for (i = 7; i >= 0;i--) { | |
386 | local_irq_save(flags); | |
387 | shadow = *port; | |
388 | *port = shadow &= ~clk_mask; | |
389 | if (data & 1<<i) | |
390 | *port = shadow |= data_mask; | |
391 | else | |
392 | *port = shadow &= ~data_mask; | |
393 | /* For FPGA: min 5.0ns (DCC) before CCLK high */ | |
394 | *port = shadow |= clk_mask; | |
395 | local_irq_restore(flags); | |
396 | } | |
397 | } else { | |
398 | for (i = 0; i <= 7;i++) { | |
399 | local_irq_save(flags); | |
400 | shadow = *port; | |
401 | *port = shadow &= ~clk_mask; | |
402 | if (data & 1<<i) | |
403 | *port = shadow |= data_mask; | |
404 | else | |
405 | *port = shadow &= ~data_mask; | |
406 | /* For FPGA: min 5.0ns (DCC) before CCLK high */ | |
407 | *port = shadow |= clk_mask; | |
408 | local_irq_restore(flags); | |
409 | } | |
410 | } | |
411 | } | |
412 | return retval; | |
413 | } | |
414 | ||
415 | ||
416 | ||
417 | static int | |
418 | gpio_open(struct inode *inode, struct file *filp) | |
419 | { | |
420 | struct gpio_private *priv; | |
32ea086b | 421 | int p = iminor(inode); |
51533b61 MS |
422 | |
423 | if (p > GPIO_MINOR_LAST) | |
424 | return -EINVAL; | |
425 | ||
5cbded58 | 426 | priv = kmalloc(sizeof(struct gpio_private), |
51533b61 MS |
427 | GFP_KERNEL); |
428 | ||
429 | if (!priv) | |
430 | return -ENOMEM; | |
431 | ||
432 | priv->minor = p; | |
433 | ||
434 | /* initialize the io/alarm struct and link it into our alarmlist */ | |
435 | ||
436 | priv->next = alarmlist; | |
437 | alarmlist = priv; | |
438 | priv->clk_mask = 0; | |
439 | priv->data_mask = 0; | |
440 | priv->highalarm = 0; | |
441 | priv->lowalarm = 0; | |
442 | init_waitqueue_head(&priv->alarm_wq); | |
443 | ||
444 | filp->private_data = (void *)priv; | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | static int | |
450 | gpio_release(struct inode *inode, struct file *filp) | |
451 | { | |
452 | struct gpio_private *p = alarmlist; | |
453 | struct gpio_private *todel = (struct gpio_private *)filp->private_data; | |
454 | /* local copies while updating them: */ | |
455 | unsigned long a_high, a_low; | |
456 | unsigned long some_alarms; | |
457 | ||
458 | /* unlink from alarmlist and free the private structure */ | |
459 | ||
460 | if (p == todel) { | |
461 | alarmlist = todel->next; | |
462 | } else { | |
463 | while (p->next != todel) | |
464 | p = p->next; | |
465 | p->next = todel->next; | |
466 | } | |
467 | ||
468 | kfree(todel); | |
469 | /* Check if there are still any alarms set */ | |
470 | p = alarmlist; | |
471 | some_alarms = 0; | |
472 | a_high = 0; | |
473 | a_low = 0; | |
474 | while (p) { | |
475 | if (p->minor == GPIO_MINOR_A) { | |
476 | a_high |= p->highalarm; | |
477 | a_low |= p->lowalarm; | |
478 | } | |
479 | ||
480 | if (p->highalarm | p->lowalarm) { | |
481 | some_alarms = 1; | |
482 | } | |
483 | p = p->next; | |
484 | } | |
485 | ||
486 | spin_lock(&alarm_lock); | |
487 | gpio_some_alarms = some_alarms; | |
488 | gpio_pa_high_alarms = a_high; | |
489 | gpio_pa_low_alarms = a_low; | |
490 | spin_unlock(&alarm_lock); | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | /* Main device API. ioctl's to read/set/clear bits, as well as to | |
496 | * set alarms to wait for using a subsequent select(). | |
497 | */ | |
498 | ||
499 | unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg) | |
500 | { | |
501 | /* Set direction 0=unchanged 1=input, | |
502 | * return mask with 1=input | |
503 | */ | |
504 | unsigned long flags; | |
505 | unsigned long dir_shadow; | |
506 | ||
507 | local_irq_save(flags); | |
508 | dir_shadow = *dir_oe[priv->minor]; | |
509 | dir_shadow &= ~(arg & changeable_dir[priv->minor]); | |
510 | *dir_oe[priv->minor] = dir_shadow; | |
511 | local_irq_restore(flags); | |
512 | ||
513 | if (priv->minor == GPIO_MINOR_A) | |
514 | dir_shadow ^= 0xFF; /* Only 8 bits */ | |
515 | else | |
516 | dir_shadow ^= 0x3FFFF; /* Only 18 bits */ | |
517 | return dir_shadow; | |
518 | ||
519 | } /* setget_input */ | |
520 | ||
521 | unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg) | |
522 | { | |
523 | unsigned long flags; | |
524 | unsigned long dir_shadow; | |
525 | ||
526 | local_irq_save(flags); | |
527 | dir_shadow = *dir_oe[priv->minor]; | |
528 | dir_shadow |= (arg & changeable_dir[priv->minor]); | |
529 | *dir_oe[priv->minor] = dir_shadow; | |
530 | local_irq_restore(flags); | |
531 | return dir_shadow; | |
532 | } /* setget_output */ | |
533 | ||
534 | static int | |
535 | gpio_leds_ioctl(unsigned int cmd, unsigned long arg); | |
536 | ||
537 | static int | |
538 | gpio_ioctl(struct inode *inode, struct file *file, | |
539 | unsigned int cmd, unsigned long arg) | |
540 | { | |
541 | unsigned long flags; | |
542 | unsigned long val; | |
543 | unsigned long shadow; | |
544 | struct gpio_private *priv = (struct gpio_private *)file->private_data; | |
545 | if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) { | |
546 | return -EINVAL; | |
547 | } | |
548 | ||
549 | switch (_IOC_NR(cmd)) { | |
550 | case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ | |
551 | // read the port | |
552 | return *data_in[priv->minor]; | |
553 | break; | |
554 | case IO_SETBITS: | |
555 | local_irq_save(flags); | |
556 | if (arg & 0x04) | |
557 | printk("GPIO SET 2\n"); | |
558 | // set changeable bits with a 1 in arg | |
559 | shadow = *data_out[priv->minor]; | |
560 | shadow |= (arg & changeable_bits[priv->minor]); | |
561 | *data_out[priv->minor] = shadow; | |
562 | local_irq_restore(flags); | |
563 | break; | |
564 | case IO_CLRBITS: | |
565 | local_irq_save(flags); | |
566 | if (arg & 0x04) | |
567 | printk("GPIO CLR 2\n"); | |
568 | // clear changeable bits with a 1 in arg | |
569 | shadow = *data_out[priv->minor]; | |
570 | shadow &= ~(arg & changeable_bits[priv->minor]); | |
571 | *data_out[priv->minor] = shadow; | |
572 | local_irq_restore(flags); | |
573 | break; | |
574 | case IO_HIGHALARM: | |
575 | // set alarm when bits with 1 in arg go high | |
576 | priv->highalarm |= arg; | |
577 | spin_lock(&alarm_lock); | |
578 | gpio_some_alarms = 1; | |
579 | if (priv->minor == GPIO_MINOR_A) { | |
580 | gpio_pa_high_alarms |= arg; | |
581 | } | |
582 | spin_unlock(&alarm_lock); | |
583 | break; | |
584 | case IO_LOWALARM: | |
585 | // set alarm when bits with 1 in arg go low | |
586 | priv->lowalarm |= arg; | |
587 | spin_lock(&alarm_lock); | |
588 | gpio_some_alarms = 1; | |
589 | if (priv->minor == GPIO_MINOR_A) { | |
590 | gpio_pa_low_alarms |= arg; | |
591 | } | |
592 | spin_unlock(&alarm_lock); | |
593 | break; | |
594 | case IO_CLRALARM: | |
595 | // clear alarm for bits with 1 in arg | |
596 | priv->highalarm &= ~arg; | |
597 | priv->lowalarm &= ~arg; | |
598 | spin_lock(&alarm_lock); | |
599 | if (priv->minor == GPIO_MINOR_A) { | |
600 | if (gpio_pa_high_alarms & arg || | |
601 | gpio_pa_low_alarms & arg) { | |
602 | /* Must update the gpio_pa_*alarms masks */ | |
603 | } | |
604 | } | |
605 | spin_unlock(&alarm_lock); | |
606 | break; | |
607 | case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ | |
608 | /* Read direction 0=input 1=output */ | |
609 | return *dir_oe[priv->minor]; | |
610 | case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ | |
611 | /* Set direction 0=unchanged 1=input, | |
612 | * return mask with 1=input | |
613 | */ | |
614 | return setget_input(priv, arg); | |
615 | break; | |
616 | case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ | |
617 | /* Set direction 0=unchanged 1=output, | |
618 | * return mask with 1=output | |
619 | */ | |
620 | return setget_output(priv, arg); | |
621 | ||
622 | case IO_CFG_WRITE_MODE: | |
623 | { | |
624 | unsigned long dir_shadow; | |
625 | dir_shadow = *dir_oe[priv->minor]; | |
626 | ||
627 | priv->clk_mask = arg & 0xFF; | |
628 | priv->data_mask = (arg >> 8) & 0xFF; | |
629 | priv->write_msb = (arg >> 16) & 0x01; | |
630 | /* Check if we're allowed to change the bits and | |
631 | * the direction is correct | |
632 | */ | |
633 | if (!((priv->clk_mask & changeable_bits[priv->minor]) && | |
634 | (priv->data_mask & changeable_bits[priv->minor]) && | |
635 | (priv->clk_mask & dir_shadow) && | |
636 | (priv->data_mask & dir_shadow))) | |
637 | { | |
638 | priv->clk_mask = 0; | |
639 | priv->data_mask = 0; | |
640 | return -EPERM; | |
641 | } | |
642 | break; | |
643 | } | |
644 | case IO_READ_INBITS: | |
645 | /* *arg is result of reading the input pins */ | |
646 | val = *data_in[priv->minor]; | |
647 | if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) | |
648 | return -EFAULT; | |
649 | return 0; | |
650 | break; | |
651 | case IO_READ_OUTBITS: | |
652 | /* *arg is result of reading the output shadow */ | |
653 | val = *data_out[priv->minor]; | |
654 | if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) | |
655 | return -EFAULT; | |
656 | break; | |
657 | case IO_SETGET_INPUT: | |
658 | /* bits set in *arg is set to input, | |
659 | * *arg updated with current input pins. | |
660 | */ | |
661 | if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) | |
662 | return -EFAULT; | |
663 | val = setget_input(priv, val); | |
664 | if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) | |
665 | return -EFAULT; | |
666 | break; | |
667 | case IO_SETGET_OUTPUT: | |
668 | /* bits set in *arg is set to output, | |
669 | * *arg updated with current output pins. | |
670 | */ | |
671 | if (copy_from_user(&val, (unsigned long*)arg, sizeof(val))) | |
672 | return -EFAULT; | |
673 | val = setget_output(priv, val); | |
674 | if (copy_to_user((unsigned long*)arg, &val, sizeof(val))) | |
675 | return -EFAULT; | |
676 | break; | |
677 | default: | |
678 | if (priv->minor == GPIO_MINOR_LEDS) | |
679 | return gpio_leds_ioctl(cmd, arg); | |
680 | else | |
681 | return -EINVAL; | |
682 | } /* switch */ | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static int | |
688 | gpio_leds_ioctl(unsigned int cmd, unsigned long arg) | |
689 | { | |
690 | unsigned char green; | |
691 | unsigned char red; | |
692 | ||
693 | switch (_IOC_NR(cmd)) { | |
694 | case IO_LEDACTIVE_SET: | |
695 | green = ((unsigned char) arg) & 1; | |
696 | red = (((unsigned char) arg) >> 1) & 1; | |
697 | LED_ACTIVE_SET_G(green); | |
698 | LED_ACTIVE_SET_R(red); | |
699 | break; | |
700 | ||
701 | default: | |
702 | return -EINVAL; | |
703 | } /* switch */ | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
5dfe4c96 | 708 | const struct file_operations gpio_fops = { |
51533b61 MS |
709 | .owner = THIS_MODULE, |
710 | .poll = gpio_poll, | |
711 | .ioctl = gpio_ioctl, | |
712 | .write = gpio_write, | |
713 | .open = gpio_open, | |
714 | .release = gpio_release, | |
715 | }; | |
716 | ||
717 | ||
718 | /* main driver initialization routine, called from mem.c */ | |
719 | ||
720 | static __init int | |
721 | gpio_init(void) | |
722 | { | |
723 | int res; | |
724 | reg_intr_vect_rw_mask intr_mask; | |
725 | ||
726 | /* do the formalities */ | |
727 | ||
728 | res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); | |
729 | if (res < 0) { | |
730 | printk(KERN_ERR "gpio: couldn't get a major number.\n"); | |
731 | return res; | |
732 | } | |
733 | ||
734 | /* Clear all leds */ | |
735 | LED_NETWORK_SET(0); | |
736 | LED_ACTIVE_SET(0); | |
737 | LED_DISK_READ(0); | |
738 | LED_DISK_WRITE(0); | |
739 | ||
740 | printk("ETRAX FS GPIO driver v2.5, (c) 2003-2005 Axis Communications AB\n"); | |
741 | /* We call etrax_gpio_wake_up_check() from timer interrupt and | |
742 | * from cpu_idle() in kernel/process.c | |
743 | * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms | |
744 | * in some tests. | |
745 | */ | |
746 | if (request_irq(TIMER_INTR_VECT, gpio_poll_timer_interrupt, | |
aa7135ff | 747 | IRQF_SHARED | IRQF_DISABLED,"gpio poll", &alarmlist)) { |
51533b61 MS |
748 | printk("err: timer0 irq for gpio\n"); |
749 | } | |
750 | if (request_irq(GEN_IO_INTR_VECT, gpio_pa_interrupt, | |
aa7135ff | 751 | IRQF_SHARED | IRQF_DISABLED,"gpio PA", &alarmlist)) { |
51533b61 MS |
752 | printk("err: PA irq for gpio\n"); |
753 | } | |
754 | /* enable the gio and timer irq in global config */ | |
755 | intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); | |
756 | intr_mask.timer = 1; | |
757 | intr_mask.gen_io = 1; | |
758 | REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); | |
759 | ||
760 | return res; | |
761 | } | |
762 | ||
763 | /* this makes sure that gpio_init is called during kernel boot */ | |
764 | ||
765 | module_init(gpio_init); |