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Merge branch 'linus' into core/softlockup
[mirror_ubuntu-hirsute-kernel.git] / arch / cris / arch-v32 / drivers / sync_serial.c
CommitLineData
51533b61 1/*
e908dfc3 2 * Simple synchronous serial port driver for ETRAX FS and Artpec-3.
51533b61
MS		 3 *
4 * Copyright (c) 2005 Axis Communications AB
5 *
6 * Author: Mikael Starvik
7 *
8 */
9
10#include <linux/module.h>
11#include <linux/kernel.h>
51533b61
MS		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/major.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
0c401df3 17#include <linux/smp_lock.h>
51533b61
MS		 18#include <linux/interrupt.h>
19#include <linux/poll.h>
20#include <linux/init.h>
21#include <linux/timer.h>
22#include <linux/spinlock.h>
23
24#include <asm/io.h>
e908dfc3
JN		 25#include <dma.h>
26#include <pinmux.h>
27#include <hwregs/reg_rdwr.h>
28#include <hwregs/sser_defs.h>
29#include <hwregs/dma_defs.h>
30#include <hwregs/dma.h>
31#include <hwregs/intr_vect_defs.h>
32#include <hwregs/intr_vect.h>
33#include <hwregs/reg_map.h>
51533b61
MS		 34#include <asm/sync_serial.h>
35
e908dfc3 36
51533b61
MS		 37/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
38/* */
39/* Three DMA descriptors are linked together. Each DMA descriptor is */
40/* responsible for port->bufchunk of a common buffer. */
41/* */
42/* +---------------------------------------------+ */
43/* | +----------+ +----------+ +----------+ | */
44/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
45/* +----------+ +----------+ +----------+ */
46/* | | | */
47/* v v v */
48/* +-------------------------------------+ */
49/* | BUFFER | */
50/* +-------------------------------------+ */
51/* |<- data_avail ->| */
52/* readp writep */
53/* */
54/* If the application keeps up the pace readp will be right after writep.*/
55/* If the application can't keep the pace we have to throw away data. */
56/* The idea is that readp should be ready with the data pointed out by */
57/* Descr[i] when the DMA has filled in Descr[i+1]. */
58/* Otherwise we will discard */
59/* the rest of the data pointed out by Descr1 and set readp to the start */
60/* of Descr2 */
61
62#define SYNC_SERIAL_MAJOR 125
63
64/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
65/* words can be handled */
66#define IN_BUFFER_SIZE 12288
67#define IN_DESCR_SIZE 256
e908dfc3
JN		 68#define NBR_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
69
70#define OUT_BUFFER_SIZE 1024*8
71#define NBR_OUT_DESCR 8
51533b61
MS		 72
73#define DEFAULT_FRAME_RATE 0
74#define DEFAULT_WORD_RATE 7
75
76/* NOTE: Enabling some debug will likely cause overrun or underrun,
77 * especially if manual mode is use.
78 */
79#define DEBUG(x)
80#define DEBUGREAD(x)
81#define DEBUGWRITE(x)
82#define DEBUGPOLL(x)
83#define DEBUGRXINT(x)
84#define DEBUGTXINT(x)
e908dfc3
JN		 85#define DEBUGTRDMA(x)
86#define DEBUGOUTBUF(x)
51533b61
MS		 87
88typedef struct sync_port
89{
90 reg_scope_instances regi_sser;
91 reg_scope_instances regi_dmain;
92 reg_scope_instances regi_dmaout;
93
94 char started; /* 1 if port has been started */
95 char port_nbr; /* Port 0 or 1 */
96 char busy; /* 1 if port is busy */
97
98 char enabled; /* 1 if port is enabled */
99 char use_dma; /* 1 if port uses dma */
100 char tr_running;
101
102 char init_irqs;
103 int output;
104 int input;
105
e908dfc3
JN		 106 /* Next byte to be read by application */
107 volatile unsigned char *volatile readp;
108 /* Next byte to be written by etrax */
109 volatile unsigned char *volatile writep;
110
51533b61
MS		 111 unsigned int in_buffer_size;
112 unsigned int inbufchunk;
113 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
114 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
115 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
116 struct dma_descr_data* next_rx_desc;
117 struct dma_descr_data* prev_rx_desc;
e908dfc3
JN		 118
119 /* Pointer to the first available descriptor in the ring,
120 * unless active_tr_descr == catch_tr_descr and a dma
121 * transfer is active */
122 struct dma_descr_data *active_tr_descr;
123
124 /* Pointer to the first allocated descriptor in the ring */
125 struct dma_descr_data *catch_tr_descr;
126
127 /* Pointer to the descriptor with the current end-of-list */
128 struct dma_descr_data *prev_tr_descr;
51533b61
MS		 129 int full;
130
e908dfc3
JN		 131 /* Pointer to the first byte being read by DMA
132 * or current position in out_buffer if not using DMA. */
133 unsigned char *out_rd_ptr;
134
135 /* Number of bytes currently locked for being read by DMA */
136 int out_buf_count;
137
138 dma_descr_data in_descr[NBR_IN_DESCR] __attribute__ ((__aligned__(16)));
51533b61 139 dma_descr_context in_context __attribute__ ((__aligned__(32)));
e908dfc3
JN		 140 dma_descr_data out_descr[NBR_OUT_DESCR]
141 __attribute__ ((__aligned__(16)));
51533b61
MS		 142 dma_descr_context out_context __attribute__ ((__aligned__(32)));
143 wait_queue_head_t out_wait_q;
144 wait_queue_head_t in_wait_q;
145
146 spinlock_t lock;
147} sync_port;
148
149static int etrax_sync_serial_init(void);
150static void initialize_port(int portnbr);
151static inline int sync_data_avail(struct sync_port *port);
152
153static int sync_serial_open(struct inode *, struct file*);
154static int sync_serial_release(struct inode*, struct file*);
155static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
156
157static int sync_serial_ioctl(struct inode*, struct file*,
158 unsigned int cmd, unsigned long arg);
159static ssize_t sync_serial_write(struct file * file, const char * buf,
160 size_t count, loff_t *ppos);
161static ssize_t sync_serial_read(struct file *file, char *buf,
162 size_t count, loff_t *ppos);
163
164#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
165 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
166 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
167 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
168#define SYNC_SER_DMA
169#endif
170
171static void send_word(sync_port* port);
e908dfc3 172static void start_dma_out(struct sync_port *port, const char *data, int count);
51533b61
MS		 173static void start_dma_in(sync_port* port);
174#ifdef SYNC_SER_DMA
e908dfc3
JN		 175static irqreturn_t tr_interrupt(int irq, void *dev_id);
176static irqreturn_t rx_interrupt(int irq, void *dev_id);
51533b61
MS		 177#endif
178
179#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
180 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
181 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
182 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
183#define SYNC_SER_MANUAL
184#endif
185#ifdef SYNC_SER_MANUAL
e908dfc3
JN		 186static irqreturn_t manual_interrupt(int irq, void *dev_id);
187#endif
188
189#ifdef CONFIG_ETRAXFS /* ETRAX FS */
190#define OUT_DMA_NBR 4
191#define IN_DMA_NBR 5
192#define PINMUX_SSER pinmux_sser0
193#define SYNCSER_INST regi_sser0
194#define SYNCSER_INTR_VECT SSER0_INTR_VECT
195#define OUT_DMA_INST regi_dma4
196#define IN_DMA_INST regi_dma5
197#define DMA_OUT_INTR_VECT DMA4_INTR_VECT
198#define DMA_IN_INTR_VECT DMA5_INTR_VECT
199#define REQ_DMA_SYNCSER dma_sser0
200#else /* Artpec-3 */
201#define OUT_DMA_NBR 6
202#define IN_DMA_NBR 7
203#define PINMUX_SSER pinmux_sser
204#define SYNCSER_INST regi_sser
205#define SYNCSER_INTR_VECT SSER_INTR_VECT
206#define OUT_DMA_INST regi_dma6
207#define IN_DMA_INST regi_dma7
208#define DMA_OUT_INTR_VECT DMA6_INTR_VECT
209#define DMA_IN_INTR_VECT DMA7_INTR_VECT
210#define REQ_DMA_SYNCSER dma_sser
51533b61
MS		 211#endif
212
213/* The ports */
214static struct sync_port ports[]=
215{
216 {
e908dfc3
JN		 217 .regi_sser = SYNCSER_INST,
218 .regi_dmaout = OUT_DMA_INST,
219 .regi_dmain = IN_DMA_INST,
51533b61
MS		 220#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
221 .use_dma = 1,
222#else
223 .use_dma = 0,
224#endif
e908dfc3
JN		 225 }
226#ifdef CONFIG_ETRAXFS
227 ,
228
51533b61
MS		 229 {
230 .regi_sser = regi_sser1,
231 .regi_dmaout = regi_dma6,
232 .regi_dmain = regi_dma7,
233#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
234 .use_dma = 1,
235#else
236 .use_dma = 0,
237#endif
238 }
e908dfc3 239#endif
51533b61
MS		 240};
241
e908dfc3 242#define NBR_PORTS ARRAY_SIZE(ports)
51533b61 243
5dfe4c96 244static const struct file_operations sync_serial_fops = {
51533b61
MS		 245 .owner = THIS_MODULE,
246 .write = sync_serial_write,
247 .read = sync_serial_read,
248 .poll = sync_serial_poll,
249 .ioctl = sync_serial_ioctl,
250 .open = sync_serial_open,
251 .release = sync_serial_release
252};
253
254static int __init etrax_sync_serial_init(void)
255{
256 ports[0].enabled = 0;
e908dfc3 257#ifdef CONFIG_ETRAXFS
51533b61 258 ports[1].enabled = 0;
e908dfc3
JN		 259#endif
260 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
261 &sync_serial_fops) < 0) {
262 printk(KERN_WARNING
263 "Unable to get major for synchronous serial port\n");
51533b61
MS		 264 return -EBUSY;
265 }
266
267 /* Initialize Ports */
268#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
e908dfc3
JN		 269 if (crisv32_pinmux_alloc_fixed(PINMUX_SSER)) {
270 printk(KERN_WARNING
271 "Unable to alloc pins for synchronous serial port 0\n");
51533b61
MS		 272 return -EIO;
273 }
274 ports[0].enabled = 1;
275 initialize_port(0);
276#endif
277
278#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
e908dfc3
JN		 279 if (crisv32_pinmux_alloc_fixed(pinmux_sser1)) {
280 printk(KERN_WARNING
281 "Unable to alloc pins for synchronous serial port 0\n");
51533b61
MS		 282 return -EIO;
283 }
284 ports[1].enabled = 1;
285 initialize_port(1);
286#endif
287
e908dfc3
JN		 288#ifdef CONFIG_ETRAXFS
289 printk(KERN_INFO "ETRAX FS synchronous serial port driver\n");
290#else
291 printk(KERN_INFO "Artpec-3 synchronous serial port driver\n");
292#endif
51533b61
MS		 293 return 0;
294}
295
296static void __init initialize_port(int portnbr)
297{
e908dfc3
JN		 298 int __attribute__((unused)) i;
299 struct sync_port *port = &ports[portnbr];
51533b61
MS		 300 reg_sser_rw_cfg cfg = {0};
301 reg_sser_rw_frm_cfg frm_cfg = {0};
302 reg_sser_rw_tr_cfg tr_cfg = {0};
303 reg_sser_rw_rec_cfg rec_cfg = {0};
304
e908dfc3 305 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
51533b61
MS		 306
307 port->port_nbr = portnbr;
308 port->init_irqs = 1;
309
e908dfc3
JN		 310 port->out_rd_ptr = port->out_buffer;
311 port->out_buf_count = 0;
312
51533b61
MS		 313 port->output = 1;
314 port->input = 0;
315
316 port->readp = port->flip;
317 port->writep = port->flip;
318 port->in_buffer_size = IN_BUFFER_SIZE;
319 port->inbufchunk = IN_DESCR_SIZE;
320 port->next_rx_desc = &port->in_descr[0];
e908dfc3 321 port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR-1];
51533b61
MS		 322 port->prev_rx_desc->eol = 1;
323
324 init_waitqueue_head(&port->out_wait_q);
325 init_waitqueue_head(&port->in_wait_q);
326
327 spin_lock_init(&port->lock);
328
329 cfg.out_clk_src = regk_sser_intern_clk;
330 cfg.out_clk_pol = regk_sser_pos;
331 cfg.clk_od_mode = regk_sser_no;
332 cfg.clk_dir = regk_sser_out;
333 cfg.gate_clk = regk_sser_no;
334 cfg.base_freq = regk_sser_f29_493;
335 cfg.clk_div = 256;
336 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
337
338 frm_cfg.wordrate = DEFAULT_WORD_RATE;
339 frm_cfg.type = regk_sser_edge;
340 frm_cfg.frame_pin_dir = regk_sser_out;
341 frm_cfg.frame_pin_use = regk_sser_frm;
342 frm_cfg.status_pin_dir = regk_sser_in;
343 frm_cfg.status_pin_use = regk_sser_hold;
344 frm_cfg.out_on = regk_sser_tr;
345 frm_cfg.tr_delay = 1;
346 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
347
348 tr_cfg.urun_stop = regk_sser_no;
349 tr_cfg.sample_size = 7;
350 tr_cfg.sh_dir = regk_sser_msbfirst;
351 tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
e908dfc3 352#if 0
51533b61
MS		 353 tr_cfg.rate_ctrl = regk_sser_bulk;
354 tr_cfg.data_pin_use = regk_sser_dout;
e908dfc3
JN		 355#else
356 tr_cfg.rate_ctrl = regk_sser_iso;
357 tr_cfg.data_pin_use = regk_sser_dout;
358#endif
51533b61
MS		 359 tr_cfg.bulk_wspace = 1;
360 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
361
362 rec_cfg.sample_size = 7;
363 rec_cfg.sh_dir = regk_sser_msbfirst;
364 rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
365 rec_cfg.fifo_thr = regk_sser_inf;
366 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
e908dfc3
JN		 367
368#ifdef SYNC_SER_DMA
369 /* Setup the descriptor ring for dma out/transmit. */
370 for (i = 0; i < NBR_OUT_DESCR; i++) {
371 port->out_descr[i].wait = 0;
372 port->out_descr[i].intr = 1;
373 port->out_descr[i].eol = 0;
374 port->out_descr[i].out_eop = 0;
375 port->out_descr[i].next =
376 (dma_descr_data *)virt_to_phys(&port->out_descr[i+1]);
377 }
378
379 /* Create a ring from the list. */
380 port->out_descr[NBR_OUT_DESCR-1].next =
381 (dma_descr_data *)virt_to_phys(&port->out_descr[0]);
382
383 /* Setup context for traversing the ring. */
384 port->active_tr_descr = &port->out_descr[0];
385 port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1];
386 port->catch_tr_descr = &port->out_descr[0];
387#endif
51533b61
MS		 388}
389
390static inline int sync_data_avail(struct sync_port *port)
391{
392 int avail;
393 unsigned char *start;
394 unsigned char *end;
395
396 start = (unsigned char*)port->readp; /* cast away volatile */
397 end = (unsigned char*)port->writep; /* cast away volatile */
398 /* 0123456789 0123456789
399 * ----- - -----
400 * ^rp ^wp ^wp ^rp
401 */
402
e908dfc3 403 if (end >= start)
51533b61
MS		 404 avail = end - start;
405 else
406 avail = port->in_buffer_size - (start - end);
407 return avail;
408}
409
410static inline int sync_data_avail_to_end(struct sync_port *port)
411{
412 int avail;
413 unsigned char *start;
414 unsigned char *end;
415
416 start = (unsigned char*)port->readp; /* cast away volatile */
417 end = (unsigned char*)port->writep; /* cast away volatile */
418 /* 0123456789 0123456789
419 * ----- -----
420 * ^rp ^wp ^wp ^rp
421 */
422
e908dfc3 423 if (end >= start)
51533b61
MS		 424 avail = end - start;
425 else
426 avail = port->flip + port->in_buffer_size - start;
427 return avail;
428}
429
430static int sync_serial_open(struct inode *inode, struct file *file)
431{
32ea086b 432 int dev = iminor(inode);
0c401df3 433 int ret = -EBUSY;
e908dfc3 434 sync_port *port;
51533b61
MS		 435 reg_dma_rw_cfg cfg = {.en = regk_dma_yes};
436 reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes};
437
0c401df3 438 lock_kernel();
e908dfc3 439 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
51533b61 440
e908dfc3 441 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61 442 {
e908dfc3 443 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
0c401df3
JC		 444 ret = -ENODEV;
445 goto out;
51533b61
MS		 446 }
447 port = &ports[dev];
448 /* Allow open this device twice (assuming one reader and one writer) */
449 if (port->busy == 2)
450 {
e908dfc3 451 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
0c401df3 452 goto out;
51533b61 453 }
e908dfc3
JN		 454
455
51533b61
MS		 456 if (port->init_irqs) {
457 if (port->use_dma) {
e908dfc3 458 if (port == &ports[0]) {
51533b61 459#ifdef SYNC_SER_DMA
e908dfc3
JN		 460 if (request_irq(DMA_OUT_INTR_VECT,
461 tr_interrupt,
462 0,
463 "synchronous serial 0 dma tr",
464 &ports[0])) {
51533b61 465 printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
0c401df3 466 goto out;
e908dfc3
JN		 467 } else if (request_irq(DMA_IN_INTR_VECT,
468 rx_interrupt,
469 0,
470 "synchronous serial 1 dma rx",
471 &ports[0])) {
472 free_irq(DMA_OUT_INTR_VECT, &port[0]);
51533b61 473 printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
0c401df3 474 goto out;
e908dfc3
JN		 475 } else if (crisv32_request_dma(OUT_DMA_NBR,
476 "synchronous serial 0 dma tr",
477 DMA_VERBOSE_ON_ERROR,
478 0,
479 REQ_DMA_SYNCSER)) {
480 free_irq(DMA_OUT_INTR_VECT, &port[0]);
481 free_irq(DMA_IN_INTR_VECT, &port[0]);
51533b61 482 printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel");
0c401df3 483 goto out;
e908dfc3
JN		 484 } else if (crisv32_request_dma(IN_DMA_NBR,
485 "synchronous serial 0 dma rec",
486 DMA_VERBOSE_ON_ERROR,
487 0,
488 REQ_DMA_SYNCSER)) {
489 crisv32_free_dma(OUT_DMA_NBR);
490 free_irq(DMA_OUT_INTR_VECT, &port[0]);
491 free_irq(DMA_IN_INTR_VECT, &port[0]);
51533b61 492 printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel");
0c401df3 493 goto out;
51533b61
MS		 494 }
495#endif
496 }
e908dfc3
JN		 497#ifdef CONFIG_ETRAXFS
498 else if (port == &ports[1]) {
51533b61
MS		 499#ifdef SYNC_SER_DMA
500 if (request_irq(DMA6_INTR_VECT,
501 tr_interrupt,
502 0,
503 "synchronous serial 1 dma tr",
504 &ports[1])) {
505 printk(KERN_CRIT "Can't allocate sync serial port 1 IRQ");
0c401df3 506 goto out;
51533b61
MS		 507 } else if (request_irq(DMA7_INTR_VECT,
508 rx_interrupt,
509 0,
510 "synchronous serial 1 dma rx",
511 &ports[1])) {
512 free_irq(DMA6_INTR_VECT, &ports[1]);
513 printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ");
0c401df3 514 goto out;
e908dfc3
JN		 515 } else if (crisv32_request_dma(
516 SYNC_SER1_TX_DMA_NBR,
517 "synchronous serial 1 dma tr",
518 DMA_VERBOSE_ON_ERROR,
519 0,
520 dma_sser1)) {
521 free_irq(DMA6_INTR_VECT, &ports[1]);
522 free_irq(DMA7_INTR_VECT, &ports[1]);
51533b61 523 printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel");
0c401df3 524 goto out;
e908dfc3
JN		 525 } else if (crisv32_request_dma(
526 SYNC_SER1_RX_DMA_NBR,
527 "synchronous serial 3 dma rec",
528 DMA_VERBOSE_ON_ERROR,
529 0,
530 dma_sser1)) {
51533b61
MS		 531 crisv32_free_dma(SYNC_SER1_TX_DMA_NBR);
532 free_irq(DMA6_INTR_VECT, &ports[1]);
533 free_irq(DMA7_INTR_VECT, &ports[1]);
534 printk(KERN_CRIT "Can't allocate sync serial port 3 RX DMA channel");
0c401df3 535 goto out;
51533b61
MS		 536 }
537#endif
538 }
e908dfc3 539#endif
51533b61
MS		 540 /* Enable DMAs */
541 REG_WR(dma, port->regi_dmain, rw_cfg, cfg);
542 REG_WR(dma, port->regi_dmaout, rw_cfg, cfg);
543 /* Enable DMA IRQs */
544 REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask);
545 REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask);
e908dfc3 546 /* Set up wordsize = 1 for DMAs. */
51533b61
MS		 547 DMA_WR_CMD (port->regi_dmain, regk_dma_set_w_size1);
548 DMA_WR_CMD (port->regi_dmaout, regk_dma_set_w_size1);
549
550 start_dma_in(port);
551 port->init_irqs = 0;
552 } else { /* !port->use_dma */
553#ifdef SYNC_SER_MANUAL
554 if (port == &ports[0]) {
e908dfc3 555 if (request_irq(SYNCSER_INTR_VECT,
51533b61
MS		 556 manual_interrupt,
557 0,
558 "synchronous serial manual irq",
559 &ports[0])) {
560 printk("Can't allocate sync serial manual irq");
0c401df3 561 goto out;
51533b61 562 }
e908dfc3
JN		 563 }
564#ifdef CONFIG_ETRAXFS
565 else if (port == &ports[1]) {
51533b61
MS		 566 if (request_irq(SSER1_INTR_VECT,
567 manual_interrupt,
568 0,
569 "synchronous serial manual irq",
570 &ports[1])) {
571 printk(KERN_CRIT "Can't allocate sync serial manual irq");
0c401df3 572 goto out;
51533b61
MS		 573 }
574 }
e908dfc3 575#endif
51533b61
MS		 576 port->init_irqs = 0;
577#else
578 panic("sync_serial: Manual mode not supported.\n");
579#endif /* SYNC_SER_MANUAL */
580 }
e908dfc3 581
51533b61
MS		 582 } /* port->init_irqs */
583
584 port->busy++;
0c401df3
JC		 585 ret = 0;
586out:
587 unlock_kernel();
588 return ret;
51533b61
MS		 589}
590
591static int sync_serial_release(struct inode *inode, struct file *file)
592{
32ea086b 593 int dev = iminor(inode);
e908dfc3 594 sync_port *port;
51533b61 595
e908dfc3 596 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61
MS		 597 {
598 DEBUG(printk("Invalid minor %d\n", dev));
599 return -ENODEV;
600 }
601 port = &ports[dev];
602 if (port->busy)
603 port->busy--;
604 if (!port->busy)
605 /* XXX */ ;
606 return 0;
607}
608
609static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
610{
d817be9c 611 int dev = iminor(file->f_path.dentry->d_inode);
51533b61 612 unsigned int mask = 0;
e908dfc3 613 sync_port *port;
51533b61
MS		 614 DEBUGPOLL( static unsigned int prev_mask = 0; );
615
616 port = &ports[dev];
e908dfc3
JN		 617
618 if (!port->started) {
619 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
620 reg_sser_rw_rec_cfg rec_cfg =
621 REG_RD(sser, port->regi_sser, rw_rec_cfg);
622 cfg.en = regk_sser_yes;
623 rec_cfg.rec_en = port->input;
624 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
625 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
626 port->started = 1;
627 }
628
51533b61
MS		 629 poll_wait(file, &port->out_wait_q, wait);
630 poll_wait(file, &port->in_wait_q, wait);
e908dfc3
JN		 631
632 /* No active transfer, descriptors are available */
633 if (port->output && !port->tr_running)
634 mask |= POLLOUT | POLLWRNORM;
635
636 /* Descriptor and buffer space available. */
637 if (port->output &&
638 port->active_tr_descr != port->catch_tr_descr &&
639 port->out_buf_count < OUT_BUFFER_SIZE)
51533b61 640 mask |= POLLOUT | POLLWRNORM;
e908dfc3 641
51533b61 642 /* At least an inbufchunk of data */
e908dfc3 643 if (port->input && sync_data_avail(port) >= port->inbufchunk)
51533b61
MS		 644 mask |= POLLIN | POLLRDNORM;
645
646 DEBUGPOLL(if (mask != prev_mask)
647 printk("sync_serial_poll: mask 0x%08X %s %s\n", mask,
648 mask&POLLOUT?"POLLOUT":"", mask&POLLIN?"POLLIN":"");
649 prev_mask = mask;
650 );
651 return mask;
652}
653
654static int sync_serial_ioctl(struct inode *inode, struct file *file,
655 unsigned int cmd, unsigned long arg)
656{
657 int return_val = 0;
e908dfc3 658 int dma_w_size = regk_dma_set_w_size1;
d817be9c 659 int dev = iminor(file->f_path.dentry->d_inode);
e908dfc3 660 sync_port *port;
51533b61
MS		 661 reg_sser_rw_tr_cfg tr_cfg;
662 reg_sser_rw_rec_cfg rec_cfg;
663 reg_sser_rw_frm_cfg frm_cfg;
664 reg_sser_rw_cfg gen_cfg;
665 reg_sser_rw_intr_mask intr_mask;
666
e908dfc3 667 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61
MS		 668 {
669 DEBUG(printk("Invalid minor %d\n", dev));
670 return -1;
671 }
672 port = &ports[dev];
673 spin_lock_irq(&port->lock);
674
675 tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
676 rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
677 frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg);
678 gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg);
679 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
680
681 switch(cmd)
682 {
683 case SSP_SPEED:
684 if (GET_SPEED(arg) == CODEC)
685 {
e908dfc3
JN		 686 unsigned int freq;
687
51533b61 688 gen_cfg.base_freq = regk_sser_f32;
e908dfc3
JN		 689
690 /* Clock divider will internally be
691 * gen_cfg.clk_div + 1.
692 */
693
694 freq = GET_FREQ(arg);
695 switch (freq) {
696 case FREQ_32kHz:
697 case FREQ_64kHz:
698 case FREQ_128kHz:
699 case FREQ_256kHz:
700 gen_cfg.clk_div = 125 *
701 (1 << (freq - FREQ_256kHz)) - 1;
702 break;
703 case FREQ_512kHz:
704 gen_cfg.clk_div = 62;
705 break;
706 case FREQ_1MHz:
707 case FREQ_2MHz:
708 case FREQ_4MHz:
709 gen_cfg.clk_div = 8 * (1 << freq) - 1;
710 break;
711 }
712 } else {
51533b61 713 gen_cfg.base_freq = regk_sser_f29_493;
e908dfc3
JN		 714 switch (GET_SPEED(arg)) {
715 case SSP150:
716 gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
717 break;
718 case SSP300:
719 gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
720 break;
721 case SSP600:
722 gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
723 break;
724 case SSP1200:
725 gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
726 break;
727 case SSP2400:
728 gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
729 break;
730 case SSP4800:
731 gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
732 break;
733 case SSP9600:
734 gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
735 break;
736 case SSP19200:
737 gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
738 break;
739 case SSP28800:
740 gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
741 break;
742 case SSP57600:
743 gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
744 break;
745 case SSP115200:
746 gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
747 break;
748 case SSP230400:
749 gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
750 break;
751 case SSP460800:
752 gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
753 break;
754 case SSP921600:
755 gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
756 break;
757 case SSP3125000:
758 gen_cfg.base_freq = regk_sser_f100;
759 gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
760 break;
51533b61
MS		 761
762 }
763 }
764 frm_cfg.wordrate = GET_WORD_RATE(arg);
765
766 break;
767 case SSP_MODE:
768 switch(arg)
769 {
770 case MASTER_OUTPUT:
771 port->output = 1;
772 port->input = 0;
e908dfc3
JN		 773 frm_cfg.out_on = regk_sser_tr;
774 frm_cfg.frame_pin_dir = regk_sser_out;
51533b61
MS		 775 gen_cfg.clk_dir = regk_sser_out;
776 break;
777 case SLAVE_OUTPUT:
778 port->output = 1;
779 port->input = 0;
e908dfc3 780 frm_cfg.frame_pin_dir = regk_sser_in;
51533b61
MS		 781 gen_cfg.clk_dir = regk_sser_in;
782 break;
783 case MASTER_INPUT:
784 port->output = 0;
785 port->input = 1;
e908dfc3
JN		 786 frm_cfg.frame_pin_dir = regk_sser_out;
787 frm_cfg.out_on = regk_sser_intern_tb;
51533b61
MS		 788 gen_cfg.clk_dir = regk_sser_out;
789 break;
790 case SLAVE_INPUT:
791 port->output = 0;
792 port->input = 1;
e908dfc3 793 frm_cfg.frame_pin_dir = regk_sser_in;
51533b61
MS		 794 gen_cfg.clk_dir = regk_sser_in;
795 break;
796 case MASTER_BIDIR:
797 port->output = 1;
798 port->input = 1;
e908dfc3
JN		 799 frm_cfg.frame_pin_dir = regk_sser_out;
800 frm_cfg.out_on = regk_sser_intern_tb;
51533b61
MS		 801 gen_cfg.clk_dir = regk_sser_out;
802 break;
803 case SLAVE_BIDIR:
804 port->output = 1;
805 port->input = 1;
e908dfc3 806 frm_cfg.frame_pin_dir = regk_sser_in;
51533b61
MS		 807 gen_cfg.clk_dir = regk_sser_in;
808 break;
809 default:
810 spin_unlock_irq(&port->lock);
811 return -EINVAL;
51533b61
MS		 812 }
813 if (!port->use_dma || (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT))
814 intr_mask.rdav = regk_sser_yes;
815 break;
816 case SSP_FRAME_SYNC:
e908dfc3
JN		 817 if (arg & NORMAL_SYNC) {
818 frm_cfg.rec_delay = 1;
51533b61 819 frm_cfg.tr_delay = 1;
e908dfc3 820 }
51533b61 821 else if (arg & EARLY_SYNC)
e908dfc3
JN		 822 frm_cfg.rec_delay = frm_cfg.tr_delay = 0;
823 else if (arg & SECOND_WORD_SYNC) {
824 frm_cfg.rec_delay = 7;
825 frm_cfg.tr_delay = 1;
826 }
51533b61
MS		 827
828 tr_cfg.bulk_wspace = frm_cfg.tr_delay;
829 frm_cfg.early_wend = regk_sser_yes;
830 if (arg & BIT_SYNC)
831 frm_cfg.type = regk_sser_edge;
832 else if (arg & WORD_SYNC)
833 frm_cfg.type = regk_sser_level;
834 else if (arg & EXTENDED_SYNC)
835 frm_cfg.early_wend = regk_sser_no;
836
837 if (arg & SYNC_ON)
838 frm_cfg.frame_pin_use = regk_sser_frm;
839 else if (arg & SYNC_OFF)
840 frm_cfg.frame_pin_use = regk_sser_gio0;
841
e908dfc3
JN		 842 dma_w_size = regk_dma_set_w_size2;
843 if (arg & WORD_SIZE_8) {
51533b61 844 rec_cfg.sample_size = tr_cfg.sample_size = 7;
e908dfc3
JN		 845 dma_w_size = regk_dma_set_w_size1;
846 } else if (arg & WORD_SIZE_12)
51533b61
MS		 847 rec_cfg.sample_size = tr_cfg.sample_size = 11;
848 else if (arg & WORD_SIZE_16)
849 rec_cfg.sample_size = tr_cfg.sample_size = 15;
850 else if (arg & WORD_SIZE_24)
851 rec_cfg.sample_size = tr_cfg.sample_size = 23;
852 else if (arg & WORD_SIZE_32)
853 rec_cfg.sample_size = tr_cfg.sample_size = 31;
854
855 if (arg & BIT_ORDER_MSB)
856 rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
857 else if (arg & BIT_ORDER_LSB)
858 rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst;
859
e908dfc3
JN		 860 if (arg & FLOW_CONTROL_ENABLE) {
861 frm_cfg.status_pin_use = regk_sser_frm;
51533b61 862 rec_cfg.fifo_thr = regk_sser_thr16;
e908dfc3
JN		 863 } else if (arg & FLOW_CONTROL_DISABLE) {
864 frm_cfg.status_pin_use = regk_sser_gio0;
51533b61 865 rec_cfg.fifo_thr = regk_sser_inf;
e908dfc3 866 }
51533b61
MS		 867
868 if (arg & CLOCK_NOT_GATED)
869 gen_cfg.gate_clk = regk_sser_no;
870 else if (arg & CLOCK_GATED)
871 gen_cfg.gate_clk = regk_sser_yes;
872
873 break;
874 case SSP_IPOLARITY:
875 /* NOTE!! negedge is considered NORMAL */
876 if (arg & CLOCK_NORMAL)
877 rec_cfg.clk_pol = regk_sser_neg;
878 else if (arg & CLOCK_INVERT)
879 rec_cfg.clk_pol = regk_sser_pos;
880
881 if (arg & FRAME_NORMAL)
882 frm_cfg.level = regk_sser_pos_hi;
883 else if (arg & FRAME_INVERT)
884 frm_cfg.level = regk_sser_neg_lo;
885
886 if (arg & STATUS_NORMAL)
887 gen_cfg.hold_pol = regk_sser_pos;
888 else if (arg & STATUS_INVERT)
889 gen_cfg.hold_pol = regk_sser_neg;
890 break;
891 case SSP_OPOLARITY:
892 if (arg & CLOCK_NORMAL)
51533b61 893 gen_cfg.out_clk_pol = regk_sser_pos;
e908dfc3
JN		 894 else if (arg & CLOCK_INVERT)
895 gen_cfg.out_clk_pol = regk_sser_neg;
51533b61
MS		 896
897 if (arg & FRAME_NORMAL)
898 frm_cfg.level = regk_sser_pos_hi;
899 else if (arg & FRAME_INVERT)
900 frm_cfg.level = regk_sser_neg_lo;
901
902 if (arg & STATUS_NORMAL)
903 gen_cfg.hold_pol = regk_sser_pos;
904 else if (arg & STATUS_INVERT)
905 gen_cfg.hold_pol = regk_sser_neg;
906 break;
907 case SSP_SPI:
908 rec_cfg.fifo_thr = regk_sser_inf;
909 rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
910 rec_cfg.sample_size = tr_cfg.sample_size = 7;
911 frm_cfg.frame_pin_use = regk_sser_frm;
912 frm_cfg.type = regk_sser_level;
913 frm_cfg.tr_delay = 1;
914 frm_cfg.level = regk_sser_neg_lo;
915 if (arg & SPI_SLAVE)
916 {
917 rec_cfg.clk_pol = regk_sser_neg;
918 gen_cfg.clk_dir = regk_sser_in;
919 port->input = 1;
920 port->output = 0;
921 }
922 else
923 {
924 gen_cfg.out_clk_pol = regk_sser_pos;
925 port->input = 0;
926 port->output = 1;
927 gen_cfg.clk_dir = regk_sser_out;
928 }
929 break;
930 case SSP_INBUFCHUNK:
931 break;
932 default:
933 return_val = -1;
934 }
935
936
e908dfc3 937 if (port->started) {
51533b61 938 rec_cfg.rec_en = port->input;
e908dfc3 939 gen_cfg.en = (port->output | port->input);
51533b61
MS		 940 }
941
942 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
943 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
944 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
945 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
946 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
947
e908dfc3
JN		 948
949 if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 |
950 WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) {
951 int en = gen_cfg.en;
952 gen_cfg.en = 0;
953 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
954 /* ##### Should DMA be stoped before we change dma size? */
955 DMA_WR_CMD(port->regi_dmain, dma_w_size);
956 DMA_WR_CMD(port->regi_dmaout, dma_w_size);
957 gen_cfg.en = en;
958 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
959 }
960
51533b61
MS		 961 spin_unlock_irq(&port->lock);
962 return return_val;
963}
964
e908dfc3
JN		 965/* NOTE: sync_serial_write does not support concurrency */
966static ssize_t sync_serial_write(struct file *file, const char *buf,
967 size_t count, loff_t *ppos)
51533b61 968{
d817be9c 969 int dev = iminor(file->f_path.dentry->d_inode);
51533b61 970 DECLARE_WAITQUEUE(wait, current);
e908dfc3
JN		 971 struct sync_port *port;
972 int trunc_count;
51533b61 973 unsigned long flags;
e908dfc3
JN		 974 int bytes_free;
975 int out_buf_count;
51533b61 976
e908dfc3
JN		 977 unsigned char *rd_ptr; /* First allocated byte in the buffer */
978 unsigned char *wr_ptr; /* First free byte in the buffer */
979 unsigned char *buf_stop_ptr; /* Last byte + 1 */
980
981 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
51533b61
MS		 982 DEBUG(printk("Invalid minor %d\n", dev));
983 return -ENODEV;
984 }
985 port = &ports[dev];
986
e908dfc3
JN		 987 /* |<- OUT_BUFFER_SIZE ->|
988 * |<- out_buf_count ->|
989 * |<- trunc_count ->| ...->|
990 * ______________________________________________________
991 * | free | data | free |
992 * |_________|___________________|________________________|
993 * ^ rd_ptr ^ wr_ptr
51533b61 994 */
e908dfc3
JN		 995 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu a: %p c: %p\n",
996 port->port_nbr, count, port->active_tr_descr,
997 port->catch_tr_descr));
51533b61
MS		 998
999 /* Read variables that may be updated by interrupts */
1000 spin_lock_irqsave(&port->lock, flags);
e908dfc3
JN		 1001 rd_ptr = port->out_rd_ptr;
1002 out_buf_count = port->out_buf_count;
51533b61 1003 spin_unlock_irqrestore(&port->lock, flags);
51533b61 1004
e908dfc3
JN		 1005 /* Check if resources are available */
1006 if (port->tr_running &&
1007 ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) ||
1008 out_buf_count >= OUT_BUFFER_SIZE)) {
1009 DEBUGWRITE(printk(KERN_DEBUG "sser%d full\n", dev));
1010 return -EAGAIN;
1011 }
1012
1013 buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE;
1014
1015 /* Determine pointer to the first free byte, before copying. */
1016 wr_ptr = rd_ptr + out_buf_count;
1017 if (wr_ptr >= buf_stop_ptr)
1018 wr_ptr -= OUT_BUFFER_SIZE;
1019
1020 /* If we wrap the ring buffer, let the user space program handle it by
1021 * truncating the data. This could be more elegant, small buffer
1022 * fragments may occur.
1023 */
1024 bytes_free = OUT_BUFFER_SIZE - out_buf_count;
1025 if (wr_ptr + bytes_free > buf_stop_ptr)
1026 bytes_free = buf_stop_ptr - wr_ptr;
1027 trunc_count = (count < bytes_free) ? count : bytes_free;
51533b61 1028
e908dfc3 1029 if (copy_from_user(wr_ptr, buf, trunc_count))
51533b61
MS		 1030 return -EFAULT;
1031
e908dfc3
JN		 1032 DEBUGOUTBUF(printk(KERN_DEBUG "%-4d + %-4d = %-4d %p %p %p\n",
1033 out_buf_count, trunc_count,
1034 port->out_buf_count, port->out_buffer,
1035 wr_ptr, buf_stop_ptr));
51533b61
MS		 1036
1037 /* Make sure transmitter/receiver is running */
e908dfc3 1038 if (!port->started) {
51533b61 1039 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
51533b61
MS		 1040 reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
1041 cfg.en = regk_sser_yes;
51533b61
MS		 1042 rec_cfg.rec_en = port->input;
1043 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
51533b61
MS		 1044 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
1045 port->started = 1;
1046 }
1047
e908dfc3
JN		 1048 /* Setup wait if blocking */
1049 if (!(file->f_flags & O_NONBLOCK)) {
1050 add_wait_queue(&port->out_wait_q, &wait);
1051 set_current_state(TASK_INTERRUPTIBLE);
51533b61
MS		 1052 }
1053
51533b61 1054 spin_lock_irqsave(&port->lock, flags);
e908dfc3
JN		 1055 port->out_buf_count += trunc_count;
1056 if (port->use_dma) {
1057 start_dma_out(port, wr_ptr, trunc_count);
1058 } else if (!port->tr_running) {
1059 reg_sser_rw_intr_mask intr_mask;
1060 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
1061 /* Start sender by writing data */
1062 send_word(port);
1063 /* and enable transmitter ready IRQ */
1064 intr_mask.trdy = 1;
1065 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
51533b61
MS		 1066 }
1067 spin_unlock_irqrestore(&port->lock, flags);
e908dfc3
JN		 1068
1069 /* Exit if non blocking */
1070 if (file->f_flags & O_NONBLOCK) {
1071 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu %08x\n",
1072 port->port_nbr, trunc_count,
1073 REG_RD_INT(dma, port->regi_dmaout, r_intr)));
1074 return trunc_count;
1075 }
1076
51533b61
MS		 1077 schedule();
1078 set_current_state(TASK_RUNNING);
1079 remove_wait_queue(&port->out_wait_q, &wait);
e908dfc3 1080
51533b61 1081 if (signal_pending(current))
51533b61 1082 return -EINTR;
cbca6634 1083
e908dfc3
JN		 1084 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n",
1085 port->port_nbr, trunc_count));
1086 return trunc_count;
51533b61
MS		 1087}
1088
1089static ssize_t sync_serial_read(struct file * file, char * buf,
1090 size_t count, loff_t *ppos)
1091{
d817be9c 1092 int dev = iminor(file->f_path.dentry->d_inode);
51533b61
MS		 1093 int avail;
1094 sync_port *port;
1095 unsigned char* start;
1096 unsigned char* end;
1097 unsigned long flags;
1098
e908dfc3 1099 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
51533b61
MS		 1100 {
1101 DEBUG(printk("Invalid minor %d\n", dev));
1102 return -ENODEV;
1103 }
1104 port = &ports[dev];
1105
1106 DEBUGREAD(printk("R%d c %d ri %lu wi %lu /%lu\n", dev, count, port->readp - port->flip, port->writep - port->flip, port->in_buffer_size));
1107
1108 if (!port->started)
1109 {
1110 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
1111 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
1112 reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
1113 cfg.en = regk_sser_yes;
1114 tr_cfg.tr_en = regk_sser_yes;
1115 rec_cfg.rec_en = regk_sser_yes;
1116 REG_WR(sser, port->regi_sser, rw_cfg, cfg);
1117 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
1118 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
1119 port->started = 1;
1120 }
1121
51533b61
MS		 1122 /* Calculate number of available bytes */
1123 /* Save pointers to avoid that they are modified by interrupt */
1124 spin_lock_irqsave(&port->lock, flags);
1125 start = (unsigned char*)port->readp; /* cast away volatile */
1126 end = (unsigned char*)port->writep; /* cast away volatile */
1127 spin_unlock_irqrestore(&port->lock, flags);
1128 while ((start == end) && !port->full) /* No data */
1129 {
e908dfc3 1130 DEBUGREAD(printk(KERN_DEBUG "&"));
51533b61 1131 if (file->f_flags & O_NONBLOCK)
51533b61 1132 return -EAGAIN;
51533b61
MS		 1133
1134 interruptible_sleep_on(&port->in_wait_q);
1135 if (signal_pending(current))
51533b61 1136 return -EINTR;
e908dfc3 1137
51533b61
MS		 1138 spin_lock_irqsave(&port->lock, flags);
1139 start = (unsigned char*)port->readp; /* cast away volatile */
1140 end = (unsigned char*)port->writep; /* cast away volatile */
1141 spin_unlock_irqrestore(&port->lock, flags);
1142 }
1143
1144 /* Lazy read, never return wrapped data. */
1145 if (port->full)
1146 avail = port->in_buffer_size;
1147 else if (end > start)
1148 avail = end - start;
1149 else
1150 avail = port->flip + port->in_buffer_size - start;
1151
1152 count = count > avail ? avail : count;
1153 if (copy_to_user(buf, start, count))
1154 return -EFAULT;
1155 /* Disable interrupts while updating readp */
1156 spin_lock_irqsave(&port->lock, flags);
1157 port->readp += count;
1158 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1159 port->readp = port->flip;
1160 port->full = 0;
1161 spin_unlock_irqrestore(&port->lock, flags);
1162 DEBUGREAD(printk("r %d\n", count));
1163 return count;
1164}
1165
1166static void send_word(sync_port* port)
1167{
1168 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
1169 reg_sser_rw_tr_data tr_data = {0};
1170
1171 switch(tr_cfg.sample_size)
1172 {
1173 case 8:
e908dfc3
JN		 1174 port->out_buf_count--;
1175 tr_data.data = *port->out_rd_ptr++;
51533b61 1176 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1177 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1178 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1179 break;
1180 case 12:
1181 {
e908dfc3
JN		 1182 int data = (*port->out_rd_ptr++) << 8;
1183 data |= *port->out_rd_ptr++;
1184 port->out_buf_count -= 2;
51533b61
MS		 1185 tr_data.data = data;
1186 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1187 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1188 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1189 }
1190 break;
1191 case 16:
e908dfc3
JN		 1192 port->out_buf_count -= 2;
1193 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1194 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1195 port->out_rd_ptr += 2;
1196 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1197 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1198 break;
1199 case 24:
e908dfc3
JN		 1200 port->out_buf_count -= 3;
1201 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1202 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1203 port->out_rd_ptr += 2;
1204 tr_data.data = *port->out_rd_ptr++;
51533b61 1205 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1206 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1207 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1208 break;
1209 case 32:
e908dfc3
JN		 1210 port->out_buf_count -= 4;
1211 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1212 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1213 port->out_rd_ptr += 2;
1214 tr_data.data = *(unsigned short *)port->out_rd_ptr;
51533b61 1215 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
e908dfc3
JN		 1216 port->out_rd_ptr += 2;
1217 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
1218 port->out_rd_ptr = port->out_buffer;
51533b61
MS		 1219 break;
1220 }
1221}
1222
e908dfc3
JN		 1223static void start_dma_out(struct sync_port *port,
1224 const char *data, int count)
51533b61 1225{
e908dfc3
JN		 1226 port->active_tr_descr->buf = (char *) virt_to_phys((char *) data);
1227 port->active_tr_descr->after = port->active_tr_descr->buf + count;
1228 port->active_tr_descr->intr = 1;
1229
1230 port->active_tr_descr->eol = 1;
1231 port->prev_tr_descr->eol = 0;
1232
1233 DEBUGTRDMA(printk(KERN_DEBUG "Inserting eolr:%p eol@:%p\n",
1234 port->prev_tr_descr, port->active_tr_descr));
1235 port->prev_tr_descr = port->active_tr_descr;
1236 port->active_tr_descr = phys_to_virt((int) port->active_tr_descr->next);
1237
1238 if (!port->tr_running) {
1239 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser,
1240 rw_tr_cfg);
51533b61 1241
e908dfc3
JN		 1242 port->out_context.next = 0;
1243 port->out_context.saved_data =
1244 (dma_descr_data *)virt_to_phys(port->prev_tr_descr);
1245 port->out_context.saved_data_buf = port->prev_tr_descr->buf;
1246
1247 DMA_START_CONTEXT(port->regi_dmaout,
1248 virt_to_phys((char *)&port->out_context));
1249
1250 tr_cfg.tr_en = regk_sser_yes;
1251 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
1252 DEBUGTRDMA(printk(KERN_DEBUG "dma s\n"););
1253 } else {
1254 DMA_CONTINUE_DATA(port->regi_dmaout);
1255 DEBUGTRDMA(printk(KERN_DEBUG "dma c\n"););
1256 }
51533b61 1257
e908dfc3 1258 port->tr_running = 1;
51533b61
MS		 1259}
1260
e908dfc3 1261static void start_dma_in(sync_port *port)
51533b61
MS		 1262{
1263 int i;
e908dfc3 1264 char *buf;
51533b61
MS		 1265 port->writep = port->flip;
1266
e908dfc3 1267 if (port->writep > port->flip + port->in_buffer_size) {
51533b61
MS		 1268 panic("Offset too large in sync serial driver\n");
1269 return;
1270 }
1271 buf = (char*)virt_to_phys(port->in_buffer);
e908dfc3 1272 for (i = 0; i < NBR_IN_DESCR; i++) {
51533b61
MS		 1273 port->in_descr[i].buf = buf;
1274 port->in_descr[i].after = buf + port->inbufchunk;
1275 port->in_descr[i].intr = 1;
1276 port->in_descr[i].next = (dma_descr_data*)virt_to_phys(&port->in_descr[i+1]);
1277 port->in_descr[i].buf = buf;
1278 buf += port->inbufchunk;
1279 }
1280 /* Link the last descriptor to the first */
1281 port->in_descr[i-1].next = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
1282 port->in_descr[i-1].eol = regk_sser_yes;
1283 port->next_rx_desc = &port->in_descr[0];
e908dfc3 1284 port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1];
51533b61
MS		 1285 port->in_context.saved_data = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
1286 port->in_context.saved_data_buf = port->in_descr[0].buf;
1287 DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context));
1288}
1289
1290#ifdef SYNC_SER_DMA
e908dfc3 1291static irqreturn_t tr_interrupt(int irq, void *dev_id)
51533b61
MS		 1292{
1293 reg_dma_r_masked_intr masked;
1294 reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
e908dfc3 1295 reg_dma_rw_stat stat;
51533b61 1296 int i;
51533b61 1297 int found = 0;
e908dfc3 1298 int stop_sser = 0;
51533b61 1299
e908dfc3 1300 for (i = 0; i < NBR_PORTS; i++) {
51533b61 1301 sync_port *port = &ports[i];
e908dfc3 1302 if (!port->enabled || !port->use_dma)
51533b61
MS		 1303 continue;
1304
e908dfc3 1305 /* IRQ active for the port? */
51533b61 1306 masked = REG_RD(dma, port->regi_dmaout, r_masked_intr);
e908dfc3
JN		 1307 if (!masked.data)
1308 continue;
51533b61 1309
e908dfc3
JN		 1310 found = 1;
1311
1312 /* Check if we should stop the DMA transfer */
1313 stat = REG_RD(dma, port->regi_dmaout, rw_stat);
1314 if (stat.list_state == regk_dma_data_at_eol)
1315 stop_sser = 1;
1316
1317 /* Clear IRQ */
1318 REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
1319
1320 if (!stop_sser) {
1321 /* The DMA has completed a descriptor, EOL was not
1322 * encountered, so step relevant descriptor and
1323 * datapointers forward. */
1324 int sent;
1325 sent = port->catch_tr_descr->after -
1326 port->catch_tr_descr->buf;
1327 DEBUGTXINT(printk(KERN_DEBUG "%-4d - %-4d = %-4d\t"
1328 "in descr %p (ac: %p)\n",
1329 port->out_buf_count, sent,
1330 port->out_buf_count - sent,
1331 port->catch_tr_descr,
1332 port->active_tr_descr););
1333 port->out_buf_count -= sent;
1334 port->catch_tr_descr =
1335 phys_to_virt((int) port->catch_tr_descr->next);
1336 port->out_rd_ptr =
1337 phys_to_virt((int) port->catch_tr_descr->buf);
1338 } else {
1339 int i, sent;
1340 /* EOL handler.
1341 * Note that if an EOL was encountered during the irq
1342 * locked section of sync_ser_write the DMA will be
1343 * restarted and the eol flag will be cleared.
1344 * The remaining descriptors will be traversed by
1345 * the descriptor interrupts as usual.
1346 */
1347 i = 0;
1348 while (!port->catch_tr_descr->eol) {
1349 sent = port->catch_tr_descr->after -
1350 port->catch_tr_descr->buf;
1351 DEBUGOUTBUF(printk(KERN_DEBUG
1352 "traversing descr %p -%d (%d)\n",
1353 port->catch_tr_descr,
1354 sent,
1355 port->out_buf_count));
1356 port->out_buf_count -= sent;
1357 port->catch_tr_descr = phys_to_virt(
1358 (int)port->catch_tr_descr->next);
1359 i++;
1360 if (i >= NBR_OUT_DESCR) {
1361 /* TODO: Reset and recover */
1362 panic("sync_serial: missing eol");
1363 }
51533b61 1364 }
e908dfc3
JN		 1365 sent = port->catch_tr_descr->after -
1366 port->catch_tr_descr->buf;
1367 DEBUGOUTBUF(printk(KERN_DEBUG
1368 "eol at descr %p -%d (%d)\n",
1369 port->catch_tr_descr,
1370 sent,
1371 port->out_buf_count));
1372
1373 port->out_buf_count -= sent;
1374
1375 /* Update read pointer to first free byte, we
1376 * may already be writing data there. */
1377 port->out_rd_ptr =
1378 phys_to_virt((int) port->catch_tr_descr->after);
1379 if (port->out_rd_ptr > port->out_buffer +
1380 OUT_BUFFER_SIZE)
1381 port->out_rd_ptr = port->out_buffer;
1382
1383 reg_sser_rw_tr_cfg tr_cfg =
1384 REG_RD(sser, port->regi_sser, rw_tr_cfg);
1385 DEBUGTXINT(printk(KERN_DEBUG
1386 "tr_int DMA stop %d, set catch @ %p\n",
1387 port->out_buf_count,
1388 port->active_tr_descr));
1389 if (port->out_buf_count != 0)
1390 printk(KERN_CRIT "sync_ser: buffer not "
1391 "empty after eol.\n");
1392 port->catch_tr_descr = port->active_tr_descr;
1393 port->tr_running = 0;
1394 tr_cfg.tr_en = regk_sser_no;
1395 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
51533b61 1396 }
e908dfc3
JN		 1397 /* wake up the waiting process */
1398 wake_up_interruptible(&port->out_wait_q);
51533b61
MS		 1399 }
1400 return IRQ_RETVAL(found);
1401} /* tr_interrupt */
1402
e908dfc3 1403static irqreturn_t rx_interrupt(int irq, void *dev_id)
51533b61
MS		 1404{
1405 reg_dma_r_masked_intr masked;
1406 reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
1407
1408 int i;
1409 int found = 0;
1410
e908dfc3 1411 for (i = 0; i < NBR_PORTS; i++)
51533b61
MS		 1412 {
1413 sync_port *port = &ports[i];
1414
1415 if (!port->enabled || !port->use_dma )
1416 continue;
1417
1418 masked = REG_RD(dma, port->regi_dmain, r_masked_intr);
1419
1420 if (masked.data) /* Descriptor interrupt */
1421 {
1422 found = 1;
1423 while (REG_RD(dma, port->regi_dmain, rw_data) !=
1424 virt_to_phys(port->next_rx_desc)) {
e908dfc3 1425 DEBUGRXINT(printk(KERN_DEBUG "!"));
51533b61
MS		 1426 if (port->writep + port->inbufchunk > port->flip + port->in_buffer_size) {
1427 int first_size = port->flip + port->in_buffer_size - port->writep;
1428 memcpy((char*)port->writep, phys_to_virt((unsigned)port->next_rx_desc->buf), first_size);
1429 memcpy(port->flip, phys_to_virt((unsigned)port->next_rx_desc->buf+first_size), port->inbufchunk - first_size);
1430 port->writep = port->flip + port->inbufchunk - first_size;
1431 } else {
1432 memcpy((char*)port->writep,
1433 phys_to_virt((unsigned)port->next_rx_desc->buf),
1434 port->inbufchunk);
1435 port->writep += port->inbufchunk;
1436 if (port->writep >= port->flip + port->in_buffer_size)
1437 port->writep = port->flip;
1438 }
1439 if (port->writep == port->readp)
1440 {
1441 port->full = 1;
1442 }
1443
e908dfc3
JN		 1444 port->next_rx_desc->eol = 1;
1445 port->prev_rx_desc->eol = 0;
1446 /* Cache bug workaround */
1447 flush_dma_descr(port->prev_rx_desc, 0);
1448 port->prev_rx_desc = port->next_rx_desc;
51533b61 1449 port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next);
e908dfc3
JN		 1450 /* Cache bug workaround */
1451 flush_dma_descr(port->prev_rx_desc, 1);
1452 /* wake up the waiting process */
1453 wake_up_interruptible(&port->in_wait_q);
51533b61
MS		 1454 DMA_CONTINUE(port->regi_dmain);
1455 REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr);
1456
1457 }
1458 }
1459 }
1460 return IRQ_RETVAL(found);
1461} /* rx_interrupt */
1462#endif /* SYNC_SER_DMA */
1463
1464#ifdef SYNC_SER_MANUAL
e908dfc3 1465static irqreturn_t manual_interrupt(int irq, void *dev_id)
51533b61
MS		 1466{
1467 int i;
1468 int found = 0;
1469 reg_sser_r_masked_intr masked;
1470
e908dfc3 1471 for (i = 0; i < NBR_PORTS; i++)
51533b61 1472 {
e908dfc3 1473 sync_port *port = &ports[i];
51533b61
MS		 1474
1475 if (!port->enabled || port->use_dma)
1476 {
1477 continue;
1478 }
1479
1480 masked = REG_RD(sser, port->regi_sser, r_masked_intr);
1481 if (masked.rdav) /* Data received? */
1482 {
1483 reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
1484 reg_sser_r_rec_data data = REG_RD(sser, port->regi_sser, r_rec_data);
1485 found = 1;
1486 /* Read data */
1487 switch(rec_cfg.sample_size)
1488 {
1489 case 8:
1490 *port->writep++ = data.data & 0xff;
1491 break;
1492 case 12:
1493 *port->writep = (data.data & 0x0ff0) >> 4;
1494 *(port->writep + 1) = data.data & 0x0f;
1495 port->writep+=2;
1496 break;
1497 case 16:
1498 *(unsigned short*)port->writep = data.data;
1499 port->writep+=2;
1500 break;
1501 case 24:
1502 *(unsigned int*)port->writep = data.data;
1503 port->writep+=3;
1504 break;
1505 case 32:
1506 *(unsigned int*)port->writep = data.data;
1507 port->writep+=4;
1508 break;
1509 }
1510
1511 if (port->writep >= port->flip + port->in_buffer_size) /* Wrap? */
1512 port->writep = port->flip;
1513 if (port->writep == port->readp) {
1514 /* receive buffer overrun, discard oldest data
1515 */
1516 port->readp++;
1517 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1518 port->readp = port->flip;
1519 }
1520 if (sync_data_avail(port) >= port->inbufchunk)
1521 wake_up_interruptible(&port->in_wait_q); /* Wake up application */
1522 }
1523
1524 if (masked.trdy) /* Transmitter ready? */
1525 {
1526 found = 1;
e908dfc3 1527 if (port->out_buf_count > 0) /* More data to send */
51533b61
MS		 1528 send_word(port);
1529 else /* transmission finished */
1530 {
1531 reg_sser_rw_intr_mask intr_mask;
1532 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
1533 intr_mask.trdy = 0;
1534 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
1535 wake_up_interruptible(&port->out_wait_q); /* Wake up application */
1536 }
1537 }
1538 }
1539 return IRQ_RETVAL(found);
1540}
1541#endif
1542
1543module_init(etrax_sync_serial_init);
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