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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __sser_defs_asm_h |
3 | #define __sser_defs_asm_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/syncser/rtl/sser_regs.r | |
8 | * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp | |
9 | * last modfied: Mon Apr 11 16:09:48 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r | |
12 | * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | ||
18 | #ifndef REG_FIELD | |
19 | #define REG_FIELD( scope, reg, field, value ) \ | |
20 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
21 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_STATE | |
25 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
26 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
27 | #define REG_STATE_X_( k, shift ) (k << shift) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_MASK | |
31 | #define REG_MASK( scope, reg, field ) \ | |
32 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
33 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
34 | #endif | |
35 | ||
36 | #ifndef REG_LSB | |
37 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
38 | #endif | |
39 | ||
40 | #ifndef REG_BIT | |
41 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
42 | #endif | |
43 | ||
44 | #ifndef REG_ADDR | |
45 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
46 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_ADDR_VECT | |
50 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
51 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
52 | STRIDE_##scope##_##reg ) | |
53 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
54 | ((inst) + offs + (index) * stride) | |
55 | #endif | |
56 | ||
57 | /* Register rw_cfg, scope sser, type rw */ | |
58 | #define reg_sser_rw_cfg___clk_div___lsb 0 | |
59 | #define reg_sser_rw_cfg___clk_div___width 16 | |
60 | #define reg_sser_rw_cfg___base_freq___lsb 16 | |
61 | #define reg_sser_rw_cfg___base_freq___width 3 | |
62 | #define reg_sser_rw_cfg___gate_clk___lsb 19 | |
63 | #define reg_sser_rw_cfg___gate_clk___width 1 | |
64 | #define reg_sser_rw_cfg___gate_clk___bit 19 | |
65 | #define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 | |
66 | #define reg_sser_rw_cfg___clkgate_ctrl___width 1 | |
67 | #define reg_sser_rw_cfg___clkgate_ctrl___bit 20 | |
68 | #define reg_sser_rw_cfg___clkgate_in___lsb 21 | |
69 | #define reg_sser_rw_cfg___clkgate_in___width 1 | |
70 | #define reg_sser_rw_cfg___clkgate_in___bit 21 | |
71 | #define reg_sser_rw_cfg___clk_dir___lsb 22 | |
72 | #define reg_sser_rw_cfg___clk_dir___width 1 | |
73 | #define reg_sser_rw_cfg___clk_dir___bit 22 | |
74 | #define reg_sser_rw_cfg___clk_od_mode___lsb 23 | |
75 | #define reg_sser_rw_cfg___clk_od_mode___width 1 | |
76 | #define reg_sser_rw_cfg___clk_od_mode___bit 23 | |
77 | #define reg_sser_rw_cfg___out_clk_pol___lsb 24 | |
78 | #define reg_sser_rw_cfg___out_clk_pol___width 1 | |
79 | #define reg_sser_rw_cfg___out_clk_pol___bit 24 | |
80 | #define reg_sser_rw_cfg___out_clk_src___lsb 25 | |
81 | #define reg_sser_rw_cfg___out_clk_src___width 2 | |
82 | #define reg_sser_rw_cfg___clk_in_sel___lsb 27 | |
83 | #define reg_sser_rw_cfg___clk_in_sel___width 1 | |
84 | #define reg_sser_rw_cfg___clk_in_sel___bit 27 | |
85 | #define reg_sser_rw_cfg___hold_pol___lsb 28 | |
86 | #define reg_sser_rw_cfg___hold_pol___width 1 | |
87 | #define reg_sser_rw_cfg___hold_pol___bit 28 | |
88 | #define reg_sser_rw_cfg___prepare___lsb 29 | |
89 | #define reg_sser_rw_cfg___prepare___width 1 | |
90 | #define reg_sser_rw_cfg___prepare___bit 29 | |
91 | #define reg_sser_rw_cfg___en___lsb 30 | |
92 | #define reg_sser_rw_cfg___en___width 1 | |
93 | #define reg_sser_rw_cfg___en___bit 30 | |
94 | #define reg_sser_rw_cfg_offset 0 | |
95 | ||
96 | /* Register rw_frm_cfg, scope sser, type rw */ | |
97 | #define reg_sser_rw_frm_cfg___wordrate___lsb 0 | |
98 | #define reg_sser_rw_frm_cfg___wordrate___width 10 | |
99 | #define reg_sser_rw_frm_cfg___rec_delay___lsb 10 | |
100 | #define reg_sser_rw_frm_cfg___rec_delay___width 3 | |
101 | #define reg_sser_rw_frm_cfg___tr_delay___lsb 13 | |
102 | #define reg_sser_rw_frm_cfg___tr_delay___width 3 | |
103 | #define reg_sser_rw_frm_cfg___early_wend___lsb 16 | |
104 | #define reg_sser_rw_frm_cfg___early_wend___width 1 | |
105 | #define reg_sser_rw_frm_cfg___early_wend___bit 16 | |
106 | #define reg_sser_rw_frm_cfg___level___lsb 17 | |
107 | #define reg_sser_rw_frm_cfg___level___width 2 | |
108 | #define reg_sser_rw_frm_cfg___type___lsb 19 | |
109 | #define reg_sser_rw_frm_cfg___type___width 1 | |
110 | #define reg_sser_rw_frm_cfg___type___bit 19 | |
111 | #define reg_sser_rw_frm_cfg___clk_pol___lsb 20 | |
112 | #define reg_sser_rw_frm_cfg___clk_pol___width 1 | |
113 | #define reg_sser_rw_frm_cfg___clk_pol___bit 20 | |
114 | #define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 | |
115 | #define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 | |
116 | #define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 | |
117 | #define reg_sser_rw_frm_cfg___clk_src___lsb 22 | |
118 | #define reg_sser_rw_frm_cfg___clk_src___width 1 | |
119 | #define reg_sser_rw_frm_cfg___clk_src___bit 22 | |
120 | #define reg_sser_rw_frm_cfg___out_off___lsb 23 | |
121 | #define reg_sser_rw_frm_cfg___out_off___width 1 | |
122 | #define reg_sser_rw_frm_cfg___out_off___bit 23 | |
123 | #define reg_sser_rw_frm_cfg___out_on___lsb 24 | |
124 | #define reg_sser_rw_frm_cfg___out_on___width 1 | |
125 | #define reg_sser_rw_frm_cfg___out_on___bit 24 | |
126 | #define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 | |
127 | #define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 | |
128 | #define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 | |
129 | #define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 | |
130 | #define reg_sser_rw_frm_cfg___frame_pin_use___width 2 | |
131 | #define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 | |
132 | #define reg_sser_rw_frm_cfg___status_pin_dir___width 1 | |
133 | #define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 | |
134 | #define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 | |
135 | #define reg_sser_rw_frm_cfg___status_pin_use___width 2 | |
136 | #define reg_sser_rw_frm_cfg_offset 4 | |
137 | ||
138 | /* Register rw_tr_cfg, scope sser, type rw */ | |
139 | #define reg_sser_rw_tr_cfg___tr_en___lsb 0 | |
140 | #define reg_sser_rw_tr_cfg___tr_en___width 1 | |
141 | #define reg_sser_rw_tr_cfg___tr_en___bit 0 | |
142 | #define reg_sser_rw_tr_cfg___stop___lsb 1 | |
143 | #define reg_sser_rw_tr_cfg___stop___width 1 | |
144 | #define reg_sser_rw_tr_cfg___stop___bit 1 | |
145 | #define reg_sser_rw_tr_cfg___urun_stop___lsb 2 | |
146 | #define reg_sser_rw_tr_cfg___urun_stop___width 1 | |
147 | #define reg_sser_rw_tr_cfg___urun_stop___bit 2 | |
148 | #define reg_sser_rw_tr_cfg___eop_stop___lsb 3 | |
149 | #define reg_sser_rw_tr_cfg___eop_stop___width 1 | |
150 | #define reg_sser_rw_tr_cfg___eop_stop___bit 3 | |
151 | #define reg_sser_rw_tr_cfg___sample_size___lsb 4 | |
152 | #define reg_sser_rw_tr_cfg___sample_size___width 6 | |
153 | #define reg_sser_rw_tr_cfg___sh_dir___lsb 10 | |
154 | #define reg_sser_rw_tr_cfg___sh_dir___width 1 | |
155 | #define reg_sser_rw_tr_cfg___sh_dir___bit 10 | |
156 | #define reg_sser_rw_tr_cfg___clk_pol___lsb 11 | |
157 | #define reg_sser_rw_tr_cfg___clk_pol___width 1 | |
158 | #define reg_sser_rw_tr_cfg___clk_pol___bit 11 | |
159 | #define reg_sser_rw_tr_cfg___clk_src___lsb 12 | |
160 | #define reg_sser_rw_tr_cfg___clk_src___width 1 | |
161 | #define reg_sser_rw_tr_cfg___clk_src___bit 12 | |
162 | #define reg_sser_rw_tr_cfg___use_dma___lsb 13 | |
163 | #define reg_sser_rw_tr_cfg___use_dma___width 1 | |
164 | #define reg_sser_rw_tr_cfg___use_dma___bit 13 | |
165 | #define reg_sser_rw_tr_cfg___mode___lsb 14 | |
166 | #define reg_sser_rw_tr_cfg___mode___width 2 | |
167 | #define reg_sser_rw_tr_cfg___frm_src___lsb 16 | |
168 | #define reg_sser_rw_tr_cfg___frm_src___width 1 | |
169 | #define reg_sser_rw_tr_cfg___frm_src___bit 16 | |
170 | #define reg_sser_rw_tr_cfg___use60958___lsb 17 | |
171 | #define reg_sser_rw_tr_cfg___use60958___width 1 | |
172 | #define reg_sser_rw_tr_cfg___use60958___bit 17 | |
173 | #define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 | |
174 | #define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 | |
175 | #define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 | |
176 | #define reg_sser_rw_tr_cfg___rate_ctrl___width 1 | |
177 | #define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 | |
178 | #define reg_sser_rw_tr_cfg___use_md___lsb 21 | |
179 | #define reg_sser_rw_tr_cfg___use_md___width 1 | |
180 | #define reg_sser_rw_tr_cfg___use_md___bit 21 | |
181 | #define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 | |
182 | #define reg_sser_rw_tr_cfg___dual_i2s___width 1 | |
183 | #define reg_sser_rw_tr_cfg___dual_i2s___bit 22 | |
184 | #define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 | |
185 | #define reg_sser_rw_tr_cfg___data_pin_use___width 2 | |
186 | #define reg_sser_rw_tr_cfg___od_mode___lsb 25 | |
187 | #define reg_sser_rw_tr_cfg___od_mode___width 1 | |
188 | #define reg_sser_rw_tr_cfg___od_mode___bit 25 | |
189 | #define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 | |
190 | #define reg_sser_rw_tr_cfg___bulk_wspace___width 2 | |
191 | #define reg_sser_rw_tr_cfg_offset 8 | |
192 | ||
193 | /* Register rw_rec_cfg, scope sser, type rw */ | |
194 | #define reg_sser_rw_rec_cfg___rec_en___lsb 0 | |
195 | #define reg_sser_rw_rec_cfg___rec_en___width 1 | |
196 | #define reg_sser_rw_rec_cfg___rec_en___bit 0 | |
197 | #define reg_sser_rw_rec_cfg___force_eop___lsb 1 | |
198 | #define reg_sser_rw_rec_cfg___force_eop___width 1 | |
199 | #define reg_sser_rw_rec_cfg___force_eop___bit 1 | |
200 | #define reg_sser_rw_rec_cfg___stop___lsb 2 | |
201 | #define reg_sser_rw_rec_cfg___stop___width 1 | |
202 | #define reg_sser_rw_rec_cfg___stop___bit 2 | |
203 | #define reg_sser_rw_rec_cfg___orun_stop___lsb 3 | |
204 | #define reg_sser_rw_rec_cfg___orun_stop___width 1 | |
205 | #define reg_sser_rw_rec_cfg___orun_stop___bit 3 | |
206 | #define reg_sser_rw_rec_cfg___eop_stop___lsb 4 | |
207 | #define reg_sser_rw_rec_cfg___eop_stop___width 1 | |
208 | #define reg_sser_rw_rec_cfg___eop_stop___bit 4 | |
209 | #define reg_sser_rw_rec_cfg___sample_size___lsb 5 | |
210 | #define reg_sser_rw_rec_cfg___sample_size___width 6 | |
211 | #define reg_sser_rw_rec_cfg___sh_dir___lsb 11 | |
212 | #define reg_sser_rw_rec_cfg___sh_dir___width 1 | |
213 | #define reg_sser_rw_rec_cfg___sh_dir___bit 11 | |
214 | #define reg_sser_rw_rec_cfg___clk_pol___lsb 12 | |
215 | #define reg_sser_rw_rec_cfg___clk_pol___width 1 | |
216 | #define reg_sser_rw_rec_cfg___clk_pol___bit 12 | |
217 | #define reg_sser_rw_rec_cfg___clk_src___lsb 13 | |
218 | #define reg_sser_rw_rec_cfg___clk_src___width 1 | |
219 | #define reg_sser_rw_rec_cfg___clk_src___bit 13 | |
220 | #define reg_sser_rw_rec_cfg___use_dma___lsb 14 | |
221 | #define reg_sser_rw_rec_cfg___use_dma___width 1 | |
222 | #define reg_sser_rw_rec_cfg___use_dma___bit 14 | |
223 | #define reg_sser_rw_rec_cfg___mode___lsb 15 | |
224 | #define reg_sser_rw_rec_cfg___mode___width 2 | |
225 | #define reg_sser_rw_rec_cfg___frm_src___lsb 17 | |
226 | #define reg_sser_rw_rec_cfg___frm_src___width 2 | |
227 | #define reg_sser_rw_rec_cfg___use60958___lsb 19 | |
228 | #define reg_sser_rw_rec_cfg___use60958___width 1 | |
229 | #define reg_sser_rw_rec_cfg___use60958___bit 19 | |
230 | #define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 | |
231 | #define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 | |
232 | #define reg_sser_rw_rec_cfg___slave2_en___lsb 25 | |
233 | #define reg_sser_rw_rec_cfg___slave2_en___width 1 | |
234 | #define reg_sser_rw_rec_cfg___slave2_en___bit 25 | |
235 | #define reg_sser_rw_rec_cfg___slave3_en___lsb 26 | |
236 | #define reg_sser_rw_rec_cfg___slave3_en___width 1 | |
237 | #define reg_sser_rw_rec_cfg___slave3_en___bit 26 | |
238 | #define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 | |
239 | #define reg_sser_rw_rec_cfg___fifo_thr___width 2 | |
240 | #define reg_sser_rw_rec_cfg_offset 12 | |
241 | ||
242 | /* Register rw_tr_data, scope sser, type rw */ | |
243 | #define reg_sser_rw_tr_data___data___lsb 0 | |
244 | #define reg_sser_rw_tr_data___data___width 16 | |
245 | #define reg_sser_rw_tr_data___md___lsb 16 | |
246 | #define reg_sser_rw_tr_data___md___width 1 | |
247 | #define reg_sser_rw_tr_data___md___bit 16 | |
248 | #define reg_sser_rw_tr_data_offset 16 | |
249 | ||
250 | /* Register r_rec_data, scope sser, type r */ | |
251 | #define reg_sser_r_rec_data___data___lsb 0 | |
252 | #define reg_sser_r_rec_data___data___width 16 | |
253 | #define reg_sser_r_rec_data___md___lsb 16 | |
254 | #define reg_sser_r_rec_data___md___width 1 | |
255 | #define reg_sser_r_rec_data___md___bit 16 | |
256 | #define reg_sser_r_rec_data___ext_clk___lsb 17 | |
257 | #define reg_sser_r_rec_data___ext_clk___width 1 | |
258 | #define reg_sser_r_rec_data___ext_clk___bit 17 | |
259 | #define reg_sser_r_rec_data___status_in___lsb 18 | |
260 | #define reg_sser_r_rec_data___status_in___width 1 | |
261 | #define reg_sser_r_rec_data___status_in___bit 18 | |
262 | #define reg_sser_r_rec_data___frame_in___lsb 19 | |
263 | #define reg_sser_r_rec_data___frame_in___width 1 | |
264 | #define reg_sser_r_rec_data___frame_in___bit 19 | |
265 | #define reg_sser_r_rec_data___din___lsb 20 | |
266 | #define reg_sser_r_rec_data___din___width 1 | |
267 | #define reg_sser_r_rec_data___din___bit 20 | |
268 | #define reg_sser_r_rec_data___data_in___lsb 21 | |
269 | #define reg_sser_r_rec_data___data_in___width 1 | |
270 | #define reg_sser_r_rec_data___data_in___bit 21 | |
271 | #define reg_sser_r_rec_data___clk_in___lsb 22 | |
272 | #define reg_sser_r_rec_data___clk_in___width 1 | |
273 | #define reg_sser_r_rec_data___clk_in___bit 22 | |
274 | #define reg_sser_r_rec_data_offset 20 | |
275 | ||
276 | /* Register rw_extra, scope sser, type rw */ | |
277 | #define reg_sser_rw_extra___clkoff_cycles___lsb 0 | |
278 | #define reg_sser_rw_extra___clkoff_cycles___width 20 | |
279 | #define reg_sser_rw_extra___clkoff_en___lsb 20 | |
280 | #define reg_sser_rw_extra___clkoff_en___width 1 | |
281 | #define reg_sser_rw_extra___clkoff_en___bit 20 | |
282 | #define reg_sser_rw_extra___clkon_en___lsb 21 | |
283 | #define reg_sser_rw_extra___clkon_en___width 1 | |
284 | #define reg_sser_rw_extra___clkon_en___bit 21 | |
285 | #define reg_sser_rw_extra___dout_delay___lsb 22 | |
286 | #define reg_sser_rw_extra___dout_delay___width 5 | |
287 | #define reg_sser_rw_extra_offset 24 | |
288 | ||
289 | /* Register rw_intr_mask, scope sser, type rw */ | |
290 | #define reg_sser_rw_intr_mask___trdy___lsb 0 | |
291 | #define reg_sser_rw_intr_mask___trdy___width 1 | |
292 | #define reg_sser_rw_intr_mask___trdy___bit 0 | |
293 | #define reg_sser_rw_intr_mask___rdav___lsb 1 | |
294 | #define reg_sser_rw_intr_mask___rdav___width 1 | |
295 | #define reg_sser_rw_intr_mask___rdav___bit 1 | |
296 | #define reg_sser_rw_intr_mask___tidle___lsb 2 | |
297 | #define reg_sser_rw_intr_mask___tidle___width 1 | |
298 | #define reg_sser_rw_intr_mask___tidle___bit 2 | |
299 | #define reg_sser_rw_intr_mask___rstop___lsb 3 | |
300 | #define reg_sser_rw_intr_mask___rstop___width 1 | |
301 | #define reg_sser_rw_intr_mask___rstop___bit 3 | |
302 | #define reg_sser_rw_intr_mask___urun___lsb 4 | |
303 | #define reg_sser_rw_intr_mask___urun___width 1 | |
304 | #define reg_sser_rw_intr_mask___urun___bit 4 | |
305 | #define reg_sser_rw_intr_mask___orun___lsb 5 | |
306 | #define reg_sser_rw_intr_mask___orun___width 1 | |
307 | #define reg_sser_rw_intr_mask___orun___bit 5 | |
308 | #define reg_sser_rw_intr_mask___md_rec___lsb 6 | |
309 | #define reg_sser_rw_intr_mask___md_rec___width 1 | |
310 | #define reg_sser_rw_intr_mask___md_rec___bit 6 | |
311 | #define reg_sser_rw_intr_mask___md_sent___lsb 7 | |
312 | #define reg_sser_rw_intr_mask___md_sent___width 1 | |
313 | #define reg_sser_rw_intr_mask___md_sent___bit 7 | |
314 | #define reg_sser_rw_intr_mask___r958err___lsb 8 | |
315 | #define reg_sser_rw_intr_mask___r958err___width 1 | |
316 | #define reg_sser_rw_intr_mask___r958err___bit 8 | |
317 | #define reg_sser_rw_intr_mask_offset 28 | |
318 | ||
319 | /* Register rw_ack_intr, scope sser, type rw */ | |
320 | #define reg_sser_rw_ack_intr___trdy___lsb 0 | |
321 | #define reg_sser_rw_ack_intr___trdy___width 1 | |
322 | #define reg_sser_rw_ack_intr___trdy___bit 0 | |
323 | #define reg_sser_rw_ack_intr___rdav___lsb 1 | |
324 | #define reg_sser_rw_ack_intr___rdav___width 1 | |
325 | #define reg_sser_rw_ack_intr___rdav___bit 1 | |
326 | #define reg_sser_rw_ack_intr___tidle___lsb 2 | |
327 | #define reg_sser_rw_ack_intr___tidle___width 1 | |
328 | #define reg_sser_rw_ack_intr___tidle___bit 2 | |
329 | #define reg_sser_rw_ack_intr___rstop___lsb 3 | |
330 | #define reg_sser_rw_ack_intr___rstop___width 1 | |
331 | #define reg_sser_rw_ack_intr___rstop___bit 3 | |
332 | #define reg_sser_rw_ack_intr___urun___lsb 4 | |
333 | #define reg_sser_rw_ack_intr___urun___width 1 | |
334 | #define reg_sser_rw_ack_intr___urun___bit 4 | |
335 | #define reg_sser_rw_ack_intr___orun___lsb 5 | |
336 | #define reg_sser_rw_ack_intr___orun___width 1 | |
337 | #define reg_sser_rw_ack_intr___orun___bit 5 | |
338 | #define reg_sser_rw_ack_intr___md_rec___lsb 6 | |
339 | #define reg_sser_rw_ack_intr___md_rec___width 1 | |
340 | #define reg_sser_rw_ack_intr___md_rec___bit 6 | |
341 | #define reg_sser_rw_ack_intr___md_sent___lsb 7 | |
342 | #define reg_sser_rw_ack_intr___md_sent___width 1 | |
343 | #define reg_sser_rw_ack_intr___md_sent___bit 7 | |
344 | #define reg_sser_rw_ack_intr___r958err___lsb 8 | |
345 | #define reg_sser_rw_ack_intr___r958err___width 1 | |
346 | #define reg_sser_rw_ack_intr___r958err___bit 8 | |
347 | #define reg_sser_rw_ack_intr_offset 32 | |
348 | ||
349 | /* Register r_intr, scope sser, type r */ | |
350 | #define reg_sser_r_intr___trdy___lsb 0 | |
351 | #define reg_sser_r_intr___trdy___width 1 | |
352 | #define reg_sser_r_intr___trdy___bit 0 | |
353 | #define reg_sser_r_intr___rdav___lsb 1 | |
354 | #define reg_sser_r_intr___rdav___width 1 | |
355 | #define reg_sser_r_intr___rdav___bit 1 | |
356 | #define reg_sser_r_intr___tidle___lsb 2 | |
357 | #define reg_sser_r_intr___tidle___width 1 | |
358 | #define reg_sser_r_intr___tidle___bit 2 | |
359 | #define reg_sser_r_intr___rstop___lsb 3 | |
360 | #define reg_sser_r_intr___rstop___width 1 | |
361 | #define reg_sser_r_intr___rstop___bit 3 | |
362 | #define reg_sser_r_intr___urun___lsb 4 | |
363 | #define reg_sser_r_intr___urun___width 1 | |
364 | #define reg_sser_r_intr___urun___bit 4 | |
365 | #define reg_sser_r_intr___orun___lsb 5 | |
366 | #define reg_sser_r_intr___orun___width 1 | |
367 | #define reg_sser_r_intr___orun___bit 5 | |
368 | #define reg_sser_r_intr___md_rec___lsb 6 | |
369 | #define reg_sser_r_intr___md_rec___width 1 | |
370 | #define reg_sser_r_intr___md_rec___bit 6 | |
371 | #define reg_sser_r_intr___md_sent___lsb 7 | |
372 | #define reg_sser_r_intr___md_sent___width 1 | |
373 | #define reg_sser_r_intr___md_sent___bit 7 | |
374 | #define reg_sser_r_intr___r958err___lsb 8 | |
375 | #define reg_sser_r_intr___r958err___width 1 | |
376 | #define reg_sser_r_intr___r958err___bit 8 | |
377 | #define reg_sser_r_intr_offset 36 | |
378 | ||
379 | /* Register r_masked_intr, scope sser, type r */ | |
380 | #define reg_sser_r_masked_intr___trdy___lsb 0 | |
381 | #define reg_sser_r_masked_intr___trdy___width 1 | |
382 | #define reg_sser_r_masked_intr___trdy___bit 0 | |
383 | #define reg_sser_r_masked_intr___rdav___lsb 1 | |
384 | #define reg_sser_r_masked_intr___rdav___width 1 | |
385 | #define reg_sser_r_masked_intr___rdav___bit 1 | |
386 | #define reg_sser_r_masked_intr___tidle___lsb 2 | |
387 | #define reg_sser_r_masked_intr___tidle___width 1 | |
388 | #define reg_sser_r_masked_intr___tidle___bit 2 | |
389 | #define reg_sser_r_masked_intr___rstop___lsb 3 | |
390 | #define reg_sser_r_masked_intr___rstop___width 1 | |
391 | #define reg_sser_r_masked_intr___rstop___bit 3 | |
392 | #define reg_sser_r_masked_intr___urun___lsb 4 | |
393 | #define reg_sser_r_masked_intr___urun___width 1 | |
394 | #define reg_sser_r_masked_intr___urun___bit 4 | |
395 | #define reg_sser_r_masked_intr___orun___lsb 5 | |
396 | #define reg_sser_r_masked_intr___orun___width 1 | |
397 | #define reg_sser_r_masked_intr___orun___bit 5 | |
398 | #define reg_sser_r_masked_intr___md_rec___lsb 6 | |
399 | #define reg_sser_r_masked_intr___md_rec___width 1 | |
400 | #define reg_sser_r_masked_intr___md_rec___bit 6 | |
401 | #define reg_sser_r_masked_intr___md_sent___lsb 7 | |
402 | #define reg_sser_r_masked_intr___md_sent___width 1 | |
403 | #define reg_sser_r_masked_intr___md_sent___bit 7 | |
404 | #define reg_sser_r_masked_intr___r958err___lsb 8 | |
405 | #define reg_sser_r_masked_intr___r958err___width 1 | |
406 | #define reg_sser_r_masked_intr___r958err___bit 8 | |
407 | #define reg_sser_r_masked_intr_offset 40 | |
408 | ||
409 | ||
410 | /* Constants */ | |
411 | #define regk_sser_both 0x00000002 | |
412 | #define regk_sser_bulk 0x00000001 | |
413 | #define regk_sser_clk100 0x00000000 | |
414 | #define regk_sser_clk_in 0x00000000 | |
415 | #define regk_sser_const0 0x00000003 | |
416 | #define regk_sser_dout 0x00000002 | |
417 | #define regk_sser_edge 0x00000000 | |
418 | #define regk_sser_ext 0x00000001 | |
419 | #define regk_sser_ext_clk 0x00000001 | |
420 | #define regk_sser_f100 0x00000000 | |
421 | #define regk_sser_f29_493 0x00000004 | |
422 | #define regk_sser_f32 0x00000005 | |
423 | #define regk_sser_f32_768 0x00000006 | |
424 | #define regk_sser_frm 0x00000003 | |
425 | #define regk_sser_gio0 0x00000000 | |
426 | #define regk_sser_gio1 0x00000001 | |
427 | #define regk_sser_hispeed 0x00000001 | |
428 | #define regk_sser_hold 0x00000002 | |
429 | #define regk_sser_in 0x00000000 | |
430 | #define regk_sser_inf 0x00000003 | |
431 | #define regk_sser_intern 0x00000000 | |
432 | #define regk_sser_intern_clk 0x00000001 | |
433 | #define regk_sser_intern_tb 0x00000000 | |
434 | #define regk_sser_iso 0x00000000 | |
435 | #define regk_sser_level 0x00000001 | |
436 | #define regk_sser_lospeed 0x00000000 | |
437 | #define regk_sser_lsbfirst 0x00000000 | |
438 | #define regk_sser_msbfirst 0x00000001 | |
439 | #define regk_sser_neg 0x00000001 | |
440 | #define regk_sser_neg_lo 0x00000000 | |
441 | #define regk_sser_no 0x00000000 | |
442 | #define regk_sser_no_clk 0x00000007 | |
443 | #define regk_sser_nojitter 0x00000002 | |
444 | #define regk_sser_out 0x00000001 | |
445 | #define regk_sser_pos 0x00000000 | |
446 | #define regk_sser_pos_hi 0x00000001 | |
447 | #define regk_sser_rec 0x00000000 | |
448 | #define regk_sser_rw_cfg_default 0x00000000 | |
449 | #define regk_sser_rw_extra_default 0x00000000 | |
450 | #define regk_sser_rw_frm_cfg_default 0x00000000 | |
451 | #define regk_sser_rw_intr_mask_default 0x00000000 | |
452 | #define regk_sser_rw_rec_cfg_default 0x00000000 | |
453 | #define regk_sser_rw_tr_cfg_default 0x01800000 | |
454 | #define regk_sser_rw_tr_data_default 0x00000000 | |
455 | #define regk_sser_thr16 0x00000001 | |
456 | #define regk_sser_thr32 0x00000002 | |
457 | #define regk_sser_thr8 0x00000000 | |
458 | #define regk_sser_tr 0x00000001 | |
459 | #define regk_sser_ts_out 0x00000003 | |
460 | #define regk_sser_tx_bulk 0x00000002 | |
461 | #define regk_sser_wiresave 0x00000002 | |
462 | #define regk_sser_yes 0x00000001 | |
463 | #endif /* __sser_defs_asm_h */ |