]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __timer_defs_asm_h |
3 | #define __timer_defs_asm_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/timer/rtl/timer_regs.r | |
8 | * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp | |
9 | * last modfied: Mon Apr 11 16:09:53 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r | |
12 | * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | ||
18 | #ifndef REG_FIELD | |
19 | #define REG_FIELD( scope, reg, field, value ) \ | |
20 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
21 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_STATE | |
25 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
26 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
27 | #define REG_STATE_X_( k, shift ) (k << shift) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_MASK | |
31 | #define REG_MASK( scope, reg, field ) \ | |
32 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
33 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
34 | #endif | |
35 | ||
36 | #ifndef REG_LSB | |
37 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
38 | #endif | |
39 | ||
40 | #ifndef REG_BIT | |
41 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
42 | #endif | |
43 | ||
44 | #ifndef REG_ADDR | |
45 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
46 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_ADDR_VECT | |
50 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
51 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
52 | STRIDE_##scope##_##reg ) | |
53 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
54 | ((inst) + offs + (index) * stride) | |
55 | #endif | |
56 | ||
57 | /* Register rw_tmr0_div, scope timer, type rw */ | |
58 | #define reg_timer_rw_tmr0_div_offset 0 | |
59 | ||
60 | /* Register r_tmr0_data, scope timer, type r */ | |
61 | #define reg_timer_r_tmr0_data_offset 4 | |
62 | ||
63 | /* Register rw_tmr0_ctrl, scope timer, type rw */ | |
64 | #define reg_timer_rw_tmr0_ctrl___op___lsb 0 | |
65 | #define reg_timer_rw_tmr0_ctrl___op___width 2 | |
66 | #define reg_timer_rw_tmr0_ctrl___freq___lsb 2 | |
67 | #define reg_timer_rw_tmr0_ctrl___freq___width 3 | |
68 | #define reg_timer_rw_tmr0_ctrl_offset 8 | |
69 | ||
70 | /* Register rw_tmr1_div, scope timer, type rw */ | |
71 | #define reg_timer_rw_tmr1_div_offset 16 | |
72 | ||
73 | /* Register r_tmr1_data, scope timer, type r */ | |
74 | #define reg_timer_r_tmr1_data_offset 20 | |
75 | ||
76 | /* Register rw_tmr1_ctrl, scope timer, type rw */ | |
77 | #define reg_timer_rw_tmr1_ctrl___op___lsb 0 | |
78 | #define reg_timer_rw_tmr1_ctrl___op___width 2 | |
79 | #define reg_timer_rw_tmr1_ctrl___freq___lsb 2 | |
80 | #define reg_timer_rw_tmr1_ctrl___freq___width 3 | |
81 | #define reg_timer_rw_tmr1_ctrl_offset 24 | |
82 | ||
83 | /* Register rs_cnt_data, scope timer, type rs */ | |
84 | #define reg_timer_rs_cnt_data___tmr___lsb 0 | |
85 | #define reg_timer_rs_cnt_data___tmr___width 24 | |
86 | #define reg_timer_rs_cnt_data___cnt___lsb 24 | |
87 | #define reg_timer_rs_cnt_data___cnt___width 8 | |
88 | #define reg_timer_rs_cnt_data_offset 32 | |
89 | ||
90 | /* Register r_cnt_data, scope timer, type r */ | |
91 | #define reg_timer_r_cnt_data___tmr___lsb 0 | |
92 | #define reg_timer_r_cnt_data___tmr___width 24 | |
93 | #define reg_timer_r_cnt_data___cnt___lsb 24 | |
94 | #define reg_timer_r_cnt_data___cnt___width 8 | |
95 | #define reg_timer_r_cnt_data_offset 36 | |
96 | ||
97 | /* Register rw_cnt_cfg, scope timer, type rw */ | |
98 | #define reg_timer_rw_cnt_cfg___clk___lsb 0 | |
99 | #define reg_timer_rw_cnt_cfg___clk___width 2 | |
100 | #define reg_timer_rw_cnt_cfg_offset 40 | |
101 | ||
102 | /* Register rw_trig, scope timer, type rw */ | |
103 | #define reg_timer_rw_trig_offset 48 | |
104 | ||
105 | /* Register rw_trig_cfg, scope timer, type rw */ | |
106 | #define reg_timer_rw_trig_cfg___tmr___lsb 0 | |
107 | #define reg_timer_rw_trig_cfg___tmr___width 2 | |
108 | #define reg_timer_rw_trig_cfg_offset 52 | |
109 | ||
110 | /* Register r_time, scope timer, type r */ | |
111 | #define reg_timer_r_time_offset 56 | |
112 | ||
113 | /* Register rw_out, scope timer, type rw */ | |
114 | #define reg_timer_rw_out___tmr___lsb 0 | |
115 | #define reg_timer_rw_out___tmr___width 2 | |
116 | #define reg_timer_rw_out_offset 60 | |
117 | ||
118 | /* Register rw_wd_ctrl, scope timer, type rw */ | |
119 | #define reg_timer_rw_wd_ctrl___cnt___lsb 0 | |
120 | #define reg_timer_rw_wd_ctrl___cnt___width 8 | |
121 | #define reg_timer_rw_wd_ctrl___cmd___lsb 8 | |
122 | #define reg_timer_rw_wd_ctrl___cmd___width 1 | |
123 | #define reg_timer_rw_wd_ctrl___cmd___bit 8 | |
124 | #define reg_timer_rw_wd_ctrl___key___lsb 9 | |
125 | #define reg_timer_rw_wd_ctrl___key___width 7 | |
126 | #define reg_timer_rw_wd_ctrl_offset 64 | |
127 | ||
128 | /* Register r_wd_stat, scope timer, type r */ | |
129 | #define reg_timer_r_wd_stat___cnt___lsb 0 | |
130 | #define reg_timer_r_wd_stat___cnt___width 8 | |
131 | #define reg_timer_r_wd_stat___cmd___lsb 8 | |
132 | #define reg_timer_r_wd_stat___cmd___width 1 | |
133 | #define reg_timer_r_wd_stat___cmd___bit 8 | |
134 | #define reg_timer_r_wd_stat_offset 68 | |
135 | ||
136 | /* Register rw_intr_mask, scope timer, type rw */ | |
137 | #define reg_timer_rw_intr_mask___tmr0___lsb 0 | |
138 | #define reg_timer_rw_intr_mask___tmr0___width 1 | |
139 | #define reg_timer_rw_intr_mask___tmr0___bit 0 | |
140 | #define reg_timer_rw_intr_mask___tmr1___lsb 1 | |
141 | #define reg_timer_rw_intr_mask___tmr1___width 1 | |
142 | #define reg_timer_rw_intr_mask___tmr1___bit 1 | |
143 | #define reg_timer_rw_intr_mask___cnt___lsb 2 | |
144 | #define reg_timer_rw_intr_mask___cnt___width 1 | |
145 | #define reg_timer_rw_intr_mask___cnt___bit 2 | |
146 | #define reg_timer_rw_intr_mask___trig___lsb 3 | |
147 | #define reg_timer_rw_intr_mask___trig___width 1 | |
148 | #define reg_timer_rw_intr_mask___trig___bit 3 | |
149 | #define reg_timer_rw_intr_mask_offset 72 | |
150 | ||
151 | /* Register rw_ack_intr, scope timer, type rw */ | |
152 | #define reg_timer_rw_ack_intr___tmr0___lsb 0 | |
153 | #define reg_timer_rw_ack_intr___tmr0___width 1 | |
154 | #define reg_timer_rw_ack_intr___tmr0___bit 0 | |
155 | #define reg_timer_rw_ack_intr___tmr1___lsb 1 | |
156 | #define reg_timer_rw_ack_intr___tmr1___width 1 | |
157 | #define reg_timer_rw_ack_intr___tmr1___bit 1 | |
158 | #define reg_timer_rw_ack_intr___cnt___lsb 2 | |
159 | #define reg_timer_rw_ack_intr___cnt___width 1 | |
160 | #define reg_timer_rw_ack_intr___cnt___bit 2 | |
161 | #define reg_timer_rw_ack_intr___trig___lsb 3 | |
162 | #define reg_timer_rw_ack_intr___trig___width 1 | |
163 | #define reg_timer_rw_ack_intr___trig___bit 3 | |
164 | #define reg_timer_rw_ack_intr_offset 76 | |
165 | ||
166 | /* Register r_intr, scope timer, type r */ | |
167 | #define reg_timer_r_intr___tmr0___lsb 0 | |
168 | #define reg_timer_r_intr___tmr0___width 1 | |
169 | #define reg_timer_r_intr___tmr0___bit 0 | |
170 | #define reg_timer_r_intr___tmr1___lsb 1 | |
171 | #define reg_timer_r_intr___tmr1___width 1 | |
172 | #define reg_timer_r_intr___tmr1___bit 1 | |
173 | #define reg_timer_r_intr___cnt___lsb 2 | |
174 | #define reg_timer_r_intr___cnt___width 1 | |
175 | #define reg_timer_r_intr___cnt___bit 2 | |
176 | #define reg_timer_r_intr___trig___lsb 3 | |
177 | #define reg_timer_r_intr___trig___width 1 | |
178 | #define reg_timer_r_intr___trig___bit 3 | |
179 | #define reg_timer_r_intr_offset 80 | |
180 | ||
181 | /* Register r_masked_intr, scope timer, type r */ | |
182 | #define reg_timer_r_masked_intr___tmr0___lsb 0 | |
183 | #define reg_timer_r_masked_intr___tmr0___width 1 | |
184 | #define reg_timer_r_masked_intr___tmr0___bit 0 | |
185 | #define reg_timer_r_masked_intr___tmr1___lsb 1 | |
186 | #define reg_timer_r_masked_intr___tmr1___width 1 | |
187 | #define reg_timer_r_masked_intr___tmr1___bit 1 | |
188 | #define reg_timer_r_masked_intr___cnt___lsb 2 | |
189 | #define reg_timer_r_masked_intr___cnt___width 1 | |
190 | #define reg_timer_r_masked_intr___cnt___bit 2 | |
191 | #define reg_timer_r_masked_intr___trig___lsb 3 | |
192 | #define reg_timer_r_masked_intr___trig___width 1 | |
193 | #define reg_timer_r_masked_intr___trig___bit 3 | |
194 | #define reg_timer_r_masked_intr_offset 84 | |
195 | ||
196 | /* Register rw_test, scope timer, type rw */ | |
197 | #define reg_timer_rw_test___dis___lsb 0 | |
198 | #define reg_timer_rw_test___dis___width 1 | |
199 | #define reg_timer_rw_test___dis___bit 0 | |
200 | #define reg_timer_rw_test___en___lsb 1 | |
201 | #define reg_timer_rw_test___en___width 1 | |
202 | #define reg_timer_rw_test___en___bit 1 | |
203 | #define reg_timer_rw_test_offset 88 | |
204 | ||
205 | ||
206 | /* Constants */ | |
207 | #define regk_timer_ext 0x00000001 | |
208 | #define regk_timer_f100 0x00000007 | |
209 | #define regk_timer_f29_493 0x00000004 | |
210 | #define regk_timer_f32 0x00000005 | |
211 | #define regk_timer_f32_768 0x00000006 | |
212 | #define regk_timer_hold 0x00000001 | |
213 | #define regk_timer_ld 0x00000000 | |
214 | #define regk_timer_no 0x00000000 | |
215 | #define regk_timer_off 0x00000000 | |
216 | #define regk_timer_run 0x00000002 | |
217 | #define regk_timer_rw_cnt_cfg_default 0x00000000 | |
218 | #define regk_timer_rw_intr_mask_default 0x00000000 | |
219 | #define regk_timer_rw_out_default 0x00000000 | |
220 | #define regk_timer_rw_test_default 0x00000000 | |
221 | #define regk_timer_rw_tmr0_ctrl_default 0x00000000 | |
222 | #define regk_timer_rw_tmr1_ctrl_default 0x00000000 | |
223 | #define regk_timer_rw_trig_cfg_default 0x00000000 | |
224 | #define regk_timer_start 0x00000001 | |
225 | #define regk_timer_stop 0x00000000 | |
226 | #define regk_timer_time 0x00000001 | |
227 | #define regk_timer_tmr0 0x00000002 | |
228 | #define regk_timer_tmr1 0x00000003 | |
229 | #define regk_timer_yes 0x00000001 | |
230 | #endif /* __timer_defs_asm_h */ |