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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51533b61 MS |
2 | #ifndef __config_defs_h |
3 | #define __config_defs_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../rtl/config_regs.r | |
8 | * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp | |
9 | * last modfied: Thu Mar 4 12:34:39 2004 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r | |
12 | * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | /* Main access macros */ | |
18 | #ifndef REG_RD | |
19 | #define REG_RD( scope, inst, reg ) \ | |
20 | REG_READ( reg_##scope##_##reg, \ | |
21 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_WR | |
25 | #define REG_WR( scope, inst, reg, val ) \ | |
26 | REG_WRITE( reg_##scope##_##reg, \ | |
27 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_RD_VECT | |
31 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
32 | REG_READ( reg_##scope##_##reg, \ | |
33 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
34 | (index) * STRIDE_##scope##_##reg ) | |
35 | #endif | |
36 | ||
37 | #ifndef REG_WR_VECT | |
38 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
39 | REG_WRITE( reg_##scope##_##reg, \ | |
40 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
41 | (index) * STRIDE_##scope##_##reg, (val) ) | |
42 | #endif | |
43 | ||
44 | #ifndef REG_RD_INT | |
45 | #define REG_RD_INT( scope, inst, reg ) \ | |
46 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_WR_INT | |
50 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
51 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
52 | #endif | |
53 | ||
54 | #ifndef REG_RD_INT_VECT | |
55 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
56 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
57 | (index) * STRIDE_##scope##_##reg ) | |
58 | #endif | |
59 | ||
60 | #ifndef REG_WR_INT_VECT | |
61 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
62 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
63 | (index) * STRIDE_##scope##_##reg, (val) ) | |
64 | #endif | |
65 | ||
66 | #ifndef REG_TYPE_CONV | |
67 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
68 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
69 | #endif | |
70 | ||
71 | #ifndef reg_page_size | |
72 | #define reg_page_size 8192 | |
73 | #endif | |
74 | ||
75 | #ifndef REG_ADDR | |
76 | #define REG_ADDR( scope, inst, reg ) \ | |
77 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
78 | #endif | |
79 | ||
80 | #ifndef REG_ADDR_VECT | |
81 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
82 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
83 | (index) * STRIDE_##scope##_##reg ) | |
84 | #endif | |
85 | ||
86 | /* C-code for register scope config */ | |
87 | ||
88 | /* Register r_bootsel, scope config, type r */ | |
89 | typedef struct { | |
90 | unsigned int boot_mode : 3; | |
91 | unsigned int full_duplex : 1; | |
92 | unsigned int user : 1; | |
93 | unsigned int pll : 1; | |
94 | unsigned int flash_bw : 1; | |
95 | unsigned int dummy1 : 25; | |
96 | } reg_config_r_bootsel; | |
97 | #define REG_RD_ADDR_config_r_bootsel 0 | |
98 | ||
99 | /* Register rw_clk_ctrl, scope config, type rw */ | |
100 | typedef struct { | |
101 | unsigned int pll : 1; | |
102 | unsigned int cpu : 1; | |
103 | unsigned int iop : 1; | |
104 | unsigned int dma01_eth0 : 1; | |
105 | unsigned int dma23 : 1; | |
106 | unsigned int dma45 : 1; | |
107 | unsigned int dma67 : 1; | |
108 | unsigned int dma89_strcop : 1; | |
109 | unsigned int bif : 1; | |
110 | unsigned int fix_io : 1; | |
111 | unsigned int dummy1 : 22; | |
112 | } reg_config_rw_clk_ctrl; | |
113 | #define REG_RD_ADDR_config_rw_clk_ctrl 4 | |
114 | #define REG_WR_ADDR_config_rw_clk_ctrl 4 | |
115 | ||
116 | /* Register rw_pad_ctrl, scope config, type rw */ | |
117 | typedef struct { | |
118 | unsigned int usb_susp : 1; | |
119 | unsigned int phyrst_n : 1; | |
120 | unsigned int dummy1 : 30; | |
121 | } reg_config_rw_pad_ctrl; | |
122 | #define REG_RD_ADDR_config_rw_pad_ctrl 8 | |
123 | #define REG_WR_ADDR_config_rw_pad_ctrl 8 | |
124 | ||
125 | ||
126 | /* Constants */ | |
127 | enum { | |
128 | regk_config_bw16 = 0x00000000, | |
129 | regk_config_bw32 = 0x00000001, | |
130 | regk_config_master = 0x00000005, | |
131 | regk_config_nand = 0x00000003, | |
132 | regk_config_net_rx = 0x00000001, | |
133 | regk_config_net_tx_rx = 0x00000002, | |
134 | regk_config_no = 0x00000000, | |
135 | regk_config_none = 0x00000007, | |
136 | regk_config_nor = 0x00000000, | |
137 | regk_config_rw_clk_ctrl_default = 0x00000002, | |
138 | regk_config_rw_pad_ctrl_default = 0x00000000, | |
139 | regk_config_ser = 0x00000004, | |
140 | regk_config_slave = 0x00000006, | |
141 | regk_config_yes = 0x00000001 | |
142 | }; | |
143 | #endif /* __config_defs_h */ |