[mirror_ubuntu-eoan-kernel.git] / arch / cris / include / arch-v32 / arch / hwregs / dma_defs.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __dma_defs_h
#define __dma_defs_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
 *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
 *     last modfied: Mon Apr 11 16:06:51 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
 *      id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope dma */

/* Register rw_data, scope dma, type rw */
typedef unsigned int reg_dma_rw_data;
#define REG_RD_ADDR_dma_rw_data 0
#define REG_WR_ADDR_dma_rw_data 0

/* Register rw_data_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_next;
#define REG_RD_ADDR_dma_rw_data_next 4
#define REG_WR_ADDR_dma_rw_data_next 4

/* Register rw_data_buf, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_buf;
#define REG_RD_ADDR_dma_rw_data_buf 8
#define REG_WR_ADDR_dma_rw_data_buf 8

/* Register rw_data_ctrl, scope dma, type rw */
typedef struct {
  unsigned int eol     : 1;
  unsigned int dummy1  : 2;
  unsigned int out_eop : 1;
  unsigned int intr    : 1;
  unsigned int wait    : 1;
  unsigned int dummy2  : 26;
} reg_dma_rw_data_ctrl;
#define REG_RD_ADDR_dma_rw_data_ctrl 12
#define REG_WR_ADDR_dma_rw_data_ctrl 12

/* Register rw_data_stat, scope dma, type rw */
typedef struct {
  unsigned int dummy1 : 3;
  unsigned int in_eop : 1;
  unsigned int dummy2 : 28;
} reg_dma_rw_data_stat;
#define REG_RD_ADDR_dma_rw_data_stat 16
#define REG_WR_ADDR_dma_rw_data_stat 16

/* Register rw_data_md, scope dma, type rw */
typedef struct {
  unsigned int md : 16;
  unsigned int dummy1 : 16;
} reg_dma_rw_data_md;
#define REG_RD_ADDR_dma_rw_data_md 20
#define REG_WR_ADDR_dma_rw_data_md 20

/* Register rw_data_md_s, scope dma, type rw */
typedef struct {
  unsigned int md_s : 16;
  unsigned int dummy1 : 16;
} reg_dma_rw_data_md_s;
#define REG_RD_ADDR_dma_rw_data_md_s 24
#define REG_WR_ADDR_dma_rw_data_md_s 24

/* Register rw_data_after, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_after;
#define REG_RD_ADDR_dma_rw_data_after 28
#define REG_WR_ADDR_dma_rw_data_after 28

/* Register rw_ctxt, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt;
#define REG_RD_ADDR_dma_rw_ctxt 32
#define REG_WR_ADDR_dma_rw_ctxt 32

/* Register rw_ctxt_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_next;
#define REG_RD_ADDR_dma_rw_ctxt_next 36
#define REG_WR_ADDR_dma_rw_ctxt_next 36

/* Register rw_ctxt_ctrl, scope dma, type rw */
typedef struct {
  unsigned int eol        : 1;
  unsigned int dummy1     : 3;
  unsigned int intr       : 1;
  unsigned int dummy2     : 1;
  unsigned int store_mode : 1;
  unsigned int en         : 1;
  unsigned int dummy3     : 24;
} reg_dma_rw_ctxt_ctrl;
#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40

/* Register rw_ctxt_stat, scope dma, type rw */
typedef struct {
  unsigned int dummy1 : 7;
  unsigned int dis : 1;
  unsigned int dummy2 : 24;
} reg_dma_rw_ctxt_stat;
#define REG_RD_ADDR_dma_rw_ctxt_stat 44
#define REG_WR_ADDR_dma_rw_ctxt_stat 44

/* Register rw_ctxt_md0, scope dma, type rw */
typedef struct {
  unsigned int md0 : 16;
  unsigned int dummy1 : 16;
} reg_dma_rw_ctxt_md0;
#define REG_RD_ADDR_dma_rw_ctxt_md0 48
#define REG_WR_ADDR_dma_rw_ctxt_md0 48

/* Register rw_ctxt_md0_s, scope dma, type rw */
typedef struct {
  unsigned int md0_s : 16;
  unsigned int dummy1 : 16;
} reg_dma_rw_ctxt_md0_s;
#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52

/* Register rw_ctxt_md1, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md1;
#define REG_RD_ADDR_dma_rw_ctxt_md1 56
#define REG_WR_ADDR_dma_rw_ctxt_md1 56

/* Register rw_ctxt_md1_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md1_s;
#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60

/* Register rw_ctxt_md2, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md2;
#define REG_RD_ADDR_dma_rw_ctxt_md2 64
#define REG_WR_ADDR_dma_rw_ctxt_md2 64

/* Register rw_ctxt_md2_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md2_s;
#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68

/* Register rw_ctxt_md3, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md3;
#define REG_RD_ADDR_dma_rw_ctxt_md3 72
#define REG_WR_ADDR_dma_rw_ctxt_md3 72

/* Register rw_ctxt_md3_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md3_s;
#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76

/* Register rw_ctxt_md4, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md4;
#define REG_RD_ADDR_dma_rw_ctxt_md4 80
#define REG_WR_ADDR_dma_rw_ctxt_md4 80

/* Register rw_ctxt_md4_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md4_s;
#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84

/* Register rw_saved_data, scope dma, type rw */
typedef unsigned int reg_dma_rw_saved_data;
#define REG_RD_ADDR_dma_rw_saved_data 88
#define REG_WR_ADDR_dma_rw_saved_data 88

/* Register rw_saved_data_buf, scope dma, type rw */
typedef unsigned int reg_dma_rw_saved_data_buf;
#define REG_RD_ADDR_dma_rw_saved_data_buf 92
#define REG_WR_ADDR_dma_rw_saved_data_buf 92

/* Register rw_group, scope dma, type rw */
typedef unsigned int reg_dma_rw_group;
#define REG_RD_ADDR_dma_rw_group 96
#define REG_WR_ADDR_dma_rw_group 96

/* Register rw_group_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_next;
#define REG_RD_ADDR_dma_rw_group_next 100
#define REG_WR_ADDR_dma_rw_group_next 100

/* Register rw_group_ctrl, scope dma, type rw */
typedef struct {
  unsigned int eol  : 1;
  unsigned int tol  : 1;
  unsigned int bol  : 1;
  unsigned int dummy1 : 1;
  unsigned int intr : 1;
  unsigned int dummy2 : 2;
  unsigned int en   : 1;
  unsigned int dummy3 : 24;
} reg_dma_rw_group_ctrl;
#define REG_RD_ADDR_dma_rw_group_ctrl 104
#define REG_WR_ADDR_dma_rw_group_ctrl 104

/* Register rw_group_stat, scope dma, type rw */
typedef struct {
  unsigned int dummy1 : 7;
  unsigned int dis : 1;
  unsigned int dummy2 : 24;
} reg_dma_rw_group_stat;
#define REG_RD_ADDR_dma_rw_group_stat 108
#define REG_WR_ADDR_dma_rw_group_stat 108

/* Register rw_group_md, scope dma, type rw */
typedef struct {
  unsigned int md : 16;
  unsigned int dummy1 : 16;
} reg_dma_rw_group_md;
#define REG_RD_ADDR_dma_rw_group_md 112
#define REG_WR_ADDR_dma_rw_group_md 112

/* Register rw_group_md_s, scope dma, type rw */
typedef struct {
  unsigned int md_s : 16;
  unsigned int dummy1 : 16;
} reg_dma_rw_group_md_s;
#define REG_RD_ADDR_dma_rw_group_md_s 116
#define REG_WR_ADDR_dma_rw_group_md_s 116

/* Register rw_group_up, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_up;
#define REG_RD_ADDR_dma_rw_group_up 120
#define REG_WR_ADDR_dma_rw_group_up 120

/* Register rw_group_down, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_down;
#define REG_RD_ADDR_dma_rw_group_down 124
#define REG_WR_ADDR_dma_rw_group_down 124

/* Register rw_cmd, scope dma, type rw */
typedef struct {
  unsigned int cont_data : 1;
  unsigned int dummy1    : 31;
} reg_dma_rw_cmd;
#define REG_RD_ADDR_dma_rw_cmd 128
#define REG_WR_ADDR_dma_rw_cmd 128

/* Register rw_cfg, scope dma, type rw */
typedef struct {
  unsigned int en   : 1;
  unsigned int stop : 1;
  unsigned int dummy1 : 30;
} reg_dma_rw_cfg;
#define REG_RD_ADDR_dma_rw_cfg 132
#define REG_WR_ADDR_dma_rw_cfg 132

/* Register rw_stat, scope dma, type rw */
typedef struct {
  unsigned int mode           : 5;
  unsigned int list_state     : 3;
  unsigned int stream_cmd_src : 8;
  unsigned int dummy1         : 8;
  unsigned int buf            : 8;
} reg_dma_rw_stat;
#define REG_RD_ADDR_dma_rw_stat 136
#define REG_WR_ADDR_dma_rw_stat 136

/* Register rw_intr_mask, scope dma, type rw */
typedef struct {
  unsigned int group      : 1;
  unsigned int ctxt       : 1;
  unsigned int data       : 1;
  unsigned int in_eop     : 1;
  unsigned int stream_cmd : 1;
  unsigned int dummy1     : 27;
} reg_dma_rw_intr_mask;
#define REG_RD_ADDR_dma_rw_intr_mask 140
#define REG_WR_ADDR_dma_rw_intr_mask 140

/* Register rw_ack_intr, scope dma, type rw */
typedef struct {
  unsigned int group      : 1;
  unsigned int ctxt       : 1;
  unsigned int data       : 1;
  unsigned int in_eop     : 1;
  unsigned int stream_cmd : 1;
  unsigned int dummy1     : 27;
} reg_dma_rw_ack_intr;
#define REG_RD_ADDR_dma_rw_ack_intr 144
#define REG_WR_ADDR_dma_rw_ack_intr 144

/* Register r_intr, scope dma, type r */
typedef struct {
  unsigned int group      : 1;
  unsigned int ctxt       : 1;
  unsigned int data       : 1;
  unsigned int in_eop     : 1;
  unsigned int stream_cmd : 1;
  unsigned int dummy1     : 27;
} reg_dma_r_intr;
#define REG_RD_ADDR_dma_r_intr 148

/* Register r_masked_intr, scope dma, type r */
typedef struct {
  unsigned int group      : 1;
  unsigned int ctxt       : 1;
  unsigned int data       : 1;
  unsigned int in_eop     : 1;
  unsigned int stream_cmd : 1;
  unsigned int dummy1     : 27;
} reg_dma_r_masked_intr;
#define REG_RD_ADDR_dma_r_masked_intr 152

/* Register rw_stream_cmd, scope dma, type rw */
typedef struct {
  unsigned int cmd  : 10;
  unsigned int dummy1 : 6;
  unsigned int n    : 8;
  unsigned int dummy2 : 7;
  unsigned int busy : 1;
} reg_dma_rw_stream_cmd;
#define REG_RD_ADDR_dma_rw_stream_cmd 156
#define REG_WR_ADDR_dma_rw_stream_cmd 156


/* Constants */
enum {
  regk_dma_ack_pkt                         = 0x00000100,
  regk_dma_anytime                         = 0x00000001,
  regk_dma_array                           = 0x00000008,
  regk_dma_burst                           = 0x00000020,
  regk_dma_client                          = 0x00000002,
  regk_dma_copy_next                       = 0x00000010,
  regk_dma_copy_up                         = 0x00000020,
  regk_dma_data_at_eol                     = 0x00000001,
  regk_dma_dis_c                           = 0x00000010,
  regk_dma_dis_g                           = 0x00000020,
  regk_dma_idle                            = 0x00000001,
  regk_dma_intern                          = 0x00000004,
  regk_dma_load_c                          = 0x00000200,
  regk_dma_load_c_n                        = 0x00000280,
  regk_dma_load_c_next                     = 0x00000240,
  regk_dma_load_d                          = 0x00000140,
  regk_dma_load_g                          = 0x00000300,
  regk_dma_load_g_down                     = 0x000003c0,
  regk_dma_load_g_next                     = 0x00000340,
  regk_dma_load_g_up                       = 0x00000380,
  regk_dma_next_en                         = 0x00000010,
  regk_dma_next_pkt                        = 0x00000010,
  regk_dma_no                              = 0x00000000,
  regk_dma_only_at_wait                    = 0x00000000,
  regk_dma_restore                         = 0x00000020,
  regk_dma_rst                             = 0x00000001,
  regk_dma_running                         = 0x00000004,
  regk_dma_rw_cfg_default                  = 0x00000000,
  regk_dma_rw_cmd_default                  = 0x00000000,
  regk_dma_rw_intr_mask_default            = 0x00000000,
  regk_dma_rw_stat_default                 = 0x00000101,
  regk_dma_rw_stream_cmd_default           = 0x00000000,
  regk_dma_save_down                       = 0x00000020,
  regk_dma_save_up                         = 0x00000020,
  regk_dma_set_reg                         = 0x00000050,
  regk_dma_set_w_size1                     = 0x00000190,
  regk_dma_set_w_size2                     = 0x000001a0,
  regk_dma_set_w_size4                     = 0x000001c0,
  regk_dma_stopped                         = 0x00000002,
  regk_dma_store_c                         = 0x00000002,
  regk_dma_store_descr                     = 0x00000000,
  regk_dma_store_g                         = 0x00000004,
  regk_dma_store_md                        = 0x00000001,
  regk_dma_sw                              = 0x00000008,
  regk_dma_update_down                     = 0x00000020,
  regk_dma_yes                             = 0x00000001
};
#endif /* __dma_defs_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
51533b61 MS	2	#ifndef __dma_defs_h
	3	#define __dma_defs_h
	4
	5	/*
	6	* This file is autogenerated from
	7	* file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
	8	* id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
	9	* last modfied: Mon Apr 11 16:06:51 2005
	10	*
	11	* by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
	12	* id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
	13	* Any changes here will be lost.
	14	*
	15	* -- buffer-read-only: t --
	16	*/
	17	/* Main access macros */
	18	#ifndef REG_RD
	19	#define REG_RD( scope, inst, reg ) \
	20	REG_READ( reg_##scope##_##reg, \
	21	(inst) + REG_RD_ADDR_##scope##_##reg )
	22	#endif
	23
	24	#ifndef REG_WR
	25	#define REG_WR( scope, inst, reg, val ) \
	26	REG_WRITE( reg_##scope##_##reg, \
	27	(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	28	#endif
	29
	30	#ifndef REG_RD_VECT
	31	#define REG_RD_VECT( scope, inst, reg, index ) \
	32	REG_READ( reg_##scope##_##reg, \
	33	(inst) + REG_RD_ADDR_##scope##_##reg + \
	34	(index) * STRIDE_##scope##_##reg )
	35	#endif
	36
	37	#ifndef REG_WR_VECT
	38	#define REG_WR_VECT( scope, inst, reg, index, val ) \
	39	REG_WRITE( reg_##scope##_##reg, \
	40	(inst) + REG_WR_ADDR_##scope##_##reg + \
	41	(index) * STRIDE_##scope##_##reg, (val) )
	42	#endif
	43
	44	#ifndef REG_RD_INT
	45	#define REG_RD_INT( scope, inst, reg ) \
	46	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
	47	#endif
	48
	49	#ifndef REG_WR_INT
	50	#define REG_WR_INT( scope, inst, reg, val ) \
	51	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	52	#endif
	53
	54	#ifndef REG_RD_INT_VECT
	55	#define REG_RD_INT_VECT( scope, inst, reg, index ) \
	56	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	57	(index) * STRIDE_##scope##_##reg )
	58	#endif
	59
	60	#ifndef REG_WR_INT_VECT
	61	#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
	62	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	63	(index) * STRIDE_##scope##_##reg, (val) )
	64	#endif
	65
66	#ifndef REG_TYPE_CONV
67	#define REG_TYPE_CONV( type, orgtype, val ) \
68	( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69	#endif
70
71	#ifndef reg_page_size
72	#define reg_page_size 8192
73	#endif
74
75	#ifndef REG_ADDR
76	#define REG_ADDR( scope, inst, reg ) \
77	( (inst) + REG_RD_ADDR_##scope##_##reg )
78	#endif
79
80	#ifndef REG_ADDR_VECT
81	#define REG_ADDR_VECT( scope, inst, reg, index ) \
82	( (inst) + REG_RD_ADDR_##scope##_##reg + \
83	(index) * STRIDE_##scope##_##reg )
84	#endif
85
86	/* C-code for register scope dma */
87
88	/* Register rw_data, scope dma, type rw */
89	typedef unsigned int reg_dma_rw_data;
90	#define REG_RD_ADDR_dma_rw_data 0
91	#define REG_WR_ADDR_dma_rw_data 0
92
93	/* Register rw_data_next, scope dma, type rw */
94	typedef unsigned int reg_dma_rw_data_next;
95	#define REG_RD_ADDR_dma_rw_data_next 4
96	#define REG_WR_ADDR_dma_rw_data_next 4
97
98	/* Register rw_data_buf, scope dma, type rw */
99	typedef unsigned int reg_dma_rw_data_buf;
100	#define REG_RD_ADDR_dma_rw_data_buf 8
101	#define REG_WR_ADDR_dma_rw_data_buf 8
102
103	/* Register rw_data_ctrl, scope dma, type rw */
104	typedef struct {
105	unsigned int eol : 1;
106	unsigned int dummy1 : 2;
107	unsigned int out_eop : 1;
108	unsigned int intr : 1;
109	unsigned int wait : 1;
110	unsigned int dummy2 : 26;
111	} reg_dma_rw_data_ctrl;
112	#define REG_RD_ADDR_dma_rw_data_ctrl 12
113	#define REG_WR_ADDR_dma_rw_data_ctrl 12
114
115	/* Register rw_data_stat, scope dma, type rw */
116	typedef struct {
117	unsigned int dummy1 : 3;
118	unsigned int in_eop : 1;
119	unsigned int dummy2 : 28;
120	} reg_dma_rw_data_stat;
121	#define REG_RD_ADDR_dma_rw_data_stat 16
122	#define REG_WR_ADDR_dma_rw_data_stat 16
123
124	/* Register rw_data_md, scope dma, type rw */
125	typedef struct {
126	unsigned int md : 16;
127	unsigned int dummy1 : 16;
128	} reg_dma_rw_data_md;
129	#define REG_RD_ADDR_dma_rw_data_md 20
130	#define REG_WR_ADDR_dma_rw_data_md 20
131
132	/* Register rw_data_md_s, scope dma, type rw */
133	typedef struct {
134	unsigned int md_s : 16;
135	unsigned int dummy1 : 16;
136	} reg_dma_rw_data_md_s;
137	#define REG_RD_ADDR_dma_rw_data_md_s 24
138	#define REG_WR_ADDR_dma_rw_data_md_s 24
139
140	/* Register rw_data_after, scope dma, type rw */
141	typedef unsigned int reg_dma_rw_data_after;
142	#define REG_RD_ADDR_dma_rw_data_after 28
143	#define REG_WR_ADDR_dma_rw_data_after 28
144
145	/* Register rw_ctxt, scope dma, type rw */
146	typedef unsigned int reg_dma_rw_ctxt;
147	#define REG_RD_ADDR_dma_rw_ctxt 32
148	#define REG_WR_ADDR_dma_rw_ctxt 32
149
150	/* Register rw_ctxt_next, scope dma, type rw */
151	typedef unsigned int reg_dma_rw_ctxt_next;
152	#define REG_RD_ADDR_dma_rw_ctxt_next 36
153	#define REG_WR_ADDR_dma_rw_ctxt_next 36
154
155	/* Register rw_ctxt_ctrl, scope dma, type rw */
156	typedef struct {
157	unsigned int eol : 1;
158	unsigned int dummy1 : 3;
159	unsigned int intr : 1;
160	unsigned int dummy2 : 1;
161	unsigned int store_mode : 1;
162	unsigned int en : 1;
163	unsigned int dummy3 : 24;
164	} reg_dma_rw_ctxt_ctrl;
165	#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
166	#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
167
168	/* Register rw_ctxt_stat, scope dma, type rw */
169	typedef struct {
170	unsigned int dummy1 : 7;
171	unsigned int dis : 1;
172	unsigned int dummy2 : 24;
173	} reg_dma_rw_ctxt_stat;
174	#define REG_RD_ADDR_dma_rw_ctxt_stat 44
175	#define REG_WR_ADDR_dma_rw_ctxt_stat 44
176
177	/* Register rw_ctxt_md0, scope dma, type rw */
178	typedef struct {
179	unsigned int md0 : 16;
180	unsigned int dummy1 : 16;
181	} reg_dma_rw_ctxt_md0;
182	#define REG_RD_ADDR_dma_rw_ctxt_md0 48
183	#define REG_WR_ADDR_dma_rw_ctxt_md0 48
184
185	/* Register rw_ctxt_md0_s, scope dma, type rw */
186	typedef struct {
187	unsigned int md0_s : 16;
188	unsigned int dummy1 : 16;
189	} reg_dma_rw_ctxt_md0_s;
190	#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
191	#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
192
193	/* Register rw_ctxt_md1, scope dma, type rw */
194	typedef unsigned int reg_dma_rw_ctxt_md1;
195	#define REG_RD_ADDR_dma_rw_ctxt_md1 56
196	#define REG_WR_ADDR_dma_rw_ctxt_md1 56
197
198	/* Register rw_ctxt_md1_s, scope dma, type rw */
199	typedef unsigned int reg_dma_rw_ctxt_md1_s;
200	#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
201	#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
202
203	/* Register rw_ctxt_md2, scope dma, type rw */
204	typedef unsigned int reg_dma_rw_ctxt_md2;
205	#define REG_RD_ADDR_dma_rw_ctxt_md2 64
206	#define REG_WR_ADDR_dma_rw_ctxt_md2 64
207
208	/* Register rw_ctxt_md2_s, scope dma, type rw */
209	typedef unsigned int reg_dma_rw_ctxt_md2_s;
210	#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
211	#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
212
213	/* Register rw_ctxt_md3, scope dma, type rw */
214	typedef unsigned int reg_dma_rw_ctxt_md3;
215	#define REG_RD_ADDR_dma_rw_ctxt_md3 72
216	#define REG_WR_ADDR_dma_rw_ctxt_md3 72
217
218	/* Register rw_ctxt_md3_s, scope dma, type rw */
219	typedef unsigned int reg_dma_rw_ctxt_md3_s;
220	#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
221	#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
222
223	/* Register rw_ctxt_md4, scope dma, type rw */
224	typedef unsigned int reg_dma_rw_ctxt_md4;
225	#define REG_RD_ADDR_dma_rw_ctxt_md4 80
226	#define REG_WR_ADDR_dma_rw_ctxt_md4 80
227
228	/* Register rw_ctxt_md4_s, scope dma, type rw */
229	typedef unsigned int reg_dma_rw_ctxt_md4_s;
230	#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
231	#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
232
233	/* Register rw_saved_data, scope dma, type rw */
234	typedef unsigned int reg_dma_rw_saved_data;
235	#define REG_RD_ADDR_dma_rw_saved_data 88
236	#define REG_WR_ADDR_dma_rw_saved_data 88
237
238	/* Register rw_saved_data_buf, scope dma, type rw */
239	typedef unsigned int reg_dma_rw_saved_data_buf;
240	#define REG_RD_ADDR_dma_rw_saved_data_buf 92
241	#define REG_WR_ADDR_dma_rw_saved_data_buf 92
242
243	/* Register rw_group, scope dma, type rw */
244	typedef unsigned int reg_dma_rw_group;
245	#define REG_RD_ADDR_dma_rw_group 96
246	#define REG_WR_ADDR_dma_rw_group 96
247
248	/* Register rw_group_next, scope dma, type rw */
249	typedef unsigned int reg_dma_rw_group_next;
250	#define REG_RD_ADDR_dma_rw_group_next 100
251	#define REG_WR_ADDR_dma_rw_group_next 100
252
253	/* Register rw_group_ctrl, scope dma, type rw */
254	typedef struct {
255	unsigned int eol : 1;
256	unsigned int tol : 1;
257	unsigned int bol : 1;
258	unsigned int dummy1 : 1;
259	unsigned int intr : 1;
260	unsigned int dummy2 : 2;
261	unsigned int en : 1;
262	unsigned int dummy3 : 24;
263	} reg_dma_rw_group_ctrl;
264	#define REG_RD_ADDR_dma_rw_group_ctrl 104
265	#define REG_WR_ADDR_dma_rw_group_ctrl 104
266
267	/* Register rw_group_stat, scope dma, type rw */
268	typedef struct {
269	unsigned int dummy1 : 7;
270	unsigned int dis : 1;
271	unsigned int dummy2 : 24;
272	} reg_dma_rw_group_stat;
273	#define REG_RD_ADDR_dma_rw_group_stat 108
274	#define REG_WR_ADDR_dma_rw_group_stat 108
275
276	/* Register rw_group_md, scope dma, type rw */
277	typedef struct {
278	unsigned int md : 16;
279	unsigned int dummy1 : 16;
280	} reg_dma_rw_group_md;
281	#define REG_RD_ADDR_dma_rw_group_md 112
282	#define REG_WR_ADDR_dma_rw_group_md 112
283
284	/* Register rw_group_md_s, scope dma, type rw */
285	typedef struct {
286	unsigned int md_s : 16;
287	unsigned int dummy1 : 16;
288	} reg_dma_rw_group_md_s;
289	#define REG_RD_ADDR_dma_rw_group_md_s 116
290	#define REG_WR_ADDR_dma_rw_group_md_s 116
291
292	/* Register rw_group_up, scope dma, type rw */
293	typedef unsigned int reg_dma_rw_group_up;
294	#define REG_RD_ADDR_dma_rw_group_up 120
295	#define REG_WR_ADDR_dma_rw_group_up 120
296
297	/* Register rw_group_down, scope dma, type rw */
298	typedef unsigned int reg_dma_rw_group_down;
299	#define REG_RD_ADDR_dma_rw_group_down 124
300	#define REG_WR_ADDR_dma_rw_group_down 124
301
302	/* Register rw_cmd, scope dma, type rw */
303	typedef struct {
304	unsigned int cont_data : 1;
305	unsigned int dummy1 : 31;
306	} reg_dma_rw_cmd;
307	#define REG_RD_ADDR_dma_rw_cmd 128
308	#define REG_WR_ADDR_dma_rw_cmd 128
309
310	/* Register rw_cfg, scope dma, type rw */
311	typedef struct {
312	unsigned int en : 1;
313	unsigned int stop : 1;
314	unsigned int dummy1 : 30;
315	} reg_dma_rw_cfg;
316	#define REG_RD_ADDR_dma_rw_cfg 132
317	#define REG_WR_ADDR_dma_rw_cfg 132
318
319	/* Register rw_stat, scope dma, type rw */
320	typedef struct {
321	unsigned int mode : 5;
322	unsigned int list_state : 3;
323	unsigned int stream_cmd_src : 8;
324	unsigned int dummy1 : 8;
325	unsigned int buf : 8;
326	} reg_dma_rw_stat;
327	#define REG_RD_ADDR_dma_rw_stat 136
328	#define REG_WR_ADDR_dma_rw_stat 136
329
330	/* Register rw_intr_mask, scope dma, type rw */
331	typedef struct {
332	unsigned int group : 1;
333	unsigned int ctxt : 1;
334	unsigned int data : 1;
335	unsigned int in_eop : 1;
336	unsigned int stream_cmd : 1;
337	unsigned int dummy1 : 27;
338	} reg_dma_rw_intr_mask;
339	#define REG_RD_ADDR_dma_rw_intr_mask 140
340	#define REG_WR_ADDR_dma_rw_intr_mask 140
341
342	/* Register rw_ack_intr, scope dma, type rw */
343	typedef struct {
344	unsigned int group : 1;
345	unsigned int ctxt : 1;
346	unsigned int data : 1;
347	unsigned int in_eop : 1;
348	unsigned int stream_cmd : 1;
349	unsigned int dummy1 : 27;
350	} reg_dma_rw_ack_intr;
351	#define REG_RD_ADDR_dma_rw_ack_intr 144
352	#define REG_WR_ADDR_dma_rw_ack_intr 144
353
354	/* Register r_intr, scope dma, type r */
355	typedef struct {
356	unsigned int group : 1;
357	unsigned int ctxt : 1;
358	unsigned int data : 1;
359	unsigned int in_eop : 1;
360	unsigned int stream_cmd : 1;
361	unsigned int dummy1 : 27;
362	} reg_dma_r_intr;
363	#define REG_RD_ADDR_dma_r_intr 148
364
365	/* Register r_masked_intr, scope dma, type r */
366	typedef struct {
367	unsigned int group : 1;
368	unsigned int ctxt : 1;
369	unsigned int data : 1;
370	unsigned int in_eop : 1;
371	unsigned int stream_cmd : 1;
372	unsigned int dummy1 : 27;
373	} reg_dma_r_masked_intr;
374	#define REG_RD_ADDR_dma_r_masked_intr 152
375
376	/* Register rw_stream_cmd, scope dma, type rw */
377	typedef struct {
378	unsigned int cmd : 10;
379	unsigned int dummy1 : 6;
380	unsigned int n : 8;
381	unsigned int dummy2 : 7;
382	unsigned int busy : 1;
383	} reg_dma_rw_stream_cmd;
384	#define REG_RD_ADDR_dma_rw_stream_cmd 156
385	#define REG_WR_ADDR_dma_rw_stream_cmd 156
386
387
388	/* Constants */
389	enum {
390	regk_dma_ack_pkt = 0x00000100,
391	regk_dma_anytime = 0x00000001,
392	regk_dma_array = 0x00000008,
393	regk_dma_burst = 0x00000020,
394	regk_dma_client = 0x00000002,
395	regk_dma_copy_next = 0x00000010,
396	regk_dma_copy_up = 0x00000020,
397	regk_dma_data_at_eol = 0x00000001,
398	regk_dma_dis_c = 0x00000010,
399	regk_dma_dis_g = 0x00000020,
400	regk_dma_idle = 0x00000001,
401	regk_dma_intern = 0x00000004,
402	regk_dma_load_c = 0x00000200,
403	regk_dma_load_c_n = 0x00000280,
404	regk_dma_load_c_next = 0x00000240,
405	regk_dma_load_d = 0x00000140,
406	regk_dma_load_g = 0x00000300,
407	regk_dma_load_g_down = 0x000003c0,
408	regk_dma_load_g_next = 0x00000340,
409	regk_dma_load_g_up = 0x00000380,
410	regk_dma_next_en = 0x00000010,
411	regk_dma_next_pkt = 0x00000010,
412	regk_dma_no = 0x00000000,
413	regk_dma_only_at_wait = 0x00000000,
414	regk_dma_restore = 0x00000020,
415	regk_dma_rst = 0x00000001,
416	regk_dma_running = 0x00000004,
417	regk_dma_rw_cfg_default = 0x00000000,
418	regk_dma_rw_cmd_default = 0x00000000,
419	regk_dma_rw_intr_mask_default = 0x00000000,
420	regk_dma_rw_stat_default = 0x00000101,
421	regk_dma_rw_stream_cmd_default = 0x00000000,
422	regk_dma_save_down = 0x00000020,
423	regk_dma_save_up = 0x00000020,
424	regk_dma_set_reg = 0x00000050,
425	regk_dma_set_w_size1 = 0x00000190,
426	regk_dma_set_w_size2 = 0x000001a0,
427	regk_dma_set_w_size4 = 0x000001c0,
428	regk_dma_stopped = 0x00000002,
429	regk_dma_store_c = 0x00000002,
430	regk_dma_store_descr = 0x00000000,
431	regk_dma_store_g = 0x00000004,
432	regk_dma_store_md = 0x00000001,
433	regk_dma_sw = 0x00000008,
434	regk_dma_update_down = 0x00000020,
435	regk_dma_yes = 0x00000001
436	};
437	#endif /* __dma_defs_h */