[mirror_ubuntu-bionic-kernel.git] / arch / cris / include / arch-v32 / arch / hwregs / eth_defs.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __eth_defs_h
#define __eth_defs_h

/*
 * This file is autogenerated from
 *   file:           eth.r
 *     id:           eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
 *     last modfied: Mon Jan  9 06:06:41 2006
 *
 *   by /n/asic/design/tools/rdesc/rdes2c eth.r
 *      id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope eth */

/* Register rw_ma0_lo, scope eth, type rw */
typedef struct {
  unsigned int addr : 32;
} reg_eth_rw_ma0_lo;
#define REG_RD_ADDR_eth_rw_ma0_lo 0
#define REG_WR_ADDR_eth_rw_ma0_lo 0

/* Register rw_ma0_hi, scope eth, type rw */
typedef struct {
  unsigned int addr : 16;
  unsigned int dummy1 : 16;
} reg_eth_rw_ma0_hi;
#define REG_RD_ADDR_eth_rw_ma0_hi 4
#define REG_WR_ADDR_eth_rw_ma0_hi 4

/* Register rw_ma1_lo, scope eth, type rw */
typedef struct {
  unsigned int addr : 32;
} reg_eth_rw_ma1_lo;
#define REG_RD_ADDR_eth_rw_ma1_lo 8
#define REG_WR_ADDR_eth_rw_ma1_lo 8

/* Register rw_ma1_hi, scope eth, type rw */
typedef struct {
  unsigned int addr : 16;
  unsigned int dummy1 : 16;
} reg_eth_rw_ma1_hi;
#define REG_RD_ADDR_eth_rw_ma1_hi 12
#define REG_WR_ADDR_eth_rw_ma1_hi 12

/* Register rw_ga_lo, scope eth, type rw */
typedef struct {
  unsigned int tbl : 32;
} reg_eth_rw_ga_lo;
#define REG_RD_ADDR_eth_rw_ga_lo 16
#define REG_WR_ADDR_eth_rw_ga_lo 16

/* Register rw_ga_hi, scope eth, type rw */
typedef struct {
  unsigned int tbl : 32;
} reg_eth_rw_ga_hi;
#define REG_RD_ADDR_eth_rw_ga_hi 20
#define REG_WR_ADDR_eth_rw_ga_hi 20

/* Register rw_gen_ctrl, scope eth, type rw */
typedef struct {
  unsigned int en         : 1;
  unsigned int phy        : 2;
  unsigned int protocol   : 1;
  unsigned int loopback   : 1;
  unsigned int flow_ctrl  : 1;
  unsigned int gtxclk_out : 1;
  unsigned int phyrst_n   : 1;
  unsigned int dummy1     : 24;
} reg_eth_rw_gen_ctrl;
#define REG_RD_ADDR_eth_rw_gen_ctrl 24
#define REG_WR_ADDR_eth_rw_gen_ctrl 24

/* Register rw_rec_ctrl, scope eth, type rw */
typedef struct {
  unsigned int ma0        : 1;
  unsigned int ma1        : 1;
  unsigned int individual : 1;
  unsigned int broadcast  : 1;
  unsigned int undersize  : 1;
  unsigned int oversize   : 1;
  unsigned int bad_crc    : 1;
  unsigned int duplex     : 1;
  unsigned int max_size   : 16;
  unsigned int dummy1     : 8;
} reg_eth_rw_rec_ctrl;
#define REG_RD_ADDR_eth_rw_rec_ctrl 28
#define REG_WR_ADDR_eth_rw_rec_ctrl 28

/* Register rw_tr_ctrl, scope eth, type rw */
typedef struct {
  unsigned int crc         : 1;
  unsigned int pad         : 1;
  unsigned int retry       : 1;
  unsigned int ignore_col  : 1;
  unsigned int cancel      : 1;
  unsigned int hsh_delay   : 1;
  unsigned int ignore_crs  : 1;
  unsigned int carrier_ext : 1;
  unsigned int dummy1      : 24;
} reg_eth_rw_tr_ctrl;
#define REG_RD_ADDR_eth_rw_tr_ctrl 32
#define REG_WR_ADDR_eth_rw_tr_ctrl 32

/* Register rw_clr_err, scope eth, type rw */
typedef struct {
  unsigned int clr : 1;
  unsigned int dummy1 : 31;
} reg_eth_rw_clr_err;
#define REG_RD_ADDR_eth_rw_clr_err 36
#define REG_WR_ADDR_eth_rw_clr_err 36

/* Register rw_mgm_ctrl, scope eth, type rw */
typedef struct {
  unsigned int mdio : 1;
  unsigned int mdoe : 1;
  unsigned int mdc  : 1;
  unsigned int dummy1 : 29;
} reg_eth_rw_mgm_ctrl;
#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
#define REG_WR_ADDR_eth_rw_mgm_ctrl 40

/* Register r_stat, scope eth, type r */
typedef struct {
  unsigned int mdio    : 1;
  unsigned int exc_col : 1;
  unsigned int urun    : 1;
  unsigned int clk_125 : 1;
  unsigned int dummy1  : 28;
} reg_eth_r_stat;
#define REG_RD_ADDR_eth_r_stat 44

/* Register rs_rec_cnt, scope eth, type rs */
typedef struct {
  unsigned int crc_err    : 8;
  unsigned int align_err  : 8;
  unsigned int oversize   : 8;
  unsigned int congestion : 8;
} reg_eth_rs_rec_cnt;
#define REG_RD_ADDR_eth_rs_rec_cnt 48

/* Register r_rec_cnt, scope eth, type r */
typedef struct {
  unsigned int crc_err    : 8;
  unsigned int align_err  : 8;
  unsigned int oversize   : 8;
  unsigned int congestion : 8;
} reg_eth_r_rec_cnt;
#define REG_RD_ADDR_eth_r_rec_cnt 52

/* Register rs_tr_cnt, scope eth, type rs */
typedef struct {
  unsigned int single_col : 8;
  unsigned int mult_col   : 8;
  unsigned int late_col   : 8;
  unsigned int deferred   : 8;
} reg_eth_rs_tr_cnt;
#define REG_RD_ADDR_eth_rs_tr_cnt 56

/* Register r_tr_cnt, scope eth, type r */
typedef struct {
  unsigned int single_col : 8;
  unsigned int mult_col   : 8;
  unsigned int late_col   : 8;
  unsigned int deferred   : 8;
} reg_eth_r_tr_cnt;
#define REG_RD_ADDR_eth_r_tr_cnt 60

/* Register rs_phy_cnt, scope eth, type rs */
typedef struct {
  unsigned int carrier_loss : 8;
  unsigned int sqe_err      : 8;
  unsigned int dummy1       : 16;
} reg_eth_rs_phy_cnt;
#define REG_RD_ADDR_eth_rs_phy_cnt 64

/* Register r_phy_cnt, scope eth, type r */
typedef struct {
  unsigned int carrier_loss : 8;
  unsigned int sqe_err      : 8;
  unsigned int dummy1       : 16;
} reg_eth_r_phy_cnt;
#define REG_RD_ADDR_eth_r_phy_cnt 68

/* Register rw_test_ctrl, scope eth, type rw */
typedef struct {
  unsigned int snmp_inc : 1;
  unsigned int snmp     : 1;
  unsigned int backoff  : 1;
  unsigned int dummy1   : 29;
} reg_eth_rw_test_ctrl;
#define REG_RD_ADDR_eth_rw_test_ctrl 72
#define REG_WR_ADDR_eth_rw_test_ctrl 72

/* Register rw_intr_mask, scope eth, type rw */
typedef struct {
  unsigned int crc          : 1;
  unsigned int align        : 1;
  unsigned int oversize     : 1;
  unsigned int congestion   : 1;
  unsigned int single_col   : 1;
  unsigned int mult_col     : 1;
  unsigned int late_col     : 1;
  unsigned int deferred     : 1;
  unsigned int carrier_loss : 1;
  unsigned int sqe_test_err : 1;
  unsigned int orun         : 1;
  unsigned int urun         : 1;
  unsigned int exc_col      : 1;
  unsigned int mdio         : 1;
  unsigned int dummy1       : 18;
} reg_eth_rw_intr_mask;
#define REG_RD_ADDR_eth_rw_intr_mask 76
#define REG_WR_ADDR_eth_rw_intr_mask 76

/* Register rw_ack_intr, scope eth, type rw */
typedef struct {
  unsigned int crc          : 1;
  unsigned int align        : 1;
  unsigned int oversize     : 1;
  unsigned int congestion   : 1;
  unsigned int single_col   : 1;
  unsigned int mult_col     : 1;
  unsigned int late_col     : 1;
  unsigned int deferred     : 1;
  unsigned int carrier_loss : 1;
  unsigned int sqe_test_err : 1;
  unsigned int orun         : 1;
  unsigned int urun         : 1;
  unsigned int exc_col      : 1;
  unsigned int mdio         : 1;
  unsigned int dummy1       : 18;
} reg_eth_rw_ack_intr;
#define REG_RD_ADDR_eth_rw_ack_intr 80
#define REG_WR_ADDR_eth_rw_ack_intr 80

/* Register r_intr, scope eth, type r */
typedef struct {
  unsigned int crc          : 1;
  unsigned int align        : 1;
  unsigned int oversize     : 1;
  unsigned int congestion   : 1;
  unsigned int single_col   : 1;
  unsigned int mult_col     : 1;
  unsigned int late_col     : 1;
  unsigned int deferred     : 1;
  unsigned int carrier_loss : 1;
  unsigned int sqe_test_err : 1;
  unsigned int orun         : 1;
  unsigned int urun         : 1;
  unsigned int exc_col      : 1;
  unsigned int mdio         : 1;
  unsigned int dummy1       : 18;
} reg_eth_r_intr;
#define REG_RD_ADDR_eth_r_intr 84

/* Register r_masked_intr, scope eth, type r */
typedef struct {
  unsigned int crc          : 1;
  unsigned int align        : 1;
  unsigned int oversize     : 1;
  unsigned int congestion   : 1;
  unsigned int single_col   : 1;
  unsigned int mult_col     : 1;
  unsigned int late_col     : 1;
  unsigned int deferred     : 1;
  unsigned int carrier_loss : 1;
  unsigned int sqe_test_err : 1;
  unsigned int orun         : 1;
  unsigned int urun         : 1;
  unsigned int exc_col      : 1;
  unsigned int mdio         : 1;
  unsigned int dummy1       : 18;
} reg_eth_r_masked_intr;
#define REG_RD_ADDR_eth_r_masked_intr 88


/* Constants */
enum {
  regk_eth_discard                         = 0x00000000,
  regk_eth_ether                           = 0x00000000,
  regk_eth_full                            = 0x00000001,
  regk_eth_gmii                            = 0x00000003,
  regk_eth_gtxclk                          = 0x00000001,
  regk_eth_half                            = 0x00000000,
  regk_eth_hsh                             = 0x00000001,
  regk_eth_mii                             = 0x00000001,
  regk_eth_mii_arec                        = 0x00000002,
  regk_eth_mii_clk                         = 0x00000000,
  regk_eth_no                              = 0x00000000,
  regk_eth_phyrst                          = 0x00000000,
  regk_eth_rec                             = 0x00000001,
  regk_eth_rw_ga_hi_default                = 0x00000000,
  regk_eth_rw_ga_lo_default                = 0x00000000,
  regk_eth_rw_gen_ctrl_default             = 0x00000000,
  regk_eth_rw_intr_mask_default            = 0x00000000,
  regk_eth_rw_ma0_hi_default               = 0x00000000,
  regk_eth_rw_ma0_lo_default               = 0x00000000,
  regk_eth_rw_ma1_hi_default               = 0x00000000,
  regk_eth_rw_ma1_lo_default               = 0x00000000,
  regk_eth_rw_mgm_ctrl_default             = 0x00000000,
  regk_eth_rw_test_ctrl_default            = 0x00000000,
  regk_eth_size1518                        = 0x000005ee,
  regk_eth_size1522                        = 0x000005f2,
  regk_eth_yes                             = 0x00000001
};
#endif /* __eth_defs_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
51533b61 MS	2	#ifndef __eth_defs_h
	3	#define __eth_defs_h
	4
	5	/*
	6	* This file is autogenerated from
6c6dc56c JN	7	* file: eth.r
	8	* id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
	9	* last modfied: Mon Jan 9 06:06:41 2006
51533b61	10	*
6c6dc56c JN	11	* by /n/asic/design/tools/rdesc/rdes2c eth.r
6c6dc56c JN	12	* id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
51533b61 MS	13	* Any changes here will be lost.
	14	*
	15	* -- buffer-read-only: t --
	16	*/
	17	/* Main access macros */
	18	#ifndef REG_RD
	19	#define REG_RD( scope, inst, reg ) \
	20	REG_READ( reg_##scope##_##reg, \
	21	(inst) + REG_RD_ADDR_##scope##_##reg )
	22	#endif
	23
	24	#ifndef REG_WR
	25	#define REG_WR( scope, inst, reg, val ) \
	26	REG_WRITE( reg_##scope##_##reg, \
	27	(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	28	#endif
	29
	30	#ifndef REG_RD_VECT
	31	#define REG_RD_VECT( scope, inst, reg, index ) \
	32	REG_READ( reg_##scope##_##reg, \
	33	(inst) + REG_RD_ADDR_##scope##_##reg + \
	34	(index) * STRIDE_##scope##_##reg )
	35	#endif
	36
	37	#ifndef REG_WR_VECT
	38	#define REG_WR_VECT( scope, inst, reg, index, val ) \
	39	REG_WRITE( reg_##scope##_##reg, \
	40	(inst) + REG_WR_ADDR_##scope##_##reg + \
	41	(index) * STRIDE_##scope##_##reg, (val) )
	42	#endif
	43
	44	#ifndef REG_RD_INT
	45	#define REG_RD_INT( scope, inst, reg ) \
	46	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
	47	#endif
	48
	49	#ifndef REG_WR_INT
	50	#define REG_WR_INT( scope, inst, reg, val ) \
	51	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	52	#endif
	53
	54	#ifndef REG_RD_INT_VECT
	55	#define REG_RD_INT_VECT( scope, inst, reg, index ) \
	56	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	57	(index) * STRIDE_##scope##_##reg )
	58	#endif
	59
	60	#ifndef REG_WR_INT_VECT
	61	#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
	62	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	63	(index) * STRIDE_##scope##_##reg, (val) )
	64	#endif
	65
	66	#ifndef REG_TYPE_CONV
	67	#define REG_TYPE_CONV( type, orgtype, val ) \
	68	( { union { orgtype o; type n; } r; r.o = val; r.n; } )
	69	#endif
	70
	71	#ifndef reg_page_size
	72	#define reg_page_size 8192
	73	#endif
	74
	75	#ifndef REG_ADDR
	76	#define REG_ADDR( scope, inst, reg ) \
77	( (inst) + REG_RD_ADDR_##scope##_##reg )
78	#endif
79
80	#ifndef REG_ADDR_VECT
81	#define REG_ADDR_VECT( scope, inst, reg, index ) \
82	( (inst) + REG_RD_ADDR_##scope##_##reg + \
83	(index) * STRIDE_##scope##_##reg )
84	#endif
85
86	/* C-code for register scope eth */
87
88	/* Register rw_ma0_lo, scope eth, type rw */
89	typedef struct {
90	unsigned int addr : 32;
91	} reg_eth_rw_ma0_lo;
92	#define REG_RD_ADDR_eth_rw_ma0_lo 0
93	#define REG_WR_ADDR_eth_rw_ma0_lo 0
94
95	/* Register rw_ma0_hi, scope eth, type rw */
96	typedef struct {
97	unsigned int addr : 16;
98	unsigned int dummy1 : 16;
99	} reg_eth_rw_ma0_hi;
100	#define REG_RD_ADDR_eth_rw_ma0_hi 4
101	#define REG_WR_ADDR_eth_rw_ma0_hi 4
102
103	/* Register rw_ma1_lo, scope eth, type rw */
104	typedef struct {
105	unsigned int addr : 32;
106	} reg_eth_rw_ma1_lo;
107	#define REG_RD_ADDR_eth_rw_ma1_lo 8
108	#define REG_WR_ADDR_eth_rw_ma1_lo 8
109
110	/* Register rw_ma1_hi, scope eth, type rw */
111	typedef struct {
112	unsigned int addr : 16;
113	unsigned int dummy1 : 16;
114	} reg_eth_rw_ma1_hi;
115	#define REG_RD_ADDR_eth_rw_ma1_hi 12
116	#define REG_WR_ADDR_eth_rw_ma1_hi 12
117
118	/* Register rw_ga_lo, scope eth, type rw */
119	typedef struct {
6c6dc56c	120	unsigned int tbl : 32;
51533b61 MS	121	} reg_eth_rw_ga_lo;
	122	#define REG_RD_ADDR_eth_rw_ga_lo 16
	123	#define REG_WR_ADDR_eth_rw_ga_lo 16
	124
	125	/* Register rw_ga_hi, scope eth, type rw */
	126	typedef struct {
6c6dc56c	127	unsigned int tbl : 32;
51533b61 MS	128	} reg_eth_rw_ga_hi;
	129	#define REG_RD_ADDR_eth_rw_ga_hi 20
	130	#define REG_WR_ADDR_eth_rw_ga_hi 20
	131
	132	/* Register rw_gen_ctrl, scope eth, type rw */
	133	typedef struct {
6c6dc56c JN	134	unsigned int en : 1;
	135	unsigned int phy : 2;
	136	unsigned int protocol : 1;
	137	unsigned int loopback : 1;
	138	unsigned int flow_ctrl : 1;
	139	unsigned int gtxclk_out : 1;
	140	unsigned int phyrst_n : 1;
	141	unsigned int dummy1 : 24;
51533b61 MS	142	} reg_eth_rw_gen_ctrl;
	143	#define REG_RD_ADDR_eth_rw_gen_ctrl 24
	144	#define REG_WR_ADDR_eth_rw_gen_ctrl 24
	145
	146	/* Register rw_rec_ctrl, scope eth, type rw */
	147	typedef struct {
	148	unsigned int ma0 : 1;
	149	unsigned int ma1 : 1;
	150	unsigned int individual : 1;
	151	unsigned int broadcast : 1;
	152	unsigned int undersize : 1;
	153	unsigned int oversize : 1;
	154	unsigned int bad_crc : 1;
	155	unsigned int duplex : 1;
6c6dc56c JN	156	unsigned int max_size : 16;
6c6dc56c JN	157	unsigned int dummy1 : 8;
51533b61 MS	158	} reg_eth_rw_rec_ctrl;
	159	#define REG_RD_ADDR_eth_rw_rec_ctrl 28
	160	#define REG_WR_ADDR_eth_rw_rec_ctrl 28
	161
	162	/* Register rw_tr_ctrl, scope eth, type rw */
	163	typedef struct {
6c6dc56c JN	164	unsigned int crc : 1;
	165	unsigned int pad : 1;
	166	unsigned int retry : 1;
	167	unsigned int ignore_col : 1;
	168	unsigned int cancel : 1;
	169	unsigned int hsh_delay : 1;
	170	unsigned int ignore_crs : 1;
	171	unsigned int carrier_ext : 1;
	172	unsigned int dummy1 : 24;
51533b61 MS	173	} reg_eth_rw_tr_ctrl;
	174	#define REG_RD_ADDR_eth_rw_tr_ctrl 32
	175	#define REG_WR_ADDR_eth_rw_tr_ctrl 32
	176
	177	/* Register rw_clr_err, scope eth, type rw */
	178	typedef struct {
	179	unsigned int clr : 1;
	180	unsigned int dummy1 : 31;
	181	} reg_eth_rw_clr_err;
	182	#define REG_RD_ADDR_eth_rw_clr_err 36
	183	#define REG_WR_ADDR_eth_rw_clr_err 36
	184
	185	/* Register rw_mgm_ctrl, scope eth, type rw */
	186	typedef struct {
6c6dc56c JN	187	unsigned int mdio : 1;
	188	unsigned int mdoe : 1;
	189	unsigned int mdc : 1;
	190	unsigned int dummy1 : 29;
51533b61 MS	191	} reg_eth_rw_mgm_ctrl;
	192	#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
	193	#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
	194
	195	/* Register r_stat, scope eth, type r */
	196	typedef struct {
	197	unsigned int mdio : 1;
	198	unsigned int exc_col : 1;
	199	unsigned int urun : 1;
6c6dc56c JN	200	unsigned int clk_125 : 1;
6c6dc56c JN	201	unsigned int dummy1 : 28;
51533b61 MS	202	} reg_eth_r_stat;
	203	#define REG_RD_ADDR_eth_r_stat 44
	204
	205	/* Register rs_rec_cnt, scope eth, type rs */
	206	typedef struct {
	207	unsigned int crc_err : 8;
	208	unsigned int align_err : 8;
	209	unsigned int oversize : 8;
	210	unsigned int congestion : 8;
	211	} reg_eth_rs_rec_cnt;
	212	#define REG_RD_ADDR_eth_rs_rec_cnt 48
	213
	214	/* Register r_rec_cnt, scope eth, type r */
	215	typedef struct {
	216	unsigned int crc_err : 8;
	217	unsigned int align_err : 8;
	218	unsigned int oversize : 8;
	219	unsigned int congestion : 8;
	220	} reg_eth_r_rec_cnt;
	221	#define REG_RD_ADDR_eth_r_rec_cnt 52
	222
	223	/* Register rs_tr_cnt, scope eth, type rs */
	224	typedef struct {
	225	unsigned int single_col : 8;
	226	unsigned int mult_col : 8;
	227	unsigned int late_col : 8;
	228	unsigned int deferred : 8;
	229	} reg_eth_rs_tr_cnt;
	230	#define REG_RD_ADDR_eth_rs_tr_cnt 56
	231
	232	/* Register r_tr_cnt, scope eth, type r */
	233	typedef struct {
	234	unsigned int single_col : 8;
	235	unsigned int mult_col : 8;
	236	unsigned int late_col : 8;
	237	unsigned int deferred : 8;
	238	} reg_eth_r_tr_cnt;
	239	#define REG_RD_ADDR_eth_r_tr_cnt 60
	240
	241	/* Register rs_phy_cnt, scope eth, type rs */
	242	typedef struct {
	243	unsigned int carrier_loss : 8;
	244	unsigned int sqe_err : 8;
	245	unsigned int dummy1 : 16;
	246	} reg_eth_rs_phy_cnt;
	247	#define REG_RD_ADDR_eth_rs_phy_cnt 64
	248
	249	/* Register r_phy_cnt, scope eth, type r */
	250	typedef struct {
	251	unsigned int carrier_loss : 8;
	252	unsigned int sqe_err : 8;
	253	unsigned int dummy1 : 16;
	254	} reg_eth_r_phy_cnt;
	255	#define REG_RD_ADDR_eth_r_phy_cnt 68
	256
	257	/* Register rw_test_ctrl, scope eth, type rw */
	258	typedef struct {
	259	unsigned int snmp_inc : 1;
	260	unsigned int snmp : 1;
	261	unsigned int backoff : 1;
	262	unsigned int dummy1 : 29;
	263	} reg_eth_rw_test_ctrl;
	264	#define REG_RD_ADDR_eth_rw_test_ctrl 72
	265	#define REG_WR_ADDR_eth_rw_test_ctrl 72
266
267	/* Register rw_intr_mask, scope eth, type rw */
268	typedef struct {
6c6dc56c JN	269	unsigned int crc : 1;
	270	unsigned int align : 1;
	271	unsigned int oversize : 1;
	272	unsigned int congestion : 1;
	273	unsigned int single_col : 1;
	274	unsigned int mult_col : 1;
	275	unsigned int late_col : 1;
	276	unsigned int deferred : 1;
	277	unsigned int carrier_loss : 1;
	278	unsigned int sqe_test_err : 1;
	279	unsigned int orun : 1;
	280	unsigned int urun : 1;
	281	unsigned int exc_col : 1;
	282	unsigned int mdio : 1;
	283	unsigned int dummy1 : 18;
51533b61 MS	284	} reg_eth_rw_intr_mask;
	285	#define REG_RD_ADDR_eth_rw_intr_mask 76
	286	#define REG_WR_ADDR_eth_rw_intr_mask 76
	287
	288	/* Register rw_ack_intr, scope eth, type rw */
	289	typedef struct {
6c6dc56c JN	290	unsigned int crc : 1;
	291	unsigned int align : 1;
	292	unsigned int oversize : 1;
	293	unsigned int congestion : 1;
	294	unsigned int single_col : 1;
	295	unsigned int mult_col : 1;
	296	unsigned int late_col : 1;
	297	unsigned int deferred : 1;
	298	unsigned int carrier_loss : 1;
	299	unsigned int sqe_test_err : 1;
	300	unsigned int orun : 1;
	301	unsigned int urun : 1;
	302	unsigned int exc_col : 1;
	303	unsigned int mdio : 1;
	304	unsigned int dummy1 : 18;
51533b61 MS	305	} reg_eth_rw_ack_intr;
	306	#define REG_RD_ADDR_eth_rw_ack_intr 80
	307	#define REG_WR_ADDR_eth_rw_ack_intr 80
	308
	309	/* Register r_intr, scope eth, type r */
	310	typedef struct {
6c6dc56c JN	311	unsigned int crc : 1;
	312	unsigned int align : 1;
	313	unsigned int oversize : 1;
	314	unsigned int congestion : 1;
	315	unsigned int single_col : 1;
	316	unsigned int mult_col : 1;
	317	unsigned int late_col : 1;
	318	unsigned int deferred : 1;
	319	unsigned int carrier_loss : 1;
	320	unsigned int sqe_test_err : 1;
	321	unsigned int orun : 1;
	322	unsigned int urun : 1;
	323	unsigned int exc_col : 1;
	324	unsigned int mdio : 1;
	325	unsigned int dummy1 : 18;
51533b61 MS	326	} reg_eth_r_intr;
	327	#define REG_RD_ADDR_eth_r_intr 84
	328
	329	/* Register r_masked_intr, scope eth, type r */
	330	typedef struct {
6c6dc56c JN	331	unsigned int crc : 1;
	332	unsigned int align : 1;
	333	unsigned int oversize : 1;
	334	unsigned int congestion : 1;
	335	unsigned int single_col : 1;
	336	unsigned int mult_col : 1;
	337	unsigned int late_col : 1;
	338	unsigned int deferred : 1;
	339	unsigned int carrier_loss : 1;
	340	unsigned int sqe_test_err : 1;
	341	unsigned int orun : 1;
	342	unsigned int urun : 1;
	343	unsigned int exc_col : 1;
	344	unsigned int mdio : 1;
	345	unsigned int dummy1 : 18;
51533b61 MS	346	} reg_eth_r_masked_intr;
	347	#define REG_RD_ADDR_eth_r_masked_intr 88
	348
	349
	350	/* Constants */
	351	enum {
	352	regk_eth_discard = 0x00000000,
	353	regk_eth_ether = 0x00000000,
	354	regk_eth_full = 0x00000001,
6c6dc56c JN	355	regk_eth_gmii = 0x00000003,
6c6dc56c JN	356	regk_eth_gtxclk = 0x00000001,
51533b61 MS	357	regk_eth_half = 0x00000000,
	358	regk_eth_hsh = 0x00000001,
	359	regk_eth_mii = 0x00000001,
6c6dc56c	360	regk_eth_mii_arec = 0x00000002,
51533b61	361	regk_eth_mii_clk = 0x00000000,
51533b61	362	regk_eth_no = 0x00000000,
6c6dc56c	363	regk_eth_phyrst = 0x00000000,
51533b61 MS	364	regk_eth_rec = 0x00000001,
	365	regk_eth_rw_ga_hi_default = 0x00000000,
	366	regk_eth_rw_ga_lo_default = 0x00000000,
	367	regk_eth_rw_gen_ctrl_default = 0x00000000,
	368	regk_eth_rw_intr_mask_default = 0x00000000,
	369	regk_eth_rw_ma0_hi_default = 0x00000000,
	370	regk_eth_rw_ma0_lo_default = 0x00000000,
	371	regk_eth_rw_ma1_hi_default = 0x00000000,
	372	regk_eth_rw_ma1_lo_default = 0x00000000,
	373	regk_eth_rw_mgm_ctrl_default = 0x00000000,
	374	regk_eth_rw_test_ctrl_default = 0x00000000,
6c6dc56c JN	375	regk_eth_size1518 = 0x000005ee,
6c6dc56c JN	376	regk_eth_size1522 = 0x000005f2,
51533b61 MS	377	regk_eth_yes = 0x00000001
	378	};
	379	#endif /* __eth_defs_h */