projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 51533b61 MS |
2 | #ifndef __iop_scrc_in_defs_asm_h |
| 3 | #define __iop_scrc_in_defs_asm_h | |
| 4 | ||
| 5 | /* | |
| 6 | * This file is autogenerated from | |
| 7 | * file: ../../inst/io_proc/rtl/iop_scrc_in.r | |
| 8 | * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp | |
| 9 | * last modfied: Mon Apr 11 16:08:46 2005 | |
| 10 | * | |
| 11 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r | |
| 12 | * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ | |
| 13 | * Any changes here will be lost. | |
| 14 | * | |
| 15 | * -*- buffer-read-only: t -*- | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef REG_FIELD | |
| 19 | #define REG_FIELD( scope, reg, field, value ) \ | |
| 20 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
| 21 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
| 22 | #endif | |
| 23 | ||
| 24 | #ifndef REG_STATE | |
| 25 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
| 26 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
| 27 | #define REG_STATE_X_( k, shift ) (k << shift) | |
| 28 | #endif | |
| 29 | ||
| 30 | #ifndef REG_MASK | |
| 31 | #define REG_MASK( scope, reg, field ) \ | |
| 32 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
| 33 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
| 34 | #endif | |
| 35 | ||
| 36 | #ifndef REG_LSB | |
| 37 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
| 38 | #endif | |
| 39 | ||
| 40 | #ifndef REG_BIT | |
| 41 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
| 42 | #endif | |
| 43 | ||
| 44 | #ifndef REG_ADDR | |
| 45 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
| 46 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
| 47 | #endif | |
| 48 | ||
| 49 | #ifndef REG_ADDR_VECT | |
| 50 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
| 51 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
| 52 | STRIDE_##scope##_##reg ) | |
| 53 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
| 54 | ((inst) + offs + (index) * stride) | |
| 55 | #endif | |
| 56 | ||
| 57 | /* Register rw_cfg, scope iop_scrc_in, type rw */ | |
| 58 | #define reg_iop_scrc_in_rw_cfg___trig___lsb 0 | |
| 59 | #define reg_iop_scrc_in_rw_cfg___trig___width 2 | |
| 60 | #define reg_iop_scrc_in_rw_cfg_offset 0 | |
| 61 | ||
| 62 | /* Register rw_ctrl, scope iop_scrc_in, type rw */ | |
| 63 | #define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 | |
| 64 | #define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 | |
| 65 | #define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 | |
| 66 | #define reg_iop_scrc_in_rw_ctrl_offset 4 | |
| 67 | ||
| 68 | /* Register r_stat, scope iop_scrc_in, type r */ | |
| 69 | #define reg_iop_scrc_in_r_stat___err___lsb 0 | |
| 70 | #define reg_iop_scrc_in_r_stat___err___width 1 | |
| 71 | #define reg_iop_scrc_in_r_stat___err___bit 0 | |
| 72 | #define reg_iop_scrc_in_r_stat_offset 8 | |
| 73 | ||
| 74 | /* Register rw_init_crc, scope iop_scrc_in, type rw */ | |
| 75 | #define reg_iop_scrc_in_rw_init_crc_offset 12 | |
| 76 | ||
| 77 | /* Register rs_computed_crc, scope iop_scrc_in, type rs */ | |
| 78 | #define reg_iop_scrc_in_rs_computed_crc_offset 16 | |
| 79 | ||
| 80 | /* Register r_computed_crc, scope iop_scrc_in, type r */ | |
| 81 | #define reg_iop_scrc_in_r_computed_crc_offset 20 | |
| 82 | ||
| 83 | /* Register rw_crc, scope iop_scrc_in, type rw */ | |
| 84 | #define reg_iop_scrc_in_rw_crc_offset 24 | |
| 85 | ||
| 86 | /* Register rw_correct_crc, scope iop_scrc_in, type rw */ | |
| 87 | #define reg_iop_scrc_in_rw_correct_crc_offset 28 | |
| 88 | ||
| 89 | /* Register rw_wr1bit, scope iop_scrc_in, type rw */ | |
| 90 | #define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 | |
| 91 | #define reg_iop_scrc_in_rw_wr1bit___data___width 2 | |
| 92 | #define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 | |
| 93 | #define reg_iop_scrc_in_rw_wr1bit___last___width 2 | |
| 94 | #define reg_iop_scrc_in_rw_wr1bit_offset 32 | |
| 95 | ||
| 96 | ||
| 97 | /* Constants */ | |
| 98 | #define regk_iop_scrc_in_dif_in 0x00000002 | |
| 99 | #define regk_iop_scrc_in_hi 0x00000000 | |
| 100 | #define regk_iop_scrc_in_neg 0x00000002 | |
| 101 | #define regk_iop_scrc_in_no 0x00000000 | |
| 102 | #define regk_iop_scrc_in_pos 0x00000001 | |
| 103 | #define regk_iop_scrc_in_pos_neg 0x00000003 | |
| 104 | #define regk_iop_scrc_in_r_computed_crc_default 0x00000000 | |
| 105 | #define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 | |
| 106 | #define regk_iop_scrc_in_rw_cfg_default 0x00000000 | |
| 107 | #define regk_iop_scrc_in_rw_ctrl_default 0x00000000 | |
| 108 | #define regk_iop_scrc_in_rw_init_crc_default 0x00000000 | |
| 109 | #define regk_iop_scrc_in_set0 0x00000000 | |
| 110 | #define regk_iop_scrc_in_set1 0x00000001 | |
| 111 | #define regk_iop_scrc_in_yes 0x00000001 | |
| 112 | #endif /* __iop_scrc_in_defs_asm_h */ |