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[mirror_ubuntu-focal-kernel.git] / arch / cris / include / arch-v32 / arch / hwregs / iop / iop_sw_mpu_defs.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
51533b61
MS		 2#ifndef __iop_sw_mpu_defs_h
3#define __iop_sw_mpu_defs_h
4
5/*
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
8 * id: <not found>
9 * last modfied: Mon Apr 11 16:10:19 2005
10 *
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
12 * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
14 *
15 * -*- buffer-read-only: t -*-
16 */
17/* Main access macros */
18#ifndef REG_RD
19#define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
22#endif
23
24#ifndef REG_WR
25#define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28#endif
29
30#ifndef REG_RD_VECT
31#define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
35#endif
36
37#ifndef REG_WR_VECT
38#define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
42#endif
43
44#ifndef REG_RD_INT
45#define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
47#endif
48
49#ifndef REG_WR_INT
50#define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
52#endif
53
54#ifndef REG_RD_INT_VECT
55#define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
58#endif
59
60#ifndef REG_WR_INT_VECT
61#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
64#endif
65
66#ifndef REG_TYPE_CONV
67#define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69#endif
70
71#ifndef reg_page_size
72#define reg_page_size 8192
73#endif
74
75#ifndef REG_ADDR
76#define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
78#endif
79
80#ifndef REG_ADDR_VECT
81#define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
84#endif
85
86/* C-code for register scope iop_sw_mpu */
87
88/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
89typedef struct {
90 unsigned int cfg : 2;
91 unsigned int dummy1 : 30;
92} reg_iop_sw_mpu_rw_sw_cfg_owner;
93#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
94#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
95
96/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
97typedef struct {
98 unsigned int keep_owner : 1;
99 unsigned int cmd : 2;
100 unsigned int size : 3;
101 unsigned int wr_spu0_mem : 1;
102 unsigned int wr_spu1_mem : 1;
103 unsigned int dummy1 : 24;
104} reg_iop_sw_mpu_rw_mc_ctrl;
105#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
106#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
107
108/* Register rw_mc_data, scope iop_sw_mpu, type rw */
109typedef struct {
110 unsigned int val : 32;
111} reg_iop_sw_mpu_rw_mc_data;
112#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
113#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
114
115/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
116typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
117#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
118#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
119
120/* Register rs_mc_data, scope iop_sw_mpu, type rs */
121typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
122#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
123
124/* Register r_mc_data, scope iop_sw_mpu, type r */
125typedef unsigned int reg_iop_sw_mpu_r_mc_data;
126#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
127
128/* Register r_mc_stat, scope iop_sw_mpu, type r */
129typedef struct {
130 unsigned int busy_cpu : 1;
131 unsigned int busy_mpu : 1;
132 unsigned int busy_spu0 : 1;
133 unsigned int busy_spu1 : 1;
134 unsigned int owned_by_cpu : 1;
135 unsigned int owned_by_mpu : 1;
136 unsigned int owned_by_spu0 : 1;
137 unsigned int owned_by_spu1 : 1;
138 unsigned int dummy1 : 24;
139} reg_iop_sw_mpu_r_mc_stat;
140#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
141
142/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
143typedef struct {
144 unsigned int byte0 : 8;
145 unsigned int byte1 : 8;
146 unsigned int byte2 : 8;
147 unsigned int byte3 : 8;
148} reg_iop_sw_mpu_rw_bus0_clr_mask;
149#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
150#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
151
152/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
153typedef struct {
154 unsigned int byte0 : 8;
155 unsigned int byte1 : 8;
156 unsigned int byte2 : 8;
157 unsigned int byte3 : 8;
158} reg_iop_sw_mpu_rw_bus0_set_mask;
159#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
160#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
161
162/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
163typedef struct {
164 unsigned int byte0 : 1;
165 unsigned int byte1 : 1;
166 unsigned int byte2 : 1;
167 unsigned int byte3 : 1;
168 unsigned int dummy1 : 28;
169} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
170#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
171#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
172
173/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
174typedef struct {
175 unsigned int byte0 : 1;
176 unsigned int byte1 : 1;
177 unsigned int byte2 : 1;
178 unsigned int byte3 : 1;
179 unsigned int dummy1 : 28;
180} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
181#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
182#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
183
184/* Register r_bus0_in, scope iop_sw_mpu, type r */
185typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
186#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
187
188/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
189typedef struct {
190 unsigned int byte0 : 8;
191 unsigned int byte1 : 8;
192 unsigned int byte2 : 8;
193 unsigned int byte3 : 8;
194} reg_iop_sw_mpu_rw_bus1_clr_mask;
195#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
196#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
197
198/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
199typedef struct {
200 unsigned int byte0 : 8;
201 unsigned int byte1 : 8;
202 unsigned int byte2 : 8;
203 unsigned int byte3 : 8;
204} reg_iop_sw_mpu_rw_bus1_set_mask;
205#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
206#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
207
208/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
209typedef struct {
210 unsigned int byte0 : 1;
211 unsigned int byte1 : 1;
212 unsigned int byte2 : 1;
213 unsigned int byte3 : 1;
214 unsigned int dummy1 : 28;
215} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
216#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
217#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
218
219/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
220typedef struct {
221 unsigned int byte0 : 1;
222 unsigned int byte1 : 1;
223 unsigned int byte2 : 1;
224 unsigned int byte3 : 1;
225 unsigned int dummy1 : 28;
226} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
227#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
228#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
229
230/* Register r_bus1_in, scope iop_sw_mpu, type r */
231typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
232#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
233
234/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
235typedef struct {
236 unsigned int val : 32;
237} reg_iop_sw_mpu_rw_gio_clr_mask;
238#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
239#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
240
241/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
242typedef struct {
243 unsigned int val : 32;
244} reg_iop_sw_mpu_rw_gio_set_mask;
245#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
246#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
247
248/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
249typedef struct {
250 unsigned int val : 32;
251} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
252#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
253#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
254
255/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
256typedef struct {
257 unsigned int val : 32;
258} reg_iop_sw_mpu_rw_gio_oe_set_mask;
259#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
260#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
261
262/* Register r_gio_in, scope iop_sw_mpu, type r */
263typedef unsigned int reg_iop_sw_mpu_r_gio_in;
264#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
265
266/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
267typedef struct {
268 unsigned int intr0 : 1;
269 unsigned int intr1 : 1;
270 unsigned int intr2 : 1;
271 unsigned int intr3 : 1;
272 unsigned int intr4 : 1;
273 unsigned int intr5 : 1;
274 unsigned int intr6 : 1;
275 unsigned int intr7 : 1;
276 unsigned int intr8 : 1;
277 unsigned int intr9 : 1;
278 unsigned int intr10 : 1;
279 unsigned int intr11 : 1;
280 unsigned int intr12 : 1;
281 unsigned int intr13 : 1;
282 unsigned int intr14 : 1;
283 unsigned int intr15 : 1;
284 unsigned int intr16 : 1;
285 unsigned int intr17 : 1;
286 unsigned int intr18 : 1;
287 unsigned int intr19 : 1;
288 unsigned int intr20 : 1;
289 unsigned int intr21 : 1;
290 unsigned int intr22 : 1;
291 unsigned int intr23 : 1;
292 unsigned int intr24 : 1;
293 unsigned int intr25 : 1;
294 unsigned int intr26 : 1;
295 unsigned int intr27 : 1;
296 unsigned int intr28 : 1;
297 unsigned int intr29 : 1;
298 unsigned int intr30 : 1;
299 unsigned int intr31 : 1;
300} reg_iop_sw_mpu_rw_cpu_intr;
301#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
302#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
303
304/* Register r_cpu_intr, scope iop_sw_mpu, type r */
305typedef struct {
306 unsigned int intr0 : 1;
307 unsigned int intr1 : 1;
308 unsigned int intr2 : 1;
309 unsigned int intr3 : 1;
310 unsigned int intr4 : 1;
311 unsigned int intr5 : 1;
312 unsigned int intr6 : 1;
313 unsigned int intr7 : 1;
314 unsigned int intr8 : 1;
315 unsigned int intr9 : 1;
316 unsigned int intr10 : 1;
317 unsigned int intr11 : 1;
318 unsigned int intr12 : 1;
319 unsigned int intr13 : 1;
320 unsigned int intr14 : 1;
321 unsigned int intr15 : 1;
322 unsigned int intr16 : 1;
323 unsigned int intr17 : 1;
324 unsigned int intr18 : 1;
325 unsigned int intr19 : 1;
326 unsigned int intr20 : 1;
327 unsigned int intr21 : 1;
328 unsigned int intr22 : 1;
329 unsigned int intr23 : 1;
330 unsigned int intr24 : 1;
331 unsigned int intr25 : 1;
332 unsigned int intr26 : 1;
333 unsigned int intr27 : 1;
334 unsigned int intr28 : 1;
335 unsigned int intr29 : 1;
336 unsigned int intr30 : 1;
337 unsigned int intr31 : 1;
338} reg_iop_sw_mpu_r_cpu_intr;
339#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
340
341/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
342typedef struct {
343 unsigned int spu0_intr0 : 1;
344 unsigned int spu1_intr0 : 1;
345 unsigned int trigger_grp0 : 1;
346 unsigned int trigger_grp4 : 1;
347 unsigned int timer_grp0 : 1;
348 unsigned int fifo_out0 : 1;
349 unsigned int fifo_out0_extra : 1;
350 unsigned int dmc_out0 : 1;
351 unsigned int spu0_intr1 : 1;
352 unsigned int spu1_intr1 : 1;
353 unsigned int trigger_grp1 : 1;
354 unsigned int trigger_grp5 : 1;
355 unsigned int timer_grp1 : 1;
356 unsigned int fifo_in0 : 1;
357 unsigned int fifo_in0_extra : 1;
358 unsigned int dmc_in0 : 1;
359 unsigned int spu0_intr2 : 1;
360 unsigned int spu1_intr2 : 1;
361 unsigned int trigger_grp2 : 1;
362 unsigned int trigger_grp6 : 1;
363 unsigned int timer_grp2 : 1;
364 unsigned int fifo_out1 : 1;
365 unsigned int fifo_out1_extra : 1;
366 unsigned int dmc_out1 : 1;
367 unsigned int spu0_intr3 : 1;
368 unsigned int spu1_intr3 : 1;
369 unsigned int trigger_grp3 : 1;
370 unsigned int trigger_grp7 : 1;
371 unsigned int timer_grp3 : 1;
372 unsigned int fifo_in1 : 1;
373 unsigned int fifo_in1_extra : 1;
374 unsigned int dmc_in1 : 1;
375} reg_iop_sw_mpu_rw_intr_grp0_mask;
376#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
377#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
378
379/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
380typedef struct {
381 unsigned int spu0_intr0 : 1;
382 unsigned int spu1_intr0 : 1;
383 unsigned int dummy1 : 6;
384 unsigned int spu0_intr1 : 1;
385 unsigned int spu1_intr1 : 1;
386 unsigned int dummy2 : 6;
387 unsigned int spu0_intr2 : 1;
388 unsigned int spu1_intr2 : 1;
389 unsigned int dummy3 : 6;
390 unsigned int spu0_intr3 : 1;
391 unsigned int spu1_intr3 : 1;
392 unsigned int dummy4 : 6;
393} reg_iop_sw_mpu_rw_ack_intr_grp0;
394#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
395#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
396
397/* Register r_intr_grp0, scope iop_sw_mpu, type r */
398typedef struct {
399 unsigned int spu0_intr0 : 1;
400 unsigned int spu1_intr0 : 1;
401 unsigned int trigger_grp0 : 1;
402 unsigned int trigger_grp4 : 1;
403 unsigned int timer_grp0 : 1;
404 unsigned int fifo_out0 : 1;
405 unsigned int fifo_out0_extra : 1;
406 unsigned int dmc_out0 : 1;
407 unsigned int spu0_intr1 : 1;
408 unsigned int spu1_intr1 : 1;
409 unsigned int trigger_grp1 : 1;
410 unsigned int trigger_grp5 : 1;
411 unsigned int timer_grp1 : 1;
412 unsigned int fifo_in0 : 1;
413 unsigned int fifo_in0_extra : 1;
414 unsigned int dmc_in0 : 1;
415 unsigned int spu0_intr2 : 1;
416 unsigned int spu1_intr2 : 1;
417 unsigned int trigger_grp2 : 1;
418 unsigned int trigger_grp6 : 1;
419 unsigned int timer_grp2 : 1;
420 unsigned int fifo_out1 : 1;
421 unsigned int fifo_out1_extra : 1;
422 unsigned int dmc_out1 : 1;
423 unsigned int spu0_intr3 : 1;
424 unsigned int spu1_intr3 : 1;
425 unsigned int trigger_grp3 : 1;
426 unsigned int trigger_grp7 : 1;
427 unsigned int timer_grp3 : 1;
428 unsigned int fifo_in1 : 1;
429 unsigned int fifo_in1_extra : 1;
430 unsigned int dmc_in1 : 1;
431} reg_iop_sw_mpu_r_intr_grp0;
432#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
433
434/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
435typedef struct {
436 unsigned int spu0_intr0 : 1;
437 unsigned int spu1_intr0 : 1;
438 unsigned int trigger_grp0 : 1;
439 unsigned int trigger_grp4 : 1;
440 unsigned int timer_grp0 : 1;
441 unsigned int fifo_out0 : 1;
442 unsigned int fifo_out0_extra : 1;
443 unsigned int dmc_out0 : 1;
444 unsigned int spu0_intr1 : 1;
445 unsigned int spu1_intr1 : 1;
446 unsigned int trigger_grp1 : 1;
447 unsigned int trigger_grp5 : 1;
448 unsigned int timer_grp1 : 1;
449 unsigned int fifo_in0 : 1;
450 unsigned int fifo_in0_extra : 1;
451 unsigned int dmc_in0 : 1;
452 unsigned int spu0_intr2 : 1;
453 unsigned int spu1_intr2 : 1;
454 unsigned int trigger_grp2 : 1;
455 unsigned int trigger_grp6 : 1;
456 unsigned int timer_grp2 : 1;
457 unsigned int fifo_out1 : 1;
458 unsigned int fifo_out1_extra : 1;
459 unsigned int dmc_out1 : 1;
460 unsigned int spu0_intr3 : 1;
461 unsigned int spu1_intr3 : 1;
462 unsigned int trigger_grp3 : 1;
463 unsigned int trigger_grp7 : 1;
464 unsigned int timer_grp3 : 1;
465 unsigned int fifo_in1 : 1;
466 unsigned int fifo_in1_extra : 1;
467 unsigned int dmc_in1 : 1;
468} reg_iop_sw_mpu_r_masked_intr_grp0;
469#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
470
471/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
472typedef struct {
473 unsigned int spu0_intr4 : 1;
474 unsigned int spu1_intr4 : 1;
475 unsigned int trigger_grp0 : 1;
476 unsigned int trigger_grp5 : 1;
477 unsigned int timer_grp0 : 1;
478 unsigned int fifo_in0 : 1;
479 unsigned int fifo_in0_extra : 1;
480 unsigned int dmc_out0 : 1;
481 unsigned int spu0_intr5 : 1;
482 unsigned int spu1_intr5 : 1;
483 unsigned int trigger_grp1 : 1;
484 unsigned int trigger_grp6 : 1;
485 unsigned int timer_grp1 : 1;
486 unsigned int fifo_out1 : 1;
487 unsigned int fifo_out0_extra : 1;
488 unsigned int dmc_in0 : 1;
489 unsigned int spu0_intr6 : 1;
490 unsigned int spu1_intr6 : 1;
491 unsigned int trigger_grp2 : 1;
492 unsigned int trigger_grp7 : 1;
493 unsigned int timer_grp2 : 1;
494 unsigned int fifo_in1 : 1;
495 unsigned int fifo_in1_extra : 1;
496 unsigned int dmc_out1 : 1;
497 unsigned int spu0_intr7 : 1;
498 unsigned int spu1_intr7 : 1;
499 unsigned int trigger_grp3 : 1;
500 unsigned int trigger_grp4 : 1;
501 unsigned int timer_grp3 : 1;
502 unsigned int fifo_out0 : 1;
503 unsigned int fifo_out1_extra : 1;
504 unsigned int dmc_in1 : 1;
505} reg_iop_sw_mpu_rw_intr_grp1_mask;
506#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
507#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
508
509/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
510typedef struct {
511 unsigned int spu0_intr4 : 1;
512 unsigned int spu1_intr4 : 1;
513 unsigned int dummy1 : 6;
514 unsigned int spu0_intr5 : 1;
515 unsigned int spu1_intr5 : 1;
516 unsigned int dummy2 : 6;
517 unsigned int spu0_intr6 : 1;
518 unsigned int spu1_intr6 : 1;
519 unsigned int dummy3 : 6;
520 unsigned int spu0_intr7 : 1;
521 unsigned int spu1_intr7 : 1;
522 unsigned int dummy4 : 6;
523} reg_iop_sw_mpu_rw_ack_intr_grp1;
524#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
525#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
526
527/* Register r_intr_grp1, scope iop_sw_mpu, type r */
528typedef struct {
529 unsigned int spu0_intr4 : 1;
530 unsigned int spu1_intr4 : 1;
531 unsigned int trigger_grp0 : 1;
532 unsigned int trigger_grp5 : 1;
533 unsigned int timer_grp0 : 1;
534 unsigned int fifo_in0 : 1;
535 unsigned int fifo_in0_extra : 1;
536 unsigned int dmc_out0 : 1;
537 unsigned int spu0_intr5 : 1;
538 unsigned int spu1_intr5 : 1;
539 unsigned int trigger_grp1 : 1;
540 unsigned int trigger_grp6 : 1;
541 unsigned int timer_grp1 : 1;
542 unsigned int fifo_out1 : 1;
543 unsigned int fifo_out0_extra : 1;
544 unsigned int dmc_in0 : 1;
545 unsigned int spu0_intr6 : 1;
546 unsigned int spu1_intr6 : 1;
547 unsigned int trigger_grp2 : 1;
548 unsigned int trigger_grp7 : 1;
549 unsigned int timer_grp2 : 1;
550 unsigned int fifo_in1 : 1;
551 unsigned int fifo_in1_extra : 1;
552 unsigned int dmc_out1 : 1;
553 unsigned int spu0_intr7 : 1;
554 unsigned int spu1_intr7 : 1;
555 unsigned int trigger_grp3 : 1;
556 unsigned int trigger_grp4 : 1;
557 unsigned int timer_grp3 : 1;
558 unsigned int fifo_out0 : 1;
559 unsigned int fifo_out1_extra : 1;
560 unsigned int dmc_in1 : 1;
561} reg_iop_sw_mpu_r_intr_grp1;
562#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
563
564/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
565typedef struct {
566 unsigned int spu0_intr4 : 1;
567 unsigned int spu1_intr4 : 1;
568 unsigned int trigger_grp0 : 1;
569 unsigned int trigger_grp5 : 1;
570 unsigned int timer_grp0 : 1;
571 unsigned int fifo_in0 : 1;
572 unsigned int fifo_in0_extra : 1;
573 unsigned int dmc_out0 : 1;
574 unsigned int spu0_intr5 : 1;
575 unsigned int spu1_intr5 : 1;
576 unsigned int trigger_grp1 : 1;
577 unsigned int trigger_grp6 : 1;
578 unsigned int timer_grp1 : 1;
579 unsigned int fifo_out1 : 1;
580 unsigned int fifo_out0_extra : 1;
581 unsigned int dmc_in0 : 1;
582 unsigned int spu0_intr6 : 1;
583 unsigned int spu1_intr6 : 1;
584 unsigned int trigger_grp2 : 1;
585 unsigned int trigger_grp7 : 1;
586 unsigned int timer_grp2 : 1;
587 unsigned int fifo_in1 : 1;
588 unsigned int fifo_in1_extra : 1;
589 unsigned int dmc_out1 : 1;
590 unsigned int spu0_intr7 : 1;
591 unsigned int spu1_intr7 : 1;
592 unsigned int trigger_grp3 : 1;
593 unsigned int trigger_grp4 : 1;
594 unsigned int timer_grp3 : 1;
595 unsigned int fifo_out0 : 1;
596 unsigned int fifo_out1_extra : 1;
597 unsigned int dmc_in1 : 1;
598} reg_iop_sw_mpu_r_masked_intr_grp1;
599#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
600
601/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
602typedef struct {
603 unsigned int spu0_intr8 : 1;
604 unsigned int spu1_intr8 : 1;
605 unsigned int trigger_grp0 : 1;
606 unsigned int trigger_grp6 : 1;
607 unsigned int timer_grp0 : 1;
608 unsigned int fifo_out1 : 1;
609 unsigned int fifo_out1_extra : 1;
610 unsigned int dmc_out0 : 1;
611 unsigned int spu0_intr9 : 1;
612 unsigned int spu1_intr9 : 1;
613 unsigned int trigger_grp1 : 1;
614 unsigned int trigger_grp7 : 1;
615 unsigned int timer_grp1 : 1;
616 unsigned int fifo_in1 : 1;
617 unsigned int fifo_in1_extra : 1;
618 unsigned int dmc_in0 : 1;
619 unsigned int spu0_intr10 : 1;
620 unsigned int spu1_intr10 : 1;
621 unsigned int trigger_grp2 : 1;
622 unsigned int trigger_grp4 : 1;
623 unsigned int timer_grp2 : 1;
624 unsigned int fifo_out0 : 1;
625 unsigned int fifo_out0_extra : 1;
626 unsigned int dmc_out1 : 1;
627 unsigned int spu0_intr11 : 1;
628 unsigned int spu1_intr11 : 1;
629 unsigned int trigger_grp3 : 1;
630 unsigned int trigger_grp5 : 1;
631 unsigned int timer_grp3 : 1;
632 unsigned int fifo_in0 : 1;
633 unsigned int fifo_in0_extra : 1;
634 unsigned int dmc_in1 : 1;
635} reg_iop_sw_mpu_rw_intr_grp2_mask;
636#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
637#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
638
639/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
640typedef struct {
641 unsigned int spu0_intr8 : 1;
642 unsigned int spu1_intr8 : 1;
643 unsigned int dummy1 : 6;
644 unsigned int spu0_intr9 : 1;
645 unsigned int spu1_intr9 : 1;
646 unsigned int dummy2 : 6;
647 unsigned int spu0_intr10 : 1;
648 unsigned int spu1_intr10 : 1;
649 unsigned int dummy3 : 6;
650 unsigned int spu0_intr11 : 1;
651 unsigned int spu1_intr11 : 1;
652 unsigned int dummy4 : 6;
653} reg_iop_sw_mpu_rw_ack_intr_grp2;
654#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
655#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
656
657/* Register r_intr_grp2, scope iop_sw_mpu, type r */
658typedef struct {
659 unsigned int spu0_intr8 : 1;
660 unsigned int spu1_intr8 : 1;
661 unsigned int trigger_grp0 : 1;
662 unsigned int trigger_grp6 : 1;
663 unsigned int timer_grp0 : 1;
664 unsigned int fifo_out1 : 1;
665 unsigned int fifo_out1_extra : 1;
666 unsigned int dmc_out0 : 1;
667 unsigned int spu0_intr9 : 1;
668 unsigned int spu1_intr9 : 1;
669 unsigned int trigger_grp1 : 1;
670 unsigned int trigger_grp7 : 1;
671 unsigned int timer_grp1 : 1;
672 unsigned int fifo_in1 : 1;
673 unsigned int fifo_in1_extra : 1;
674 unsigned int dmc_in0 : 1;
675 unsigned int spu0_intr10 : 1;
676 unsigned int spu1_intr10 : 1;
677 unsigned int trigger_grp2 : 1;
678 unsigned int trigger_grp4 : 1;
679 unsigned int timer_grp2 : 1;
680 unsigned int fifo_out0 : 1;
681 unsigned int fifo_out0_extra : 1;
682 unsigned int dmc_out1 : 1;
683 unsigned int spu0_intr11 : 1;
684 unsigned int spu1_intr11 : 1;
685 unsigned int trigger_grp3 : 1;
686 unsigned int trigger_grp5 : 1;
687 unsigned int timer_grp3 : 1;
688 unsigned int fifo_in0 : 1;
689 unsigned int fifo_in0_extra : 1;
690 unsigned int dmc_in1 : 1;
691} reg_iop_sw_mpu_r_intr_grp2;
692#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
693
694/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
695typedef struct {
696 unsigned int spu0_intr8 : 1;
697 unsigned int spu1_intr8 : 1;
698 unsigned int trigger_grp0 : 1;
699 unsigned int trigger_grp6 : 1;
700 unsigned int timer_grp0 : 1;
701 unsigned int fifo_out1 : 1;
702 unsigned int fifo_out1_extra : 1;
703 unsigned int dmc_out0 : 1;
704 unsigned int spu0_intr9 : 1;
705 unsigned int spu1_intr9 : 1;
706 unsigned int trigger_grp1 : 1;
707 unsigned int trigger_grp7 : 1;
708 unsigned int timer_grp1 : 1;
709 unsigned int fifo_in1 : 1;
710 unsigned int fifo_in1_extra : 1;
711 unsigned int dmc_in0 : 1;
712 unsigned int spu0_intr10 : 1;
713 unsigned int spu1_intr10 : 1;
714 unsigned int trigger_grp2 : 1;
715 unsigned int trigger_grp4 : 1;
716 unsigned int timer_grp2 : 1;
717 unsigned int fifo_out0 : 1;
718 unsigned int fifo_out0_extra : 1;
719 unsigned int dmc_out1 : 1;
720 unsigned int spu0_intr11 : 1;
721 unsigned int spu1_intr11 : 1;
722 unsigned int trigger_grp3 : 1;
723 unsigned int trigger_grp5 : 1;
724 unsigned int timer_grp3 : 1;
725 unsigned int fifo_in0 : 1;
726 unsigned int fifo_in0_extra : 1;
727 unsigned int dmc_in1 : 1;
728} reg_iop_sw_mpu_r_masked_intr_grp2;
729#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
730
731/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
732typedef struct {
733 unsigned int spu0_intr12 : 1;
734 unsigned int spu1_intr12 : 1;
735 unsigned int trigger_grp0 : 1;
736 unsigned int trigger_grp7 : 1;
737 unsigned int timer_grp0 : 1;
738 unsigned int fifo_in1 : 1;
739 unsigned int fifo_in1_extra : 1;
740 unsigned int dmc_out0 : 1;
741 unsigned int spu0_intr13 : 1;
742 unsigned int spu1_intr13 : 1;
743 unsigned int trigger_grp1 : 1;
744 unsigned int trigger_grp4 : 1;
745 unsigned int timer_grp1 : 1;
746 unsigned int fifo_out0 : 1;
747 unsigned int fifo_out0_extra : 1;
748 unsigned int dmc_in0 : 1;
749 unsigned int spu0_intr14 : 1;
750 unsigned int spu1_intr14 : 1;
751 unsigned int trigger_grp2 : 1;
752 unsigned int trigger_grp5 : 1;
753 unsigned int timer_grp2 : 1;
754 unsigned int fifo_in0 : 1;
755 unsigned int fifo_in0_extra : 1;
756 unsigned int dmc_out1 : 1;
757 unsigned int spu0_intr15 : 1;
758 unsigned int spu1_intr15 : 1;
759 unsigned int trigger_grp3 : 1;
760 unsigned int trigger_grp6 : 1;
761 unsigned int timer_grp3 : 1;
762 unsigned int fifo_out1 : 1;
763 unsigned int fifo_out1_extra : 1;
764 unsigned int dmc_in1 : 1;
765} reg_iop_sw_mpu_rw_intr_grp3_mask;
766#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
767#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
768
769/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
770typedef struct {
771 unsigned int spu0_intr12 : 1;
772 unsigned int spu1_intr12 : 1;
773 unsigned int dummy1 : 6;
774 unsigned int spu0_intr13 : 1;
775 unsigned int spu1_intr13 : 1;
776 unsigned int dummy2 : 6;
777 unsigned int spu0_intr14 : 1;
778 unsigned int spu1_intr14 : 1;
779 unsigned int dummy3 : 6;
780 unsigned int spu0_intr15 : 1;
781 unsigned int spu1_intr15 : 1;
782 unsigned int dummy4 : 6;
783} reg_iop_sw_mpu_rw_ack_intr_grp3;
784#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
785#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
786
787/* Register r_intr_grp3, scope iop_sw_mpu, type r */
788typedef struct {
789 unsigned int spu0_intr12 : 1;
790 unsigned int spu1_intr12 : 1;
791 unsigned int trigger_grp0 : 1;
792 unsigned int trigger_grp7 : 1;
793 unsigned int timer_grp0 : 1;
794 unsigned int fifo_in1 : 1;
795 unsigned int fifo_in1_extra : 1;
796 unsigned int dmc_out0 : 1;
797 unsigned int spu0_intr13 : 1;
798 unsigned int spu1_intr13 : 1;
799 unsigned int trigger_grp1 : 1;
800 unsigned int trigger_grp4 : 1;
801 unsigned int timer_grp1 : 1;
802 unsigned int fifo_out0 : 1;
803 unsigned int fifo_out0_extra : 1;
804 unsigned int dmc_in0 : 1;
805 unsigned int spu0_intr14 : 1;
806 unsigned int spu1_intr14 : 1;
807 unsigned int trigger_grp2 : 1;
808 unsigned int trigger_grp5 : 1;
809 unsigned int timer_grp2 : 1;
810 unsigned int fifo_in0 : 1;
811 unsigned int fifo_in0_extra : 1;
812 unsigned int dmc_out1 : 1;
813 unsigned int spu0_intr15 : 1;
814 unsigned int spu1_intr15 : 1;
815 unsigned int trigger_grp3 : 1;
816 unsigned int trigger_grp6 : 1;
817 unsigned int timer_grp3 : 1;
818 unsigned int fifo_out1 : 1;
819 unsigned int fifo_out1_extra : 1;
820 unsigned int dmc_in1 : 1;
821} reg_iop_sw_mpu_r_intr_grp3;
822#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
823
824/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
825typedef struct {
826 unsigned int spu0_intr12 : 1;
827 unsigned int spu1_intr12 : 1;
828 unsigned int trigger_grp0 : 1;
829 unsigned int trigger_grp7 : 1;
830 unsigned int timer_grp0 : 1;
831 unsigned int fifo_in1 : 1;
832 unsigned int fifo_in1_extra : 1;
833 unsigned int dmc_out0 : 1;
834 unsigned int spu0_intr13 : 1;
835 unsigned int spu1_intr13 : 1;
836 unsigned int trigger_grp1 : 1;
837 unsigned int trigger_grp4 : 1;
838 unsigned int timer_grp1 : 1;
839 unsigned int fifo_out0 : 1;
840 unsigned int fifo_out0_extra : 1;
841 unsigned int dmc_in0 : 1;
842 unsigned int spu0_intr14 : 1;
843 unsigned int spu1_intr14 : 1;
844 unsigned int trigger_grp2 : 1;
845 unsigned int trigger_grp5 : 1;
846 unsigned int timer_grp2 : 1;
847 unsigned int fifo_in0 : 1;
848 unsigned int fifo_in0_extra : 1;
849 unsigned int dmc_out1 : 1;
850 unsigned int spu0_intr15 : 1;
851 unsigned int spu1_intr15 : 1;
852 unsigned int trigger_grp3 : 1;
853 unsigned int trigger_grp6 : 1;
854 unsigned int timer_grp3 : 1;
855 unsigned int fifo_out1 : 1;
856 unsigned int fifo_out1_extra : 1;
857 unsigned int dmc_in1 : 1;
858} reg_iop_sw_mpu_r_masked_intr_grp3;
859#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
860
861
862/* Constants */
863enum {
864 regk_iop_sw_mpu_copy = 0x00000000,
865 regk_iop_sw_mpu_cpu = 0x00000000,
866 regk_iop_sw_mpu_mpu = 0x00000001,
867 regk_iop_sw_mpu_no = 0x00000000,
868 regk_iop_sw_mpu_nop = 0x00000000,
869 regk_iop_sw_mpu_rd = 0x00000002,
870 regk_iop_sw_mpu_reg_copy = 0x00000001,
871 regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
872 regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
873 regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
874 regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
875 regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
876 regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
877 regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
878 regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
879 regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
880 regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
881 regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
882 regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
883 regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
884 regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
885 regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
886 regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
887 regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
888 regk_iop_sw_mpu_set = 0x00000001,
889 regk_iop_sw_mpu_spu0 = 0x00000002,
890 regk_iop_sw_mpu_spu1 = 0x00000003,
891 regk_iop_sw_mpu_wr = 0x00000003,
892 regk_iop_sw_mpu_yes = 0x00000001
893};
894#endif /* __iop_sw_mpu_defs_h */
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