[mirror_ubuntu-bionic-kernel.git] / arch / cris / include / arch-v32 / arch / hwregs / iop / iop_timer_grp_defs.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __iop_timer_grp_defs_h
#define __iop_timer_grp_defs_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
 *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
 *     last modfied: Mon Apr 11 16:08:46 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
 *      id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope iop_timer_grp */

/* Register rw_cfg, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int clk_src     : 1;
  unsigned int trig        : 2;
  unsigned int clk_gen_div : 8;
  unsigned int clk_div     : 8;
  unsigned int dummy1      : 13;
} reg_iop_timer_grp_rw_cfg;
#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0

/* Register rw_half_period, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int quota_lo     : 15;
  unsigned int quota_hi     : 15;
  unsigned int quota_hi_sel : 1;
  unsigned int dummy1       : 1;
} reg_iop_timer_grp_rw_half_period;
#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4

/* Register rw_half_period_len, scope iop_timer_grp, type rw */
typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8

#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int clk_src         : 3;
  unsigned int strb            : 2;
  unsigned int run_mode        : 2;
  unsigned int out_mode        : 1;
  unsigned int active_on_tmr   : 2;
  unsigned int inv             : 1;
  unsigned int en_by_tmr       : 2;
  unsigned int dis_by_tmr      : 2;
  unsigned int en_only_by_reg  : 1;
  unsigned int dis_only_by_reg : 1;
  unsigned int rst_at_en_strb  : 1;
  unsigned int dummy1          : 14;
} reg_iop_timer_grp_rw_tmr_cfg;
#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12

#define STRIDE_iop_timer_grp_rw_tmr_len 4
/* Register rw_tmr_len, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_timer_grp_rw_tmr_len;
#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44

/* Register rw_cmd, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int rst  : 4;
  unsigned int en   : 4;
  unsigned int dis  : 4;
  unsigned int strb : 4;
  unsigned int dummy1 : 16;
} reg_iop_timer_grp_rw_cmd;
#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60

/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64

#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_timer_grp_rs_tmr_cnt;
#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68

#define STRIDE_iop_timer_grp_r_tmr_cnt 8
/* Register r_tmr_cnt, scope iop_timer_grp, type r */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_timer_grp_r_tmr_cnt;
#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72

/* Register rw_intr_mask, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int tmr0 : 1;
  unsigned int tmr1 : 1;
  unsigned int tmr2 : 1;
  unsigned int tmr3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_timer_grp_rw_intr_mask;
#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100

/* Register rw_ack_intr, scope iop_timer_grp, type rw */
typedef struct {
  unsigned int tmr0 : 1;
  unsigned int tmr1 : 1;
  unsigned int tmr2 : 1;
  unsigned int tmr3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_timer_grp_rw_ack_intr;
#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104

/* Register r_intr, scope iop_timer_grp, type r */
typedef struct {
  unsigned int tmr0 : 1;
  unsigned int tmr1 : 1;
  unsigned int tmr2 : 1;
  unsigned int tmr3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_timer_grp_r_intr;
#define REG_RD_ADDR_iop_timer_grp_r_intr 108

/* Register r_masked_intr, scope iop_timer_grp, type r */
typedef struct {
  unsigned int tmr0 : 1;
  unsigned int tmr1 : 1;
  unsigned int tmr2 : 1;
  unsigned int tmr3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_timer_grp_r_masked_intr;
#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112


/* Constants */
enum {
  regk_iop_timer_grp_clk200                = 0x00000000,
  regk_iop_timer_grp_clk_gen               = 0x00000002,
  regk_iop_timer_grp_complete              = 0x00000002,
  regk_iop_timer_grp_div_clk200            = 0x00000001,
  regk_iop_timer_grp_div_clk_gen           = 0x00000003,
  regk_iop_timer_grp_ext                   = 0x00000001,
  regk_iop_timer_grp_hi                    = 0x00000000,
  regk_iop_timer_grp_long_period           = 0x00000001,
  regk_iop_timer_grp_neg                   = 0x00000002,
  regk_iop_timer_grp_no                    = 0x00000000,
  regk_iop_timer_grp_once                  = 0x00000003,
  regk_iop_timer_grp_pause                 = 0x00000001,
  regk_iop_timer_grp_pos                   = 0x00000001,
  regk_iop_timer_grp_pos_neg               = 0x00000003,
  regk_iop_timer_grp_pulse                 = 0x00000000,
  regk_iop_timer_grp_r_tmr_cnt_size        = 0x00000004,
  regk_iop_timer_grp_rs_tmr_cnt_size       = 0x00000004,
  regk_iop_timer_grp_rw_cfg_default        = 0x00000002,
  regk_iop_timer_grp_rw_intr_mask_default  = 0x00000000,
  regk_iop_timer_grp_rw_tmr_cfg_default0   = 0x00018000,
  regk_iop_timer_grp_rw_tmr_cfg_default1   = 0x0001a900,
  regk_iop_timer_grp_rw_tmr_cfg_default2   = 0x0001d200,
  regk_iop_timer_grp_rw_tmr_cfg_default3   = 0x0001fb00,
  regk_iop_timer_grp_rw_tmr_cfg_size       = 0x00000004,
  regk_iop_timer_grp_rw_tmr_len_default    = 0x00000000,
  regk_iop_timer_grp_rw_tmr_len_size       = 0x00000004,
  regk_iop_timer_grp_short_period          = 0x00000000,
  regk_iop_timer_grp_stop                  = 0x00000000,
  regk_iop_timer_grp_tmr                   = 0x00000004,
  regk_iop_timer_grp_toggle                = 0x00000001,
  regk_iop_timer_grp_yes                   = 0x00000001
};
#endif /* __iop_timer_grp_defs_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
51533b61 MS	2	#ifndef __iop_timer_grp_defs_h
	3	#define __iop_timer_grp_defs_h
	4
	5	/*
	6	* This file is autogenerated from
	7	* file: ../../inst/io_proc/rtl/iop_timer_grp.r
	8	* id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
	9	* last modfied: Mon Apr 11 16:08:46 2005
	10	*
	11	* by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
	12	* id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
	13	* Any changes here will be lost.
	14	*
	15	* -- buffer-read-only: t --
	16	*/
	17	/* Main access macros */
	18	#ifndef REG_RD
	19	#define REG_RD( scope, inst, reg ) \
	20	REG_READ( reg_##scope##_##reg, \
	21	(inst) + REG_RD_ADDR_##scope##_##reg )
	22	#endif
	23
	24	#ifndef REG_WR
	25	#define REG_WR( scope, inst, reg, val ) \
	26	REG_WRITE( reg_##scope##_##reg, \
	27	(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	28	#endif
	29
	30	#ifndef REG_RD_VECT
	31	#define REG_RD_VECT( scope, inst, reg, index ) \
	32	REG_READ( reg_##scope##_##reg, \
	33	(inst) + REG_RD_ADDR_##scope##_##reg + \
	34	(index) * STRIDE_##scope##_##reg )
	35	#endif
	36
	37	#ifndef REG_WR_VECT
	38	#define REG_WR_VECT( scope, inst, reg, index, val ) \
	39	REG_WRITE( reg_##scope##_##reg, \
	40	(inst) + REG_WR_ADDR_##scope##_##reg + \
	41	(index) * STRIDE_##scope##_##reg, (val) )
	42	#endif
	43
	44	#ifndef REG_RD_INT
	45	#define REG_RD_INT( scope, inst, reg ) \
	46	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
	47	#endif
	48
	49	#ifndef REG_WR_INT
	50	#define REG_WR_INT( scope, inst, reg, val ) \
	51	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	52	#endif
	53
	54	#ifndef REG_RD_INT_VECT
	55	#define REG_RD_INT_VECT( scope, inst, reg, index ) \
	56	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	57	(index) * STRIDE_##scope##_##reg )
	58	#endif
	59
	60	#ifndef REG_WR_INT_VECT
	61	#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
	62	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	63	(index) * STRIDE_##scope##_##reg, (val) )
	64	#endif
	65
66	#ifndef REG_TYPE_CONV
67	#define REG_TYPE_CONV( type, orgtype, val ) \
68	( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69	#endif
70
71	#ifndef reg_page_size
72	#define reg_page_size 8192
73	#endif
74
75	#ifndef REG_ADDR
76	#define REG_ADDR( scope, inst, reg ) \
77	( (inst) + REG_RD_ADDR_##scope##_##reg )
78	#endif
79
80	#ifndef REG_ADDR_VECT
81	#define REG_ADDR_VECT( scope, inst, reg, index ) \
82	( (inst) + REG_RD_ADDR_##scope##_##reg + \
83	(index) * STRIDE_##scope##_##reg )
84	#endif
85
86	/* C-code for register scope iop_timer_grp */
87
88	/* Register rw_cfg, scope iop_timer_grp, type rw */
89	typedef struct {
90	unsigned int clk_src : 1;
91	unsigned int trig : 2;
92	unsigned int clk_gen_div : 8;
93	unsigned int clk_div : 8;
94	unsigned int dummy1 : 13;
95	} reg_iop_timer_grp_rw_cfg;
96	#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
97	#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
98
99	/* Register rw_half_period, scope iop_timer_grp, type rw */
100	typedef struct {
101	unsigned int quota_lo : 15;
102	unsigned int quota_hi : 15;
103	unsigned int quota_hi_sel : 1;
104	unsigned int dummy1 : 1;
105	} reg_iop_timer_grp_rw_half_period;
106	#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
107	#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
108
109	/* Register rw_half_period_len, scope iop_timer_grp, type rw */
110	typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
111	#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
112	#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
113
114	#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
115	/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
116	typedef struct {
117	unsigned int clk_src : 3;
118	unsigned int strb : 2;
119	unsigned int run_mode : 2;
120	unsigned int out_mode : 1;
121	unsigned int active_on_tmr : 2;
122	unsigned int inv : 1;
123	unsigned int en_by_tmr : 2;
124	unsigned int dis_by_tmr : 2;
125	unsigned int en_only_by_reg : 1;
126	unsigned int dis_only_by_reg : 1;
127	unsigned int rst_at_en_strb : 1;
128	unsigned int dummy1 : 14;
129	} reg_iop_timer_grp_rw_tmr_cfg;
130	#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
131	#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
132
133	#define STRIDE_iop_timer_grp_rw_tmr_len 4
134	/* Register rw_tmr_len, scope iop_timer_grp, type rw */
135	typedef struct {
136	unsigned int val : 16;
137	unsigned int dummy1 : 16;
138	} reg_iop_timer_grp_rw_tmr_len;
139	#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
140	#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
141
142	/* Register rw_cmd, scope iop_timer_grp, type rw */
143	typedef struct {
144	unsigned int rst : 4;
145	unsigned int en : 4;
146	unsigned int dis : 4;
147	unsigned int strb : 4;
148	unsigned int dummy1 : 16;
149	} reg_iop_timer_grp_rw_cmd;
150	#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
151	#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
152
153	/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
154	typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
155	#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
156
157	#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
158	/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
159	typedef struct {
160	unsigned int val : 16;
161	unsigned int dummy1 : 16;
162	} reg_iop_timer_grp_rs_tmr_cnt;
163	#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
164
165	#define STRIDE_iop_timer_grp_r_tmr_cnt 8
166	/* Register r_tmr_cnt, scope iop_timer_grp, type r */
167	typedef struct {
168	unsigned int val : 16;
169	unsigned int dummy1 : 16;
170	} reg_iop_timer_grp_r_tmr_cnt;
171	#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
172
173	/* Register rw_intr_mask, scope iop_timer_grp, type rw */
174	typedef struct {
175	unsigned int tmr0 : 1;
176	unsigned int tmr1 : 1;
177	unsigned int tmr2 : 1;
178	unsigned int tmr3 : 1;
179	unsigned int dummy1 : 28;
180	} reg_iop_timer_grp_rw_intr_mask;
181	#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
182	#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
183
184	/* Register rw_ack_intr, scope iop_timer_grp, type rw */
185	typedef struct {
186	unsigned int tmr0 : 1;
187	unsigned int tmr1 : 1;
188	unsigned int tmr2 : 1;
189	unsigned int tmr3 : 1;
190	unsigned int dummy1 : 28;
191	} reg_iop_timer_grp_rw_ack_intr;
192	#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
193	#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
194
195	/* Register r_intr, scope iop_timer_grp, type r */
196	typedef struct {
197	unsigned int tmr0 : 1;
198	unsigned int tmr1 : 1;
199	unsigned int tmr2 : 1;
200	unsigned int tmr3 : 1;
201	unsigned int dummy1 : 28;
202	} reg_iop_timer_grp_r_intr;
203	#define REG_RD_ADDR_iop_timer_grp_r_intr 108
204
205	/* Register r_masked_intr, scope iop_timer_grp, type r */
206	typedef struct {
207	unsigned int tmr0 : 1;
208	unsigned int tmr1 : 1;
209	unsigned int tmr2 : 1;
210	unsigned int tmr3 : 1;
211	unsigned int dummy1 : 28;
212	} reg_iop_timer_grp_r_masked_intr;
213	#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
214
215
216	/* Constants */
217	enum {
218	regk_iop_timer_grp_clk200 = 0x00000000,
219	regk_iop_timer_grp_clk_gen = 0x00000002,
220	regk_iop_timer_grp_complete = 0x00000002,
221	regk_iop_timer_grp_div_clk200 = 0x00000001,
222	regk_iop_timer_grp_div_clk_gen = 0x00000003,
223	regk_iop_timer_grp_ext = 0x00000001,
224	regk_iop_timer_grp_hi = 0x00000000,
225	regk_iop_timer_grp_long_period = 0x00000001,
226	regk_iop_timer_grp_neg = 0x00000002,
227	regk_iop_timer_grp_no = 0x00000000,
228	regk_iop_timer_grp_once = 0x00000003,
229	regk_iop_timer_grp_pause = 0x00000001,
230	regk_iop_timer_grp_pos = 0x00000001,
231	regk_iop_timer_grp_pos_neg = 0x00000003,
232	regk_iop_timer_grp_pulse = 0x00000000,
233	regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004,
234	regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004,
235	regk_iop_timer_grp_rw_cfg_default = 0x00000002,
236	regk_iop_timer_grp_rw_intr_mask_default = 0x00000000,
237	regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000,
238	regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900,
239	regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200,
240	regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00,
241	regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004,
242	regk_iop_timer_grp_rw_tmr_len_default = 0x00000000,
243	regk_iop_timer_grp_rw_tmr_len_size = 0x00000004,
244	regk_iop_timer_grp_short_period = 0x00000000,
245	regk_iop_timer_grp_stop = 0x00000000,
246	regk_iop_timer_grp_tmr = 0x00000004,
247	regk_iop_timer_grp_toggle = 0x00000001,
248	regk_iop_timer_grp_yes = 0x00000001
249	};
250	#endif /* __iop_timer_grp_defs_h */