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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
58d08319 JN |
2 | #ifndef __iop_sw_cfg_defs_h |
3 | #define __iop_sw_cfg_defs_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: iop_sw_cfg.r | |
8 | * | |
9 | * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r | |
10 | * Any changes here will be lost. | |
11 | * | |
12 | * -*- buffer-read-only: t -*- | |
13 | */ | |
14 | /* Main access macros */ | |
15 | #ifndef REG_RD | |
16 | #define REG_RD( scope, inst, reg ) \ | |
17 | REG_READ( reg_##scope##_##reg, \ | |
18 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
19 | #endif | |
20 | ||
21 | #ifndef REG_WR | |
22 | #define REG_WR( scope, inst, reg, val ) \ | |
23 | REG_WRITE( reg_##scope##_##reg, \ | |
24 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
25 | #endif | |
26 | ||
27 | #ifndef REG_RD_VECT | |
28 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
29 | REG_READ( reg_##scope##_##reg, \ | |
30 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
31 | (index) * STRIDE_##scope##_##reg ) | |
32 | #endif | |
33 | ||
34 | #ifndef REG_WR_VECT | |
35 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
36 | REG_WRITE( reg_##scope##_##reg, \ | |
37 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
38 | (index) * STRIDE_##scope##_##reg, (val) ) | |
39 | #endif | |
40 | ||
41 | #ifndef REG_RD_INT | |
42 | #define REG_RD_INT( scope, inst, reg ) \ | |
43 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
44 | #endif | |
45 | ||
46 | #ifndef REG_WR_INT | |
47 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
48 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
49 | #endif | |
50 | ||
51 | #ifndef REG_RD_INT_VECT | |
52 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
53 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
54 | (index) * STRIDE_##scope##_##reg ) | |
55 | #endif | |
56 | ||
57 | #ifndef REG_WR_INT_VECT | |
58 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
59 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
60 | (index) * STRIDE_##scope##_##reg, (val) ) | |
61 | #endif | |
62 | ||
63 | #ifndef REG_TYPE_CONV | |
64 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
65 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
66 | #endif | |
67 | ||
68 | #ifndef reg_page_size | |
69 | #define reg_page_size 8192 | |
70 | #endif | |
71 | ||
72 | #ifndef REG_ADDR | |
73 | #define REG_ADDR( scope, inst, reg ) \ | |
74 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
75 | #endif | |
76 | ||
77 | #ifndef REG_ADDR_VECT | |
78 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
79 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
80 | (index) * STRIDE_##scope##_##reg ) | |
81 | #endif | |
82 | ||
83 | /* C-code for register scope iop_sw_cfg */ | |
84 | ||
85 | /* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ | |
86 | typedef struct { | |
87 | unsigned int cfg : 2; | |
88 | unsigned int dummy1 : 30; | |
89 | } reg_iop_sw_cfg_rw_crc_par_owner; | |
90 | #define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | |
91 | #define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 | |
92 | ||
93 | /* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ | |
94 | typedef struct { | |
95 | unsigned int cfg : 2; | |
96 | unsigned int dummy1 : 30; | |
97 | } reg_iop_sw_cfg_rw_dmc_in_owner; | |
98 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | |
99 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 | |
100 | ||
101 | /* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ | |
102 | typedef struct { | |
103 | unsigned int cfg : 2; | |
104 | unsigned int dummy1 : 30; | |
105 | } reg_iop_sw_cfg_rw_dmc_out_owner; | |
106 | #define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | |
107 | #define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 | |
108 | ||
109 | /* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ | |
110 | typedef struct { | |
111 | unsigned int cfg : 2; | |
112 | unsigned int dummy1 : 30; | |
113 | } reg_iop_sw_cfg_rw_fifo_in_owner; | |
114 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | |
115 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 | |
116 | ||
117 | /* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ | |
118 | typedef struct { | |
119 | unsigned int cfg : 2; | |
120 | unsigned int dummy1 : 30; | |
121 | } reg_iop_sw_cfg_rw_fifo_in_extra_owner; | |
122 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | |
123 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 | |
124 | ||
125 | /* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ | |
126 | typedef struct { | |
127 | unsigned int cfg : 2; | |
128 | unsigned int dummy1 : 30; | |
129 | } reg_iop_sw_cfg_rw_fifo_out_owner; | |
130 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | |
131 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 | |
132 | ||
133 | /* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ | |
134 | typedef struct { | |
135 | unsigned int cfg : 2; | |
136 | unsigned int dummy1 : 30; | |
137 | } reg_iop_sw_cfg_rw_fifo_out_extra_owner; | |
138 | #define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | |
139 | #define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 | |
140 | ||
141 | /* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ | |
142 | typedef struct { | |
143 | unsigned int cfg : 2; | |
144 | unsigned int dummy1 : 30; | |
145 | } reg_iop_sw_cfg_rw_sap_in_owner; | |
146 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | |
147 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 | |
148 | ||
149 | /* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ | |
150 | typedef struct { | |
151 | unsigned int cfg : 2; | |
152 | unsigned int dummy1 : 30; | |
153 | } reg_iop_sw_cfg_rw_sap_out_owner; | |
154 | #define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | |
155 | #define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 | |
156 | ||
157 | /* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ | |
158 | typedef struct { | |
159 | unsigned int cfg : 2; | |
160 | unsigned int dummy1 : 30; | |
161 | } reg_iop_sw_cfg_rw_scrc_in_owner; | |
162 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | |
163 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 | |
164 | ||
165 | /* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ | |
166 | typedef struct { | |
167 | unsigned int cfg : 2; | |
168 | unsigned int dummy1 : 30; | |
169 | } reg_iop_sw_cfg_rw_scrc_out_owner; | |
170 | #define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | |
171 | #define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 | |
172 | ||
173 | /* Register rw_spu_owner, scope iop_sw_cfg, type rw */ | |
174 | typedef struct { | |
175 | unsigned int cfg : 1; | |
176 | unsigned int dummy1 : 31; | |
177 | } reg_iop_sw_cfg_rw_spu_owner; | |
178 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 | |
179 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 | |
180 | ||
181 | /* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ | |
182 | typedef struct { | |
183 | unsigned int cfg : 2; | |
184 | unsigned int dummy1 : 30; | |
185 | } reg_iop_sw_cfg_rw_timer_grp0_owner; | |
186 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | |
187 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 | |
188 | ||
189 | /* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ | |
190 | typedef struct { | |
191 | unsigned int cfg : 2; | |
192 | unsigned int dummy1 : 30; | |
193 | } reg_iop_sw_cfg_rw_timer_grp1_owner; | |
194 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | |
195 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 | |
196 | ||
197 | /* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ | |
198 | typedef struct { | |
199 | unsigned int cfg : 2; | |
200 | unsigned int dummy1 : 30; | |
201 | } reg_iop_sw_cfg_rw_trigger_grp0_owner; | |
202 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | |
203 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 | |
204 | ||
205 | /* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ | |
206 | typedef struct { | |
207 | unsigned int cfg : 2; | |
208 | unsigned int dummy1 : 30; | |
209 | } reg_iop_sw_cfg_rw_trigger_grp1_owner; | |
210 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | |
211 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 | |
212 | ||
213 | /* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ | |
214 | typedef struct { | |
215 | unsigned int cfg : 2; | |
216 | unsigned int dummy1 : 30; | |
217 | } reg_iop_sw_cfg_rw_trigger_grp2_owner; | |
218 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | |
219 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 | |
220 | ||
221 | /* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ | |
222 | typedef struct { | |
223 | unsigned int cfg : 2; | |
224 | unsigned int dummy1 : 30; | |
225 | } reg_iop_sw_cfg_rw_trigger_grp3_owner; | |
226 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | |
227 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 | |
228 | ||
229 | /* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ | |
230 | typedef struct { | |
231 | unsigned int cfg : 2; | |
232 | unsigned int dummy1 : 30; | |
233 | } reg_iop_sw_cfg_rw_trigger_grp4_owner; | |
234 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | |
235 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 | |
236 | ||
237 | /* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ | |
238 | typedef struct { | |
239 | unsigned int cfg : 2; | |
240 | unsigned int dummy1 : 30; | |
241 | } reg_iop_sw_cfg_rw_trigger_grp5_owner; | |
242 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | |
243 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 | |
244 | ||
245 | /* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ | |
246 | typedef struct { | |
247 | unsigned int cfg : 2; | |
248 | unsigned int dummy1 : 30; | |
249 | } reg_iop_sw_cfg_rw_trigger_grp6_owner; | |
250 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | |
251 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 | |
252 | ||
253 | /* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ | |
254 | typedef struct { | |
255 | unsigned int cfg : 2; | |
256 | unsigned int dummy1 : 30; | |
257 | } reg_iop_sw_cfg_rw_trigger_grp7_owner; | |
258 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | |
259 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 | |
260 | ||
261 | /* Register rw_bus_mask, scope iop_sw_cfg, type rw */ | |
262 | typedef struct { | |
263 | unsigned int byte0 : 8; | |
264 | unsigned int byte1 : 8; | |
265 | unsigned int byte2 : 8; | |
266 | unsigned int byte3 : 8; | |
267 | } reg_iop_sw_cfg_rw_bus_mask; | |
268 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 | |
269 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 | |
270 | ||
271 | /* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ | |
272 | typedef struct { | |
273 | unsigned int byte0 : 1; | |
274 | unsigned int byte1 : 1; | |
275 | unsigned int byte2 : 1; | |
276 | unsigned int byte3 : 1; | |
277 | unsigned int dummy1 : 28; | |
278 | } reg_iop_sw_cfg_rw_bus_oe_mask; | |
279 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | |
280 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 | |
281 | ||
282 | /* Register rw_gio_mask, scope iop_sw_cfg, type rw */ | |
283 | typedef struct { | |
284 | unsigned int val : 32; | |
285 | } reg_iop_sw_cfg_rw_gio_mask; | |
286 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 | |
287 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 | |
288 | ||
289 | /* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ | |
290 | typedef struct { | |
291 | unsigned int val : 32; | |
292 | } reg_iop_sw_cfg_rw_gio_oe_mask; | |
293 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | |
294 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 | |
295 | ||
296 | /* Register rw_pinmapping, scope iop_sw_cfg, type rw */ | |
297 | typedef struct { | |
298 | unsigned int bus_byte0 : 2; | |
299 | unsigned int bus_byte1 : 2; | |
300 | unsigned int bus_byte2 : 2; | |
301 | unsigned int bus_byte3 : 2; | |
302 | unsigned int gio3_0 : 2; | |
303 | unsigned int gio7_4 : 2; | |
304 | unsigned int gio11_8 : 2; | |
305 | unsigned int gio15_12 : 2; | |
306 | unsigned int gio19_16 : 2; | |
307 | unsigned int gio23_20 : 2; | |
308 | unsigned int gio27_24 : 2; | |
309 | unsigned int gio31_28 : 2; | |
310 | unsigned int dummy1 : 8; | |
311 | } reg_iop_sw_cfg_rw_pinmapping; | |
312 | #define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 | |
313 | #define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 | |
314 | ||
315 | /* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ | |
316 | typedef struct { | |
317 | unsigned int bus_lo : 2; | |
318 | unsigned int bus_hi : 2; | |
319 | unsigned int bus_lo_oe : 2; | |
320 | unsigned int bus_hi_oe : 2; | |
321 | unsigned int dummy1 : 24; | |
322 | } reg_iop_sw_cfg_rw_bus_out_cfg; | |
323 | #define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | |
324 | #define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 | |
325 | ||
326 | /* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ | |
327 | typedef struct { | |
328 | unsigned int gio0 : 3; | |
329 | unsigned int gio0_oe : 1; | |
330 | unsigned int gio1 : 3; | |
331 | unsigned int gio1_oe : 1; | |
332 | unsigned int gio2 : 3; | |
333 | unsigned int gio2_oe : 1; | |
334 | unsigned int gio3 : 3; | |
335 | unsigned int gio3_oe : 1; | |
336 | unsigned int dummy1 : 16; | |
337 | } reg_iop_sw_cfg_rw_gio_out_grp0_cfg; | |
338 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | |
339 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 | |
340 | ||
341 | /* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ | |
342 | typedef struct { | |
343 | unsigned int gio4 : 3; | |
344 | unsigned int gio4_oe : 1; | |
345 | unsigned int gio5 : 3; | |
346 | unsigned int gio5_oe : 1; | |
347 | unsigned int gio6 : 3; | |
348 | unsigned int gio6_oe : 1; | |
349 | unsigned int gio7 : 3; | |
350 | unsigned int gio7_oe : 1; | |
351 | unsigned int dummy1 : 16; | |
352 | } reg_iop_sw_cfg_rw_gio_out_grp1_cfg; | |
353 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | |
354 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 | |
355 | ||
356 | /* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ | |
357 | typedef struct { | |
358 | unsigned int gio8 : 3; | |
359 | unsigned int gio8_oe : 1; | |
360 | unsigned int gio9 : 3; | |
361 | unsigned int gio9_oe : 1; | |
362 | unsigned int gio10 : 3; | |
363 | unsigned int gio10_oe : 1; | |
364 | unsigned int gio11 : 3; | |
365 | unsigned int gio11_oe : 1; | |
366 | unsigned int dummy1 : 16; | |
367 | } reg_iop_sw_cfg_rw_gio_out_grp2_cfg; | |
368 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | |
369 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 | |
370 | ||
371 | /* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ | |
372 | typedef struct { | |
373 | unsigned int gio12 : 3; | |
374 | unsigned int gio12_oe : 1; | |
375 | unsigned int gio13 : 3; | |
376 | unsigned int gio13_oe : 1; | |
377 | unsigned int gio14 : 3; | |
378 | unsigned int gio14_oe : 1; | |
379 | unsigned int gio15 : 3; | |
380 | unsigned int gio15_oe : 1; | |
381 | unsigned int dummy1 : 16; | |
382 | } reg_iop_sw_cfg_rw_gio_out_grp3_cfg; | |
383 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | |
384 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 | |
385 | ||
386 | /* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ | |
387 | typedef struct { | |
388 | unsigned int gio16 : 3; | |
389 | unsigned int gio16_oe : 1; | |
390 | unsigned int gio17 : 3; | |
391 | unsigned int gio17_oe : 1; | |
392 | unsigned int gio18 : 3; | |
393 | unsigned int gio18_oe : 1; | |
394 | unsigned int gio19 : 3; | |
395 | unsigned int gio19_oe : 1; | |
396 | unsigned int dummy1 : 16; | |
397 | } reg_iop_sw_cfg_rw_gio_out_grp4_cfg; | |
398 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | |
399 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 | |
400 | ||
401 | /* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ | |
402 | typedef struct { | |
403 | unsigned int gio20 : 3; | |
404 | unsigned int gio20_oe : 1; | |
405 | unsigned int gio21 : 3; | |
406 | unsigned int gio21_oe : 1; | |
407 | unsigned int gio22 : 3; | |
408 | unsigned int gio22_oe : 1; | |
409 | unsigned int gio23 : 3; | |
410 | unsigned int gio23_oe : 1; | |
411 | unsigned int dummy1 : 16; | |
412 | } reg_iop_sw_cfg_rw_gio_out_grp5_cfg; | |
413 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | |
414 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 | |
415 | ||
416 | /* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ | |
417 | typedef struct { | |
418 | unsigned int gio24 : 3; | |
419 | unsigned int gio24_oe : 1; | |
420 | unsigned int gio25 : 3; | |
421 | unsigned int gio25_oe : 1; | |
422 | unsigned int gio26 : 3; | |
423 | unsigned int gio26_oe : 1; | |
424 | unsigned int gio27 : 3; | |
425 | unsigned int gio27_oe : 1; | |
426 | unsigned int dummy1 : 16; | |
427 | } reg_iop_sw_cfg_rw_gio_out_grp6_cfg; | |
428 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | |
429 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 | |
430 | ||
431 | /* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ | |
432 | typedef struct { | |
433 | unsigned int gio28 : 3; | |
434 | unsigned int gio28_oe : 1; | |
435 | unsigned int gio29 : 3; | |
436 | unsigned int gio29_oe : 1; | |
437 | unsigned int gio30 : 3; | |
438 | unsigned int gio30_oe : 1; | |
439 | unsigned int gio31 : 3; | |
440 | unsigned int gio31_oe : 1; | |
441 | unsigned int dummy1 : 16; | |
442 | } reg_iop_sw_cfg_rw_gio_out_grp7_cfg; | |
443 | #define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | |
444 | #define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 | |
445 | ||
446 | /* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ | |
447 | typedef struct { | |
448 | unsigned int bus0_in : 1; | |
449 | unsigned int bus1_in : 1; | |
450 | unsigned int dummy1 : 30; | |
451 | } reg_iop_sw_cfg_rw_spu_cfg; | |
452 | #define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 | |
453 | #define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 | |
454 | ||
455 | /* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ | |
456 | typedef struct { | |
457 | unsigned int ext_clk : 3; | |
458 | unsigned int tmr0_en : 2; | |
459 | unsigned int tmr1_en : 2; | |
460 | unsigned int tmr2_en : 2; | |
461 | unsigned int tmr3_en : 2; | |
462 | unsigned int tmr0_dis : 2; | |
463 | unsigned int tmr1_dis : 2; | |
464 | unsigned int tmr2_dis : 2; | |
465 | unsigned int tmr3_dis : 2; | |
466 | unsigned int dummy1 : 13; | |
467 | } reg_iop_sw_cfg_rw_timer_grp0_cfg; | |
468 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | |
469 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 | |
470 | ||
471 | /* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ | |
472 | typedef struct { | |
473 | unsigned int ext_clk : 3; | |
474 | unsigned int tmr0_en : 2; | |
475 | unsigned int tmr1_en : 2; | |
476 | unsigned int tmr2_en : 2; | |
477 | unsigned int tmr3_en : 2; | |
478 | unsigned int tmr0_dis : 2; | |
479 | unsigned int tmr1_dis : 2; | |
480 | unsigned int tmr2_dis : 2; | |
481 | unsigned int tmr3_dis : 2; | |
482 | unsigned int dummy1 : 13; | |
483 | } reg_iop_sw_cfg_rw_timer_grp1_cfg; | |
484 | #define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | |
485 | #define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 | |
486 | ||
487 | /* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ | |
488 | typedef struct { | |
489 | unsigned int grp0_dis : 1; | |
490 | unsigned int grp0_en : 1; | |
491 | unsigned int grp1_dis : 1; | |
492 | unsigned int grp1_en : 1; | |
493 | unsigned int grp2_dis : 1; | |
494 | unsigned int grp2_en : 1; | |
495 | unsigned int grp3_dis : 1; | |
496 | unsigned int grp3_en : 1; | |
497 | unsigned int grp4_dis : 1; | |
498 | unsigned int grp4_en : 1; | |
499 | unsigned int grp5_dis : 1; | |
500 | unsigned int grp5_en : 1; | |
501 | unsigned int grp6_dis : 1; | |
502 | unsigned int grp6_en : 1; | |
503 | unsigned int grp7_dis : 1; | |
504 | unsigned int grp7_en : 1; | |
505 | unsigned int dummy1 : 16; | |
506 | } reg_iop_sw_cfg_rw_trigger_grps_cfg; | |
507 | #define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | |
508 | #define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 | |
509 | ||
510 | /* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ | |
511 | typedef struct { | |
512 | unsigned int out_strb : 4; | |
513 | unsigned int in_src : 2; | |
514 | unsigned int in_size : 3; | |
515 | unsigned int in_last : 2; | |
516 | unsigned int in_strb : 4; | |
517 | unsigned int dummy1 : 17; | |
518 | } reg_iop_sw_cfg_rw_pdp_cfg; | |
519 | #define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | |
520 | #define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 | |
521 | ||
522 | /* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ | |
523 | typedef struct { | |
524 | unsigned int sdp_out_strb : 3; | |
525 | unsigned int sdp_in_data : 3; | |
526 | unsigned int sdp_in_last : 2; | |
527 | unsigned int sdp_in_strb : 3; | |
528 | unsigned int dummy1 : 21; | |
529 | } reg_iop_sw_cfg_rw_sdp_cfg; | |
530 | #define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | |
531 | #define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 | |
532 | ||
533 | ||
534 | /* Constants */ | |
535 | enum { | |
536 | regk_iop_sw_cfg_a = 0x00000001, | |
537 | regk_iop_sw_cfg_b = 0x00000002, | |
538 | regk_iop_sw_cfg_bus = 0x00000000, | |
539 | regk_iop_sw_cfg_bus_rot16 = 0x00000002, | |
540 | regk_iop_sw_cfg_bus_rot24 = 0x00000003, | |
541 | regk_iop_sw_cfg_bus_rot8 = 0x00000001, | |
542 | regk_iop_sw_cfg_clk12 = 0x00000000, | |
543 | regk_iop_sw_cfg_cpu = 0x00000000, | |
544 | regk_iop_sw_cfg_gated_clk0 = 0x0000000e, | |
545 | regk_iop_sw_cfg_gated_clk1 = 0x0000000f, | |
546 | regk_iop_sw_cfg_gio0 = 0x00000004, | |
547 | regk_iop_sw_cfg_gio1 = 0x00000001, | |
548 | regk_iop_sw_cfg_gio2 = 0x00000005, | |
549 | regk_iop_sw_cfg_gio3 = 0x00000002, | |
550 | regk_iop_sw_cfg_gio4 = 0x00000006, | |
551 | regk_iop_sw_cfg_gio5 = 0x00000003, | |
552 | regk_iop_sw_cfg_gio6 = 0x00000007, | |
553 | regk_iop_sw_cfg_gio7 = 0x00000004, | |
554 | regk_iop_sw_cfg_gio_in18 = 0x00000002, | |
555 | regk_iop_sw_cfg_gio_in19 = 0x00000003, | |
556 | regk_iop_sw_cfg_gio_in20 = 0x00000004, | |
557 | regk_iop_sw_cfg_gio_in21 = 0x00000005, | |
558 | regk_iop_sw_cfg_gio_in26 = 0x00000006, | |
559 | regk_iop_sw_cfg_gio_in27 = 0x00000007, | |
560 | regk_iop_sw_cfg_gio_in4 = 0x00000000, | |
561 | regk_iop_sw_cfg_gio_in5 = 0x00000001, | |
562 | regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, | |
563 | regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, | |
564 | regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, | |
565 | regk_iop_sw_cfg_mpu = 0x00000001, | |
566 | regk_iop_sw_cfg_none = 0x00000000, | |
567 | regk_iop_sw_cfg_pdp_out = 0x00000001, | |
568 | regk_iop_sw_cfg_pdp_out_hi = 0x00000001, | |
569 | regk_iop_sw_cfg_pdp_out_lo = 0x00000000, | |
570 | regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, | |
571 | regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, | |
572 | regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, | |
573 | regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, | |
574 | regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, | |
575 | regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, | |
576 | regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, | |
577 | regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, | |
578 | regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, | |
579 | regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, | |
580 | regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, | |
581 | regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, | |
582 | regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, | |
583 | regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, | |
584 | regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, | |
585 | regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, | |
586 | regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, | |
587 | regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, | |
588 | regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, | |
589 | regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, | |
590 | regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, | |
591 | regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, | |
592 | regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, | |
593 | regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, | |
594 | regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, | |
595 | regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, | |
596 | regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, | |
597 | regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, | |
598 | regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, | |
599 | regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, | |
600 | regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, | |
601 | regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, | |
602 | regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, | |
603 | regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, | |
604 | regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, | |
605 | regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, | |
606 | regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, | |
607 | regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, | |
608 | regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, | |
609 | regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, | |
610 | regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, | |
611 | regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, | |
612 | regk_iop_sw_cfg_sdp_out = 0x00000004, | |
613 | regk_iop_sw_cfg_size16 = 0x00000002, | |
614 | regk_iop_sw_cfg_size24 = 0x00000003, | |
615 | regk_iop_sw_cfg_size32 = 0x00000004, | |
616 | regk_iop_sw_cfg_size8 = 0x00000001, | |
617 | regk_iop_sw_cfg_spu = 0x00000002, | |
618 | regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, | |
619 | regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, | |
620 | regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, | |
621 | regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, | |
622 | regk_iop_sw_cfg_spu_g0 = 0x00000007, | |
623 | regk_iop_sw_cfg_spu_g1 = 0x00000007, | |
624 | regk_iop_sw_cfg_spu_g2 = 0x00000007, | |
625 | regk_iop_sw_cfg_spu_g3 = 0x00000007, | |
626 | regk_iop_sw_cfg_spu_g4 = 0x00000007, | |
627 | regk_iop_sw_cfg_spu_g5 = 0x00000007, | |
628 | regk_iop_sw_cfg_spu_g6 = 0x00000007, | |
629 | regk_iop_sw_cfg_spu_g7 = 0x00000007, | |
630 | regk_iop_sw_cfg_spu_gio0 = 0x00000000, | |
631 | regk_iop_sw_cfg_spu_gio1 = 0x00000001, | |
632 | regk_iop_sw_cfg_spu_gio5 = 0x00000005, | |
633 | regk_iop_sw_cfg_spu_gio6 = 0x00000006, | |
634 | regk_iop_sw_cfg_spu_gio7 = 0x00000007, | |
635 | regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, | |
636 | regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, | |
637 | regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, | |
638 | regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, | |
639 | regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, | |
640 | regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, | |
641 | regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, | |
642 | regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, | |
643 | regk_iop_sw_cfg_spu_gioout0 = 0x00000000, | |
644 | regk_iop_sw_cfg_spu_gioout1 = 0x00000000, | |
645 | regk_iop_sw_cfg_spu_gioout10 = 0x00000007, | |
646 | regk_iop_sw_cfg_spu_gioout11 = 0x00000007, | |
647 | regk_iop_sw_cfg_spu_gioout12 = 0x00000007, | |
648 | regk_iop_sw_cfg_spu_gioout13 = 0x00000007, | |
649 | regk_iop_sw_cfg_spu_gioout14 = 0x00000007, | |
650 | regk_iop_sw_cfg_spu_gioout15 = 0x00000007, | |
651 | regk_iop_sw_cfg_spu_gioout16 = 0x00000007, | |
652 | regk_iop_sw_cfg_spu_gioout17 = 0x00000007, | |
653 | regk_iop_sw_cfg_spu_gioout18 = 0x00000007, | |
654 | regk_iop_sw_cfg_spu_gioout19 = 0x00000007, | |
655 | regk_iop_sw_cfg_spu_gioout2 = 0x00000001, | |
656 | regk_iop_sw_cfg_spu_gioout20 = 0x00000007, | |
657 | regk_iop_sw_cfg_spu_gioout21 = 0x00000007, | |
658 | regk_iop_sw_cfg_spu_gioout22 = 0x00000007, | |
659 | regk_iop_sw_cfg_spu_gioout23 = 0x00000007, | |
660 | regk_iop_sw_cfg_spu_gioout24 = 0x00000007, | |
661 | regk_iop_sw_cfg_spu_gioout25 = 0x00000007, | |
662 | regk_iop_sw_cfg_spu_gioout26 = 0x00000007, | |
663 | regk_iop_sw_cfg_spu_gioout27 = 0x00000007, | |
664 | regk_iop_sw_cfg_spu_gioout28 = 0x00000007, | |
665 | regk_iop_sw_cfg_spu_gioout29 = 0x00000007, | |
666 | regk_iop_sw_cfg_spu_gioout3 = 0x00000001, | |
667 | regk_iop_sw_cfg_spu_gioout30 = 0x00000007, | |
668 | regk_iop_sw_cfg_spu_gioout31 = 0x00000007, | |
669 | regk_iop_sw_cfg_spu_gioout4 = 0x00000002, | |
670 | regk_iop_sw_cfg_spu_gioout5 = 0x00000002, | |
671 | regk_iop_sw_cfg_spu_gioout6 = 0x00000003, | |
672 | regk_iop_sw_cfg_spu_gioout7 = 0x00000003, | |
673 | regk_iop_sw_cfg_spu_gioout8 = 0x00000007, | |
674 | regk_iop_sw_cfg_spu_gioout9 = 0x00000007, | |
675 | regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, | |
676 | regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, | |
677 | regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, | |
678 | regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, | |
679 | regk_iop_sw_cfg_timer_grp0 = 0x00000000, | |
680 | regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, | |
681 | regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, | |
682 | regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, | |
683 | regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, | |
684 | regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, | |
685 | regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, | |
686 | regk_iop_sw_cfg_timer_grp1 = 0x00000000, | |
687 | regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, | |
688 | regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, | |
689 | regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, | |
690 | regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, | |
691 | regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, | |
692 | regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, | |
693 | regk_iop_sw_cfg_trig0_0 = 0x00000000, | |
694 | regk_iop_sw_cfg_trig0_1 = 0x00000000, | |
695 | regk_iop_sw_cfg_trig0_2 = 0x00000000, | |
696 | regk_iop_sw_cfg_trig0_3 = 0x00000000, | |
697 | regk_iop_sw_cfg_trig1_0 = 0x00000000, | |
698 | regk_iop_sw_cfg_trig1_1 = 0x00000000, | |
699 | regk_iop_sw_cfg_trig1_2 = 0x00000000, | |
700 | regk_iop_sw_cfg_trig1_3 = 0x00000000, | |
701 | regk_iop_sw_cfg_trig2_0 = 0x00000001, | |
702 | regk_iop_sw_cfg_trig2_1 = 0x00000001, | |
703 | regk_iop_sw_cfg_trig2_2 = 0x00000001, | |
704 | regk_iop_sw_cfg_trig2_3 = 0x00000001, | |
705 | regk_iop_sw_cfg_trig3_0 = 0x00000001, | |
706 | regk_iop_sw_cfg_trig3_1 = 0x00000001, | |
707 | regk_iop_sw_cfg_trig3_2 = 0x00000001, | |
708 | regk_iop_sw_cfg_trig3_3 = 0x00000001, | |
709 | regk_iop_sw_cfg_trig4_0 = 0x00000002, | |
710 | regk_iop_sw_cfg_trig4_1 = 0x00000002, | |
711 | regk_iop_sw_cfg_trig4_2 = 0x00000002, | |
712 | regk_iop_sw_cfg_trig4_3 = 0x00000002, | |
713 | regk_iop_sw_cfg_trig5_0 = 0x00000002, | |
714 | regk_iop_sw_cfg_trig5_1 = 0x00000002, | |
715 | regk_iop_sw_cfg_trig5_2 = 0x00000002, | |
716 | regk_iop_sw_cfg_trig5_3 = 0x00000002, | |
717 | regk_iop_sw_cfg_trig6_0 = 0x00000003, | |
718 | regk_iop_sw_cfg_trig6_1 = 0x00000003, | |
719 | regk_iop_sw_cfg_trig6_2 = 0x00000003, | |
720 | regk_iop_sw_cfg_trig6_3 = 0x00000003, | |
721 | regk_iop_sw_cfg_trig7_0 = 0x00000003, | |
722 | regk_iop_sw_cfg_trig7_1 = 0x00000003, | |
723 | regk_iop_sw_cfg_trig7_2 = 0x00000003, | |
724 | regk_iop_sw_cfg_trig7_3 = 0x00000003 | |
725 | }; | |
726 | #endif /* __iop_sw_cfg_defs_h */ |