[mirror_ubuntu-bionic-kernel.git] / arch / cris / include / arch-v32 / mach-a3 / mach / hwregs / iop / iop_sw_spu_defs.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __iop_sw_spu_defs_h
#define __iop_sw_spu_defs_h

/*
 * This file is autogenerated from
 *   file:           iop_sw_spu.r
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope iop_sw_spu */

/* Register r_mpu_trace, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0

/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int keep_owner : 1;
  unsigned int cmd        : 2;
  unsigned int size       : 3;
  unsigned int wr_spu_mem : 1;
  unsigned int dummy1     : 25;
} reg_iop_sw_spu_rw_mc_ctrl;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4

/* Register rw_mc_data, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_mc_data;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8

/* Register rw_mc_addr, scope iop_sw_spu, type rw */
typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12

/* Register rs_mc_data, scope iop_sw_spu, type rs */
typedef unsigned int reg_iop_sw_spu_rs_mc_data;
#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16

/* Register r_mc_data, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_mc_data;
#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20

/* Register r_mc_stat, scope iop_sw_spu, type r */
typedef struct {
  unsigned int busy_cpu     : 1;
  unsigned int busy_mpu     : 1;
  unsigned int busy_spu     : 1;
  unsigned int owned_by_cpu : 1;
  unsigned int owned_by_mpu : 1;
  unsigned int owned_by_spu : 1;
  unsigned int dummy1       : 26;
} reg_iop_sw_spu_r_mc_stat;
#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24

/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28

/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
} reg_iop_sw_spu_rw_bus_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32

/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36

/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 1;
  unsigned int byte1 : 1;
  unsigned int byte2 : 1;
  unsigned int byte3 : 1;
  unsigned int dummy1 : 28;
} reg_iop_sw_spu_rw_bus_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40

/* Register r_bus_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_bus_in;
#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44

/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48

/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52

/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_oe_clr_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56

/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 32;
} reg_iop_sw_spu_rw_gio_oe_set_mask;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60

/* Register r_gio_in, scope iop_sw_spu, type r */
typedef unsigned int reg_iop_sw_spu_r_gio_in;
#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64

/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68

/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72

/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte0 : 8;
  unsigned int byte1 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76

/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int byte2 : 8;
  unsigned int byte3 : 8;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_bus_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80

/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84

/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88

/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92

/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96

/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100

/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104

/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108

/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int val : 16;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112

/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_cpu_intr;
#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116

/* Register r_cpu_intr, scope iop_sw_spu, type r */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_r_cpu_intr;
#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120

/* Register r_hw_intr, scope iop_sw_spu, type r */
typedef struct {
  unsigned int trigger_grp0   : 1;
  unsigned int trigger_grp1   : 1;
  unsigned int trigger_grp2   : 1;
  unsigned int trigger_grp3   : 1;
  unsigned int trigger_grp4   : 1;
  unsigned int trigger_grp5   : 1;
  unsigned int trigger_grp6   : 1;
  unsigned int trigger_grp7   : 1;
  unsigned int timer_grp0     : 1;
  unsigned int timer_grp1     : 1;
  unsigned int fifo_out       : 1;
  unsigned int fifo_out_extra : 1;
  unsigned int fifo_in        : 1;
  unsigned int fifo_in_extra  : 1;
  unsigned int dmc_out        : 1;
  unsigned int dmc_in         : 1;
  unsigned int dummy1         : 16;
} reg_iop_sw_spu_r_hw_intr;
#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124

/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_rw_mpu_intr;
#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128

/* Register r_mpu_intr, scope iop_sw_spu, type r */
typedef struct {
  unsigned int intr0  : 1;
  unsigned int intr1  : 1;
  unsigned int intr2  : 1;
  unsigned int intr3  : 1;
  unsigned int intr4  : 1;
  unsigned int intr5  : 1;
  unsigned int intr6  : 1;
  unsigned int intr7  : 1;
  unsigned int intr8  : 1;
  unsigned int intr9  : 1;
  unsigned int intr10 : 1;
  unsigned int intr11 : 1;
  unsigned int intr12 : 1;
  unsigned int intr13 : 1;
  unsigned int intr14 : 1;
  unsigned int intr15 : 1;
  unsigned int dummy1 : 16;
} reg_iop_sw_spu_r_mpu_intr;
#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132


/* Constants */
enum {
  regk_iop_sw_spu_copy                     = 0x00000000,
  regk_iop_sw_spu_no                       = 0x00000000,
  regk_iop_sw_spu_nop                      = 0x00000000,
  regk_iop_sw_spu_rd                       = 0x00000002,
  regk_iop_sw_spu_reg_copy                 = 0x00000001,
  regk_iop_sw_spu_rw_bus_clr_mask_default  = 0x00000000,
  regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_bus_set_mask_default  = 0x00000000,
  regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
  regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
  regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
  regk_iop_sw_spu_set                      = 0x00000001,
  regk_iop_sw_spu_wr                       = 0x00000003,
  regk_iop_sw_spu_yes                      = 0x00000001
};
#endif /* __iop_sw_spu_defs_h */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
58d08319 JN	2	#ifndef __iop_sw_spu_defs_h
	3	#define __iop_sw_spu_defs_h
	4
	5	/*
	6	* This file is autogenerated from
	7	* file: iop_sw_spu.r
	8	*
	9	* by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
	10	* Any changes here will be lost.
	11	*
	12	* -- buffer-read-only: t --
	13	*/
	14	/* Main access macros */
	15	#ifndef REG_RD
	16	#define REG_RD( scope, inst, reg ) \
	17	REG_READ( reg_##scope##_##reg, \
	18	(inst) + REG_RD_ADDR_##scope##_##reg )
	19	#endif
	20
	21	#ifndef REG_WR
	22	#define REG_WR( scope, inst, reg, val ) \
	23	REG_WRITE( reg_##scope##_##reg, \
	24	(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	25	#endif
	26
	27	#ifndef REG_RD_VECT
	28	#define REG_RD_VECT( scope, inst, reg, index ) \
	29	REG_READ( reg_##scope##_##reg, \
	30	(inst) + REG_RD_ADDR_##scope##_##reg + \
	31	(index) * STRIDE_##scope##_##reg )
	32	#endif
	33
	34	#ifndef REG_WR_VECT
	35	#define REG_WR_VECT( scope, inst, reg, index, val ) \
	36	REG_WRITE( reg_##scope##_##reg, \
	37	(inst) + REG_WR_ADDR_##scope##_##reg + \
	38	(index) * STRIDE_##scope##_##reg, (val) )
	39	#endif
	40
	41	#ifndef REG_RD_INT
	42	#define REG_RD_INT( scope, inst, reg ) \
	43	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
	44	#endif
	45
	46	#ifndef REG_WR_INT
	47	#define REG_WR_INT( scope, inst, reg, val ) \
	48	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
	49	#endif
	50
	51	#ifndef REG_RD_INT_VECT
	52	#define REG_RD_INT_VECT( scope, inst, reg, index ) \
	53	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	54	(index) * STRIDE_##scope##_##reg )
	55	#endif
	56
	57	#ifndef REG_WR_INT_VECT
	58	#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
	59	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	60	(index) * STRIDE_##scope##_##reg, (val) )
	61	#endif
	62
	63	#ifndef REG_TYPE_CONV
	64	#define REG_TYPE_CONV( type, orgtype, val ) \
	65	( { union { orgtype o; type n; } r; r.o = val; r.n; } )
66	#endif
67
68	#ifndef reg_page_size
69	#define reg_page_size 8192
70	#endif
71
72	#ifndef REG_ADDR
73	#define REG_ADDR( scope, inst, reg ) \
74	( (inst) + REG_RD_ADDR_##scope##_##reg )
75	#endif
76
77	#ifndef REG_ADDR_VECT
78	#define REG_ADDR_VECT( scope, inst, reg, index ) \
79	( (inst) + REG_RD_ADDR_##scope##_##reg + \
80	(index) * STRIDE_##scope##_##reg )
81	#endif
82
83	/* C-code for register scope iop_sw_spu */
84
85	/* Register r_mpu_trace, scope iop_sw_spu, type r */
86	typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
87	#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
88
89	/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
90	typedef struct {
91	unsigned int keep_owner : 1;
92	unsigned int cmd : 2;
93	unsigned int size : 3;
94	unsigned int wr_spu_mem : 1;
95	unsigned int dummy1 : 25;
96	} reg_iop_sw_spu_rw_mc_ctrl;
97	#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
98	#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
99
100	/* Register rw_mc_data, scope iop_sw_spu, type rw */
101	typedef struct {
102	unsigned int val : 32;
103	} reg_iop_sw_spu_rw_mc_data;
104	#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
105	#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
106
107	/* Register rw_mc_addr, scope iop_sw_spu, type rw */
108	typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
109	#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
110	#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
111
112	/* Register rs_mc_data, scope iop_sw_spu, type rs */
113	typedef unsigned int reg_iop_sw_spu_rs_mc_data;
114	#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
115
116	/* Register r_mc_data, scope iop_sw_spu, type r */
117	typedef unsigned int reg_iop_sw_spu_r_mc_data;
118	#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
119
120	/* Register r_mc_stat, scope iop_sw_spu, type r */
121	typedef struct {
122	unsigned int busy_cpu : 1;
123	unsigned int busy_mpu : 1;
124	unsigned int busy_spu : 1;
125	unsigned int owned_by_cpu : 1;
126	unsigned int owned_by_mpu : 1;
127	unsigned int owned_by_spu : 1;
128	unsigned int dummy1 : 26;
129	} reg_iop_sw_spu_r_mc_stat;
130	#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
131
132	/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
133	typedef struct {
134	unsigned int byte0 : 8;
135	unsigned int byte1 : 8;
136	unsigned int byte2 : 8;
137	unsigned int byte3 : 8;
138	} reg_iop_sw_spu_rw_bus_clr_mask;
139	#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
140	#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
141
142	/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
143	typedef struct {
144	unsigned int byte0 : 8;
145	unsigned int byte1 : 8;
146	unsigned int byte2 : 8;
147	unsigned int byte3 : 8;
148	} reg_iop_sw_spu_rw_bus_set_mask;
149	#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
150	#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
151
152	/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
153	typedef struct {
154	unsigned int byte0 : 1;
155	unsigned int byte1 : 1;
156	unsigned int byte2 : 1;
157	unsigned int byte3 : 1;
158	unsigned int dummy1 : 28;
159	} reg_iop_sw_spu_rw_bus_oe_clr_mask;
160	#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
161	#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
162
163	/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
164	typedef struct {
165	unsigned int byte0 : 1;
166	unsigned int byte1 : 1;
167	unsigned int byte2 : 1;
168	unsigned int byte3 : 1;
169	unsigned int dummy1 : 28;
170	} reg_iop_sw_spu_rw_bus_oe_set_mask;
171	#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
172	#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
173
174	/* Register r_bus_in, scope iop_sw_spu, type r */
175	typedef unsigned int reg_iop_sw_spu_r_bus_in;
176	#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
177
178	/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
179	typedef struct {
180	unsigned int val : 32;
181	} reg_iop_sw_spu_rw_gio_clr_mask;
182	#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
183	#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
184
185	/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
186	typedef struct {
187	unsigned int val : 32;
188	} reg_iop_sw_spu_rw_gio_set_mask;
189	#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
190	#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
191
192	/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
193	typedef struct {
194	unsigned int val : 32;
195	} reg_iop_sw_spu_rw_gio_oe_clr_mask;
196	#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
197	#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
198
199	/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
200	typedef struct {
201	unsigned int val : 32;
202	} reg_iop_sw_spu_rw_gio_oe_set_mask;
203	#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
204	#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
205
206	/* Register r_gio_in, scope iop_sw_spu, type r */
207	typedef unsigned int reg_iop_sw_spu_r_gio_in;
208	#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
209
210	/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
211	typedef struct {
212	unsigned int byte0 : 8;
213	unsigned int byte1 : 8;
214	unsigned int dummy1 : 16;
215	} reg_iop_sw_spu_rw_bus_clr_mask_lo;
216	#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
217	#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
218
219	/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
220	typedef struct {
221	unsigned int byte2 : 8;
222	unsigned int byte3 : 8;
223	unsigned int dummy1 : 16;
224	} reg_iop_sw_spu_rw_bus_clr_mask_hi;
225	#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
226	#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
227
228	/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
229	typedef struct {
230	unsigned int byte0 : 8;
231	unsigned int byte1 : 8;
232	unsigned int dummy1 : 16;
233	} reg_iop_sw_spu_rw_bus_set_mask_lo;
234	#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
235	#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
236
237	/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
238	typedef struct {
239	unsigned int byte2 : 8;
240	unsigned int byte3 : 8;
241	unsigned int dummy1 : 16;
242	} reg_iop_sw_spu_rw_bus_set_mask_hi;
243	#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
244	#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
245
246	/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
247	typedef struct {
248	unsigned int val : 16;
249	unsigned int dummy1 : 16;
250	} reg_iop_sw_spu_rw_gio_clr_mask_lo;
251	#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
252	#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
253
254	/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
255	typedef struct {
256	unsigned int val : 16;
257	unsigned int dummy1 : 16;
258	} reg_iop_sw_spu_rw_gio_clr_mask_hi;
259	#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
260	#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
261
262	/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
263	typedef struct {
264	unsigned int val : 16;
265	unsigned int dummy1 : 16;
266	} reg_iop_sw_spu_rw_gio_set_mask_lo;
267	#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
268	#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
269
270	/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
271	typedef struct {
272	unsigned int val : 16;
273	unsigned int dummy1 : 16;
274	} reg_iop_sw_spu_rw_gio_set_mask_hi;
275	#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
276	#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
277
278	/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
279	typedef struct {
280	unsigned int val : 16;
281	unsigned int dummy1 : 16;
282	} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
283	#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
284	#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
285
286	/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
287	typedef struct {
288	unsigned int val : 16;
289	unsigned int dummy1 : 16;
290	} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
291	#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
292	#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
293
294	/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
295	typedef struct {
296	unsigned int val : 16;
297	unsigned int dummy1 : 16;
298	} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
299	#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
300	#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
301
302	/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
303	typedef struct {
304	unsigned int val : 16;
305	unsigned int dummy1 : 16;
306	} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
307	#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
308	#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
309
310	/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
311	typedef struct {
312	unsigned int intr0 : 1;
313	unsigned int intr1 : 1;
314	unsigned int intr2 : 1;
315	unsigned int intr3 : 1;
316	unsigned int intr4 : 1;
317	unsigned int intr5 : 1;
318	unsigned int intr6 : 1;
319	unsigned int intr7 : 1;
320	unsigned int intr8 : 1;
321	unsigned int intr9 : 1;
322	unsigned int intr10 : 1;
323	unsigned int intr11 : 1;
324	unsigned int intr12 : 1;
325	unsigned int intr13 : 1;
326	unsigned int intr14 : 1;
327	unsigned int intr15 : 1;
328	unsigned int dummy1 : 16;
329	} reg_iop_sw_spu_rw_cpu_intr;
330	#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
331	#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
332
333	/* Register r_cpu_intr, scope iop_sw_spu, type r */
334	typedef struct {
335	unsigned int intr0 : 1;
336	unsigned int intr1 : 1;
337	unsigned int intr2 : 1;
338	unsigned int intr3 : 1;
339	unsigned int intr4 : 1;
340	unsigned int intr5 : 1;
341	unsigned int intr6 : 1;
342	unsigned int intr7 : 1;
343	unsigned int intr8 : 1;
344	unsigned int intr9 : 1;
345	unsigned int intr10 : 1;
346	unsigned int intr11 : 1;
347	unsigned int intr12 : 1;
348	unsigned int intr13 : 1;
349	unsigned int intr14 : 1;
350	unsigned int intr15 : 1;
351	unsigned int dummy1 : 16;
352	} reg_iop_sw_spu_r_cpu_intr;
353	#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
354
355	/* Register r_hw_intr, scope iop_sw_spu, type r */
356	typedef struct {
357	unsigned int trigger_grp0 : 1;
358	unsigned int trigger_grp1 : 1;
359	unsigned int trigger_grp2 : 1;
360	unsigned int trigger_grp3 : 1;
361	unsigned int trigger_grp4 : 1;
362	unsigned int trigger_grp5 : 1;
363	unsigned int trigger_grp6 : 1;
364	unsigned int trigger_grp7 : 1;
365	unsigned int timer_grp0 : 1;
366	unsigned int timer_grp1 : 1;
367	unsigned int fifo_out : 1;
368	unsigned int fifo_out_extra : 1;
369	unsigned int fifo_in : 1;
370	unsigned int fifo_in_extra : 1;
371	unsigned int dmc_out : 1;
372	unsigned int dmc_in : 1;
373	unsigned int dummy1 : 16;
374	} reg_iop_sw_spu_r_hw_intr;
375	#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
376
377	/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
378	typedef struct {
379	unsigned int intr0 : 1;
380	unsigned int intr1 : 1;
381	unsigned int intr2 : 1;
382	unsigned int intr3 : 1;
383	unsigned int intr4 : 1;
384	unsigned int intr5 : 1;
385	unsigned int intr6 : 1;
386	unsigned int intr7 : 1;
387	unsigned int intr8 : 1;
388	unsigned int intr9 : 1;
389	unsigned int intr10 : 1;
390	unsigned int intr11 : 1;
391	unsigned int intr12 : 1;
392	unsigned int intr13 : 1;
393	unsigned int intr14 : 1;
394	unsigned int intr15 : 1;
395	unsigned int dummy1 : 16;
396	} reg_iop_sw_spu_rw_mpu_intr;
397	#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
398	#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
399
400	/* Register r_mpu_intr, scope iop_sw_spu, type r */
401	typedef struct {
402	unsigned int intr0 : 1;
403	unsigned int intr1 : 1;
404	unsigned int intr2 : 1;
405	unsigned int intr3 : 1;
406	unsigned int intr4 : 1;
407	unsigned int intr5 : 1;
408	unsigned int intr6 : 1;
409	unsigned int intr7 : 1;
410	unsigned int intr8 : 1;
411	unsigned int intr9 : 1;
412	unsigned int intr10 : 1;
413	unsigned int intr11 : 1;
414	unsigned int intr12 : 1;
415	unsigned int intr13 : 1;
416	unsigned int intr14 : 1;
417	unsigned int intr15 : 1;
418	unsigned int dummy1 : 16;
419	} reg_iop_sw_spu_r_mpu_intr;
420	#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
421
422
423	/* Constants */
424	enum {
425	regk_iop_sw_spu_copy = 0x00000000,
426	regk_iop_sw_spu_no = 0x00000000,
427	regk_iop_sw_spu_nop = 0x00000000,
428	regk_iop_sw_spu_rd = 0x00000002,
429	regk_iop_sw_spu_reg_copy = 0x00000001,
430	regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000,
431	regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
432	regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
433	regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000,
434	regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
435	regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
436	regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
437	regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
438	regk_iop_sw_spu_set = 0x00000001,
439	regk_iop_sw_spu_wr = 0x00000003,
440	regk_iop_sw_spu_yes = 0x00000001
441	};
442	#endif /* __iop_sw_spu_defs_h */