projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 58d08319 JN |
2 | #ifndef __l2cache_defs_h |
| 3 | #define __l2cache_defs_h | |
| 4 | ||
| 5 | /* | |
| 6 | * This file is autogenerated from | |
| 7 | * file: l2cache.r | |
| 8 | * | |
| 9 | * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r | |
| 10 | * Any changes here will be lost. | |
| 11 | * | |
| 12 | * -*- buffer-read-only: t -*- | |
| 13 | */ | |
| 14 | /* Main access macros */ | |
| 15 | #ifndef REG_RD | |
| 16 | #define REG_RD( scope, inst, reg ) \ | |
| 17 | REG_READ( reg_##scope##_##reg, \ | |
| 18 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 19 | #endif | |
| 20 | ||
| 21 | #ifndef REG_WR | |
| 22 | #define REG_WR( scope, inst, reg, val ) \ | |
| 23 | REG_WRITE( reg_##scope##_##reg, \ | |
| 24 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
| 25 | #endif | |
| 26 | ||
| 27 | #ifndef REG_RD_VECT | |
| 28 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
| 29 | REG_READ( reg_##scope##_##reg, \ | |
| 30 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 31 | (index) * STRIDE_##scope##_##reg ) | |
| 32 | #endif | |
| 33 | ||
| 34 | #ifndef REG_WR_VECT | |
| 35 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
| 36 | REG_WRITE( reg_##scope##_##reg, \ | |
| 37 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
| 38 | (index) * STRIDE_##scope##_##reg, (val) ) | |
| 39 | #endif | |
| 40 | ||
| 41 | #ifndef REG_RD_INT | |
| 42 | #define REG_RD_INT( scope, inst, reg ) \ | |
| 43 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 44 | #endif | |
| 45 | ||
| 46 | #ifndef REG_WR_INT | |
| 47 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
| 48 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
| 49 | #endif | |
| 50 | ||
| 51 | #ifndef REG_RD_INT_VECT | |
| 52 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
| 53 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 54 | (index) * STRIDE_##scope##_##reg ) | |
| 55 | #endif | |
| 56 | ||
| 57 | #ifndef REG_WR_INT_VECT | |
| 58 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
| 59 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
| 60 | (index) * STRIDE_##scope##_##reg, (val) ) | |
| 61 | #endif | |
| 62 | ||
| 63 | #ifndef REG_TYPE_CONV | |
| 64 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
| 65 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
| 66 | #endif | |
| 67 | ||
| 68 | #ifndef reg_page_size | |
| 69 | #define reg_page_size 8192 | |
| 70 | #endif | |
| 71 | ||
| 72 | #ifndef REG_ADDR | |
| 73 | #define REG_ADDR( scope, inst, reg ) \ | |
| 74 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
| 75 | #endif | |
| 76 | ||
| 77 | #ifndef REG_ADDR_VECT | |
| 78 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
| 79 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
| 80 | (index) * STRIDE_##scope##_##reg ) | |
| 81 | #endif | |
| 82 | ||
| 83 | /* C-code for register scope l2cache */ | |
| 84 | ||
| 85 | /* Register rw_cfg, scope l2cache, type rw */ | |
| 86 | typedef struct { | |
| 87 | unsigned int en : 1; | |
| 88 | unsigned int dummy1 : 31; | |
| 89 | } reg_l2cache_rw_cfg; | |
| 90 | #define REG_RD_ADDR_l2cache_rw_cfg 0 | |
| 91 | #define REG_WR_ADDR_l2cache_rw_cfg 0 | |
| 92 | ||
| 93 | /* Register rw_ctrl, scope l2cache, type rw */ | |
| 94 | typedef struct { | |
| 95 | unsigned int dummy1 : 7; | |
| 96 | unsigned int cbase : 9; | |
| 97 | unsigned int dummy2 : 4; | |
| 98 | unsigned int csize : 10; | |
| 99 | unsigned int dummy3 : 2; | |
| 100 | } reg_l2cache_rw_ctrl; | |
| 101 | #define REG_RD_ADDR_l2cache_rw_ctrl 4 | |
| 102 | #define REG_WR_ADDR_l2cache_rw_ctrl 4 | |
| 103 | ||
| 104 | /* Register rw_idxop, scope l2cache, type rw */ | |
| 105 | typedef struct { | |
| 106 | unsigned int idx : 10; | |
| 107 | unsigned int dummy1 : 14; | |
| 108 | unsigned int way : 3; | |
| 109 | unsigned int dummy2 : 2; | |
| 110 | unsigned int cmd : 3; | |
| 111 | } reg_l2cache_rw_idxop; | |
| 112 | #define REG_RD_ADDR_l2cache_rw_idxop 8 | |
| 113 | #define REG_WR_ADDR_l2cache_rw_idxop 8 | |
| 114 | ||
| 115 | /* Register rw_addrop_addr, scope l2cache, type rw */ | |
| 116 | typedef struct { | |
| 117 | unsigned int addr : 32; | |
| 118 | } reg_l2cache_rw_addrop_addr; | |
| 119 | #define REG_RD_ADDR_l2cache_rw_addrop_addr 12 | |
| 120 | #define REG_WR_ADDR_l2cache_rw_addrop_addr 12 | |
| 121 | ||
| 122 | /* Register rw_addrop_ctrl, scope l2cache, type rw */ | |
| 123 | typedef struct { | |
| 124 | unsigned int size : 16; | |
| 125 | unsigned int dummy1 : 13; | |
| 126 | unsigned int cmd : 3; | |
| 127 | } reg_l2cache_rw_addrop_ctrl; | |
| 128 | #define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 | |
| 129 | #define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 | |
| 130 | ||
| 131 | ||
| 132 | /* Constants */ | |
| 133 | enum { | |
| 134 | regk_l2cache_flush = 0x00000001, | |
| 135 | regk_l2cache_no = 0x00000000, | |
| 136 | regk_l2cache_rw_addrop_addr_default = 0x00000000, | |
| 137 | regk_l2cache_rw_addrop_ctrl_default = 0x00000000, | |
| 138 | regk_l2cache_rw_cfg_default = 0x00000000, | |
| 139 | regk_l2cache_rw_ctrl_default = 0x00000000, | |
| 140 | regk_l2cache_rw_idxop_default = 0x00000000, | |
| 141 | regk_l2cache_yes = 0x00000001 | |
| 142 | }; | |
| 143 | #endif /* __l2cache_defs_h */ |