]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* irq-mb93091.c: MB93091 FPGA interrupt handling |
2 | * | |
3 | * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
1da177e4 LT |
12 | #include <linux/ptrace.h> |
13 | #include <linux/errno.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/irq.h> | |
20 | ||
21 | #include <asm/io.h> | |
22 | #include <asm/system.h> | |
23 | #include <asm/bitops.h> | |
24 | #include <asm/delay.h> | |
25 | #include <asm/irq.h> | |
26 | #include <asm/irc-regs.h> | |
1da177e4 LT |
27 | |
28 | #define __reg16(ADDR) (*(volatile unsigned short *)(ADDR)) | |
29 | ||
30 | #define __get_IMR() ({ __reg16(0xffc00004); }) | |
31 | #define __set_IMR(M) do { __reg16(0xffc00004) = (M); wmb(); } while(0) | |
32 | #define __get_IFR() ({ __reg16(0xffc0000c); }) | |
33 | #define __clr_IFR(M) do { __reg16(0xffc0000c) = ~(M); wmb(); } while(0) | |
34 | ||
1da177e4 | 35 | |
1da177e4 | 36 | /* |
1bcbba30 | 37 | * on-motherboard FPGA PIC operations |
1da177e4 | 38 | */ |
1bcbba30 DH |
39 | static void frv_fpga_enable(unsigned int irq) |
40 | { | |
41 | uint16_t imr = __get_IMR(); | |
1da177e4 | 42 | |
1bcbba30 | 43 | imr &= ~(1 << (irq - IRQ_BASE_FPGA)); |
1da177e4 | 44 | |
1bcbba30 DH |
45 | __set_IMR(imr); |
46 | } | |
1da177e4 | 47 | |
1bcbba30 | 48 | static void frv_fpga_disable(unsigned int irq) |
1da177e4 LT |
49 | { |
50 | uint16_t imr = __get_IMR(); | |
51 | ||
1bcbba30 | 52 | imr |= 1 << (irq - IRQ_BASE_FPGA); |
1da177e4 LT |
53 | |
54 | __set_IMR(imr); | |
55 | } | |
56 | ||
1bcbba30 DH |
57 | static void frv_fpga_ack(unsigned int irq) |
58 | { | |
59 | __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); | |
60 | } | |
61 | ||
62 | static void frv_fpga_end(unsigned int irq) | |
63 | { | |
64 | } | |
65 | ||
66 | static struct irq_chip frv_fpga_pic = { | |
67 | .name = "mb93091", | |
68 | .enable = frv_fpga_enable, | |
69 | .disable = frv_fpga_disable, | |
70 | .ack = frv_fpga_ack, | |
71 | .mask = frv_fpga_disable, | |
72 | .unmask = frv_fpga_enable, | |
73 | .end = frv_fpga_end, | |
74 | }; | |
75 | ||
76 | /* | |
77 | * FPGA PIC interrupt handler | |
78 | */ | |
79 | static irqreturn_t fpga_interrupt(int irq, void *_mask, struct pt_regs *regs) | |
1da177e4 | 80 | { |
1bcbba30 DH |
81 | uint16_t imr, mask = (unsigned long) _mask; |
82 | irqreturn_t iret = 0; | |
1da177e4 LT |
83 | |
84 | imr = __get_IMR(); | |
1bcbba30 DH |
85 | mask = mask & ~imr & __get_IFR(); |
86 | ||
87 | /* poll all the triggered IRQs */ | |
88 | while (mask) { | |
89 | int irq; | |
90 | ||
91 | asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask)); | |
92 | irq = 31 - irq; | |
93 | mask &= ~(1 << irq); | |
94 | ||
95 | if (__do_IRQ(IRQ_BASE_FPGA + irq, regs)) | |
96 | iret |= IRQ_HANDLED; | |
1da177e4 | 97 | } |
1bcbba30 DH |
98 | |
99 | return iret; | |
1da177e4 LT |
100 | } |
101 | ||
1bcbba30 DH |
102 | /* |
103 | * define an interrupt action for each FPGA PIC output | |
104 | * - use dev_id to indicate the FPGA PIC input to output mappings | |
105 | */ | |
106 | static struct irqaction fpga_irq[4] = { | |
107 | [0] = { | |
108 | .handler = fpga_interrupt, | |
109 | .flags = IRQF_DISABLED | IRQF_SHARED, | |
110 | .mask = CPU_MASK_NONE, | |
111 | .name = "fpga.0", | |
112 | .dev_id = (void *) 0x0028UL, | |
113 | }, | |
114 | [1] = { | |
115 | .handler = fpga_interrupt, | |
116 | .flags = IRQF_DISABLED | IRQF_SHARED, | |
117 | .mask = CPU_MASK_NONE, | |
118 | .name = "fpga.1", | |
119 | .dev_id = (void *) 0x0050UL, | |
120 | }, | |
121 | [2] = { | |
122 | .handler = fpga_interrupt, | |
123 | .flags = IRQF_DISABLED | IRQF_SHARED, | |
124 | .mask = CPU_MASK_NONE, | |
125 | .name = "fpga.2", | |
126 | .dev_id = (void *) 0x1c00UL, | |
127 | }, | |
128 | [3] = { | |
129 | .handler = fpga_interrupt, | |
130 | .flags = IRQF_DISABLED | IRQF_SHARED, | |
131 | .mask = CPU_MASK_NONE, | |
132 | .name = "fpga.3", | |
133 | .dev_id = (void *) 0x6386UL, | |
134 | } | |
135 | }; | |
136 | ||
137 | /* | |
138 | * initialise the motherboard FPGA's PIC | |
139 | */ | |
1da177e4 LT |
140 | void __init fpga_init(void) |
141 | { | |
1bcbba30 DH |
142 | int irq; |
143 | ||
144 | /* all PIC inputs are all set to be low-level driven, apart from the | |
145 | * NMI button (15) which is fixed at falling-edge | |
146 | */ | |
1da177e4 LT |
147 | __set_IMR(0x7ffe); |
148 | __clr_IFR(0x0000); | |
149 | ||
1bcbba30 DH |
150 | for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++) |
151 | set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); | |
152 | ||
153 | set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); | |
154 | ||
155 | /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ | |
156 | setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]); | |
157 | setup_irq(IRQ_CPU_EXTERNAL1, &fpga_irq[1]); | |
158 | setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[2]); | |
159 | setup_irq(IRQ_CPU_EXTERNAL3, &fpga_irq[3]); | |
1da177e4 | 160 | } |