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013bf24c RK |
1 | /* |
2 | * IO definitions for the Hexagon architecture | |
3 | * | |
7c6a5df4 | 4 | * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. |
013bf24c RK |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 and | |
8 | * only version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
18 | * 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #ifndef _ASM_IO_H | |
22 | #define _ASM_IO_H | |
23 | ||
24 | #ifdef __KERNEL__ | |
25 | ||
26 | #include <linux/types.h> | |
013bf24c RK |
27 | #include <asm/iomap.h> |
28 | #include <asm/page.h> | |
29 | #include <asm/cacheflush.h> | |
013bf24c RK |
30 | |
31 | /* | |
32 | * We don't have PCI yet. | |
33 | * _IO_BASE is pointing at what should be unused virtual space. | |
34 | */ | |
35 | #define IO_SPACE_LIMIT 0xffff | |
36 | #define _IO_BASE ((void __iomem *)0xfe000000) | |
37 | ||
1ce81f4f RK |
38 | #define IOMEM(x) ((void __force __iomem *)(x)) |
39 | ||
013bf24c RK |
40 | extern int remap_area_pages(unsigned long start, unsigned long phys_addr, |
41 | unsigned long end, unsigned long flags); | |
42 | ||
43 | extern void __iounmap(const volatile void __iomem *addr); | |
44 | ||
45 | /* Defined in lib/io.c, needed for smc91x driver. */ | |
46 | extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); | |
47 | extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen); | |
48 | ||
49 | extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen); | |
50 | extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen); | |
51 | ||
52 | #define readsw(p, d, l) __raw_readsw(p, d, l) | |
53 | #define writesw(p, d, l) __raw_writesw(p, d, l) | |
54 | ||
55 | #define readsl(p, d, l) __raw_readsl(p, d, l) | |
56 | #define writesl(p, d, l) __raw_writesl(p, d, l) | |
57 | ||
58 | /* | |
59 | * virt_to_phys - map virtual address to physical | |
60 | * @address: address to map | |
61 | */ | |
62 | static inline unsigned long virt_to_phys(volatile void *address) | |
63 | { | |
64 | return __pa(address); | |
65 | } | |
66 | ||
67 | /* | |
68 | * phys_to_virt - map physical address to virtual | |
69 | * @address: address to map | |
70 | */ | |
71 | static inline void *phys_to_virt(unsigned long address) | |
72 | { | |
73 | return __va(address); | |
74 | } | |
75 | ||
76 | /* | |
77 | * convert a physical pointer to a virtual kernel pointer for | |
78 | * /dev/mem access. | |
79 | */ | |
80 | #define xlate_dev_kmem_ptr(p) __va(p) | |
81 | #define xlate_dev_mem_ptr(p) __va(p) | |
82 | ||
83 | /* | |
84 | * IO port access primitives. Hexagon doesn't have special IO access | |
85 | * instructions; all I/O is memory mapped. | |
86 | * | |
87 | * in/out are used for "ports", but we don't have "port instructions", | |
88 | * so these are really just memory mapped too. | |
89 | */ | |
90 | ||
91 | /* | |
92 | * readb - read byte from memory mapped device | |
93 | * @addr: pointer to memory | |
94 | * | |
95 | * Operates on "I/O bus memory space" | |
96 | */ | |
97 | static inline u8 readb(const volatile void __iomem *addr) | |
98 | { | |
99 | u8 val; | |
100 | asm volatile( | |
101 | "%0 = memb(%1);" | |
102 | : "=&r" (val) | |
103 | : "r" (addr) | |
104 | ); | |
105 | return val; | |
106 | } | |
107 | ||
108 | static inline u16 readw(const volatile void __iomem *addr) | |
109 | { | |
110 | u16 val; | |
111 | asm volatile( | |
112 | "%0 = memh(%1);" | |
113 | : "=&r" (val) | |
114 | : "r" (addr) | |
115 | ); | |
116 | return val; | |
117 | } | |
118 | ||
119 | static inline u32 readl(const volatile void __iomem *addr) | |
120 | { | |
121 | u32 val; | |
122 | asm volatile( | |
123 | "%0 = memw(%1);" | |
124 | : "=&r" (val) | |
125 | : "r" (addr) | |
126 | ); | |
127 | return val; | |
128 | } | |
129 | ||
130 | /* | |
131 | * writeb - write a byte to a memory location | |
132 | * @data: data to write to | |
133 | * @addr: pointer to memory | |
134 | * | |
135 | */ | |
136 | static inline void writeb(u8 data, volatile void __iomem *addr) | |
137 | { | |
138 | asm volatile( | |
139 | "memb(%0) = %1;" | |
140 | : | |
141 | : "r" (addr), "r" (data) | |
142 | : "memory" | |
143 | ); | |
144 | } | |
145 | ||
146 | static inline void writew(u16 data, volatile void __iomem *addr) | |
147 | { | |
148 | asm volatile( | |
149 | "memh(%0) = %1;" | |
150 | : | |
151 | : "r" (addr), "r" (data) | |
152 | : "memory" | |
153 | ); | |
154 | ||
155 | } | |
156 | ||
157 | static inline void writel(u32 data, volatile void __iomem *addr) | |
158 | { | |
159 | asm volatile( | |
160 | "memw(%0) = %1;" | |
161 | : | |
162 | : "r" (addr), "r" (data) | |
163 | : "memory" | |
164 | ); | |
165 | } | |
166 | ||
167 | #define __raw_writeb writeb | |
168 | #define __raw_writew writew | |
169 | #define __raw_writel writel | |
170 | ||
171 | #define __raw_readb readb | |
172 | #define __raw_readw readw | |
173 | #define __raw_readl readl | |
174 | ||
1ce81f4f RK |
175 | /* |
176 | * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626 | |
177 | */ | |
178 | ||
179 | #define readb_relaxed __raw_readb | |
180 | #define readw_relaxed __raw_readw | |
181 | #define readl_relaxed __raw_readl | |
182 | ||
183 | #define writeb_relaxed __raw_writeb | |
184 | #define writew_relaxed __raw_writew | |
185 | #define writel_relaxed __raw_writel | |
186 | ||
5e78a264 CG |
187 | #define mmiowb() |
188 | ||
013bf24c RK |
189 | /* |
190 | * Need an mtype somewhere in here, for cache type deals? | |
191 | * This is probably too long for an inline. | |
192 | */ | |
193 | void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size); | |
194 | ||
195 | static inline void __iomem *ioremap(unsigned long phys_addr, unsigned long size) | |
196 | { | |
197 | return ioremap_nocache(phys_addr, size); | |
198 | } | |
199 | ||
200 | static inline void iounmap(volatile void __iomem *addr) | |
201 | { | |
202 | __iounmap(addr); | |
203 | } | |
204 | ||
205 | #define __raw_writel writel | |
206 | ||
207 | static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, | |
208 | int count) | |
209 | { | |
210 | memcpy(dst, (void *) src, count); | |
211 | } | |
212 | ||
213 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, | |
214 | int count) | |
215 | { | |
216 | memcpy((void *) dst, src, count); | |
217 | } | |
218 | ||
219 | #define PCI_IO_ADDR (volatile void __iomem *) | |
220 | ||
221 | /* | |
222 | * inb - read byte from I/O port or something | |
223 | * @port: address in I/O space | |
224 | * | |
225 | * Operates on "I/O bus I/O space" | |
226 | */ | |
227 | static inline u8 inb(unsigned long port) | |
228 | { | |
229 | return readb(_IO_BASE + (port & IO_SPACE_LIMIT)); | |
230 | } | |
231 | ||
232 | static inline u16 inw(unsigned long port) | |
233 | { | |
234 | return readw(_IO_BASE + (port & IO_SPACE_LIMIT)); | |
235 | } | |
236 | ||
237 | static inline u32 inl(unsigned long port) | |
238 | { | |
239 | return readl(_IO_BASE + (port & IO_SPACE_LIMIT)); | |
240 | } | |
241 | ||
242 | /* | |
243 | * outb - write a byte to a memory location | |
244 | * @data: data to write to | |
245 | * @addr: address in I/O space | |
246 | */ | |
247 | static inline void outb(u8 data, unsigned long port) | |
248 | { | |
249 | writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT)); | |
250 | } | |
251 | ||
252 | static inline void outw(u16 data, unsigned long port) | |
253 | { | |
254 | writew(data, _IO_BASE + (port & IO_SPACE_LIMIT)); | |
255 | } | |
256 | ||
257 | static inline void outl(u32 data, unsigned long port) | |
258 | { | |
259 | writel(data, _IO_BASE + (port & IO_SPACE_LIMIT)); | |
260 | } | |
261 | ||
262 | #define outb_p outb | |
263 | #define outw_p outw | |
264 | #define outl_p outl | |
265 | ||
266 | #define inb_p inb | |
267 | #define inw_p inw | |
268 | #define inl_p inl | |
269 | ||
270 | static inline void insb(unsigned long port, void *buffer, int count) | |
271 | { | |
272 | if (count) { | |
273 | u8 *buf = buffer; | |
274 | do { | |
275 | u8 x = inb(port); | |
276 | *buf++ = x; | |
277 | } while (--count); | |
278 | } | |
279 | } | |
280 | ||
281 | static inline void insw(unsigned long port, void *buffer, int count) | |
282 | { | |
283 | if (count) { | |
284 | u16 *buf = buffer; | |
285 | do { | |
286 | u16 x = inw(port); | |
287 | *buf++ = x; | |
288 | } while (--count); | |
289 | } | |
290 | } | |
291 | ||
292 | static inline void insl(unsigned long port, void *buffer, int count) | |
293 | { | |
294 | if (count) { | |
295 | u32 *buf = buffer; | |
296 | do { | |
297 | u32 x = inw(port); | |
298 | *buf++ = x; | |
299 | } while (--count); | |
300 | } | |
301 | } | |
302 | ||
303 | static inline void outsb(unsigned long port, const void *buffer, int count) | |
304 | { | |
305 | if (count) { | |
306 | const u8 *buf = buffer; | |
307 | do { | |
308 | outb(*buf++, port); | |
309 | } while (--count); | |
310 | } | |
311 | } | |
312 | ||
313 | static inline void outsw(unsigned long port, const void *buffer, int count) | |
314 | { | |
315 | if (count) { | |
316 | const u16 *buf = buffer; | |
317 | do { | |
318 | outw(*buf++, port); | |
319 | } while (--count); | |
320 | } | |
321 | } | |
322 | ||
323 | static inline void outsl(unsigned long port, const void *buffer, int count) | |
324 | { | |
325 | if (count) { | |
326 | const u32 *buf = buffer; | |
327 | do { | |
328 | outl(*buf++, port); | |
329 | } while (--count); | |
330 | } | |
331 | } | |
332 | ||
333 | #define flush_write_buffers() do { } while (0) | |
334 | ||
335 | #endif /* __KERNEL__ */ | |
336 | ||
337 | #endif |