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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/smp_lock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/mc146818rtc.h> | |
25 | #include <linux/kernel_stat.h> | |
26 | #include <linux/sysdev.h> | |
f3705136 | 27 | #include <linux/cpu.h> |
e9e2cdb4 | 28 | #include <linux/clockchips.h> |
d36b49b9 | 29 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 30 | #include <linux/module.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 LT |
45 | |
46 | #include "io_ports.h" | |
47 | ||
e05d723f TG |
48 | /* |
49 | * Sanity check | |
50 | */ | |
51 | #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F | |
52 | # error SPURIOUS_APIC_VECTOR definition error | |
53 | #endif | |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f TG |
57 | * |
58 | * -1=force-disable, +1=force-enable | |
9635b47d | 59 | */ |
e05d723f | 60 | static int enable_local_apic __initdata = 0; |
9635b47d | 61 | |
d36b49b9 TG |
62 | /* Local APIC timer verification ok */ |
63 | static int local_apic_timer_verify_ok; | |
e9e2cdb4 | 64 | |
1da177e4 | 65 | /* |
e05d723f | 66 | * Debug level, exported for io_apic.c |
1da177e4 LT |
67 | */ |
68 | int apic_verbosity; | |
69 | ||
e9e2cdb4 | 70 | static unsigned int calibration_result; |
1da177e4 | 71 | |
e9e2cdb4 TG |
72 | static int lapic_next_event(unsigned long delta, |
73 | struct clock_event_device *evt); | |
74 | static void lapic_timer_setup(enum clock_event_mode mode, | |
75 | struct clock_event_device *evt); | |
76 | static void lapic_timer_broadcast(cpumask_t mask); | |
77 | static void apic_pm_activate(void); | |
e05d723f | 78 | |
e9e2cdb4 TG |
79 | /* |
80 | * The local apic timer can be used for any function which is CPU local. | |
81 | */ | |
82 | static struct clock_event_device lapic_clockevent = { | |
83 | .name = "lapic", | |
84 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 85 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
86 | .shift = 32, |
87 | .set_mode = lapic_timer_setup, | |
88 | .set_next_event = lapic_next_event, | |
89 | .broadcast = lapic_timer_broadcast, | |
90 | .rating = 100, | |
91 | .irq = -1, | |
92 | }; | |
93 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
94 | |
95 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
96 | static int enabled_via_apicbase; | |
97 | ||
98 | /* | |
99 | * Get the LAPIC version | |
100 | */ | |
101 | static inline int lapic_get_version(void) | |
95d769aa | 102 | { |
e05d723f | 103 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
104 | } |
105 | ||
1da177e4 | 106 | /* |
e05d723f | 107 | * Check, if the APIC is integrated or a seperate chip |
1da177e4 | 108 | */ |
e05d723f | 109 | static inline int lapic_is_integrated(void) |
1da177e4 | 110 | { |
e05d723f | 111 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
112 | } |
113 | ||
e05d723f TG |
114 | /* |
115 | * Check, whether this is a modern or a first generation APIC | |
116 | */ | |
117 | static int modern_apic(void) | |
1da177e4 | 118 | { |
e05d723f TG |
119 | /* AMD systems use old APIC versions, so check the CPU */ |
120 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
121 | boot_cpu_data.x86 >= 0xf) | |
122 | return 1; | |
123 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
124 | } |
125 | ||
e05d723f TG |
126 | /** |
127 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
128 | */ | |
1da177e4 LT |
129 | void enable_NMI_through_LVT0 (void * dummy) |
130 | { | |
e05d723f | 131 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 132 | |
e05d723f TG |
133 | /* Level triggered for 82489DX */ |
134 | if (!lapic_is_integrated()) | |
1da177e4 LT |
135 | v |= APIC_LVT_LEVEL_TRIGGER; |
136 | apic_write_around(APIC_LVT0, v); | |
137 | } | |
138 | ||
e05d723f TG |
139 | /** |
140 | * get_physical_broadcast - Get number of physical broadcast IDs | |
141 | */ | |
1da177e4 LT |
142 | int get_physical_broadcast(void) |
143 | { | |
e05d723f | 144 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
145 | } |
146 | ||
e05d723f TG |
147 | /** |
148 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
149 | */ | |
150 | int lapic_get_maxlvt(void) | |
1da177e4 | 151 | { |
e05d723f | 152 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 153 | |
1da177e4 | 154 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 155 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
156 | } |
157 | ||
e05d723f TG |
158 | /* |
159 | * Local APIC timer | |
160 | */ | |
161 | ||
d36b49b9 TG |
162 | /* Clock divisor is set to 16 */ |
163 | #define APIC_DIVISOR 16 | |
e05d723f TG |
164 | |
165 | /* | |
166 | * This function sets up the local APIC timer, with a timeout of | |
167 | * 'clocks' APIC bus clock. During calibration we actually call | |
168 | * this function twice on the boot CPU, once with a bogus timeout | |
169 | * value, second time for real. The other (noncalibrating) CPUs | |
170 | * call this function only once, with the real, calibrated value. | |
171 | * | |
172 | * We do reads before writes even if unnecessary, to get around the | |
173 | * P5 APIC double write bug. | |
174 | */ | |
e9e2cdb4 | 175 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 176 | { |
e05d723f | 177 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 178 | |
e9e2cdb4 TG |
179 | lvtt_value = LOCAL_TIMER_VECTOR; |
180 | if (!oneshot) | |
181 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
182 | if (!lapic_is_integrated()) |
183 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
184 | ||
e9e2cdb4 | 185 | if (!irqen) |
e05d723f TG |
186 | lvtt_value |= APIC_LVT_MASKED; |
187 | ||
188 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
189 | |
190 | /* | |
e05d723f | 191 | * Divide PICLK by 16 |
1da177e4 | 192 | */ |
e05d723f TG |
193 | tmp_value = apic_read(APIC_TDCR); |
194 | apic_write_around(APIC_TDCR, (tmp_value | |
195 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
196 | | APIC_TDR_DIV_16); | |
1da177e4 | 197 | |
e9e2cdb4 TG |
198 | if (!oneshot) |
199 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
200 | } | |
201 | ||
202 | /* | |
203 | * Program the next event, relative to now | |
204 | */ | |
205 | static int lapic_next_event(unsigned long delta, | |
206 | struct clock_event_device *evt) | |
207 | { | |
208 | apic_write_around(APIC_TMICT, delta); | |
209 | return 0; | |
1da177e4 LT |
210 | } |
211 | ||
e9e2cdb4 TG |
212 | /* |
213 | * Setup the lapic timer in periodic or oneshot mode | |
214 | */ | |
215 | static void lapic_timer_setup(enum clock_event_mode mode, | |
216 | struct clock_event_device *evt) | |
1da177e4 | 217 | { |
e05d723f | 218 | unsigned long flags; |
e9e2cdb4 | 219 | unsigned int v; |
e05d723f | 220 | |
d36b49b9 TG |
221 | /* Lapic used for broadcast ? */ |
222 | if (!local_apic_timer_verify_ok) | |
223 | return; | |
224 | ||
e05d723f | 225 | local_irq_save(flags); |
1da177e4 | 226 | |
e9e2cdb4 TG |
227 | switch (mode) { |
228 | case CLOCK_EVT_MODE_PERIODIC: | |
229 | case CLOCK_EVT_MODE_ONESHOT: | |
230 | __setup_APIC_LVTT(calibration_result, | |
231 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
232 | break; | |
233 | case CLOCK_EVT_MODE_UNUSED: | |
234 | case CLOCK_EVT_MODE_SHUTDOWN: | |
235 | v = apic_read(APIC_LVTT); | |
236 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
237 | apic_write_around(APIC_LVTT, v); | |
238 | break; | |
239 | } | |
e05d723f TG |
240 | |
241 | local_irq_restore(flags); | |
242 | } | |
243 | ||
e9e2cdb4 TG |
244 | /* |
245 | * Local APIC timer broadcast function | |
246 | */ | |
247 | static void lapic_timer_broadcast(cpumask_t mask) | |
248 | { | |
249 | #ifdef CONFIG_SMP | |
250 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
251 | #endif | |
252 | } | |
253 | ||
254 | /* | |
255 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
256 | * of the boot CPU and register the clock event in the framework. | |
257 | */ | |
258 | static void __devinit setup_APIC_timer(void) | |
259 | { | |
260 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
261 | ||
262 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
263 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
264 | ||
265 | clockevents_register_device(levt); | |
266 | } | |
267 | ||
e05d723f | 268 | /* |
d36b49b9 TG |
269 | * In this functions we calibrate APIC bus clocks to the external timer. |
270 | * | |
271 | * We want to do the calibration only once since we want to have local timer | |
272 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
273 | * frequency. | |
274 | * | |
275 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
276 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
277 | * readout is broken, so it never gets out of the wait loop again. This was | |
278 | * also reported by others. | |
e05d723f | 279 | * |
d36b49b9 TG |
280 | * Monitoring the jiffies value is inaccurate and the clockevents |
281 | * infrastructure allows us to do a simple substitution of the interrupt | |
282 | * handler. | |
e9e2cdb4 | 283 | * |
d36b49b9 TG |
284 | * The calibration routine also uses the pm_timer when possible, as the PIT |
285 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
286 | * back to normal later in the boot process). | |
e05d723f TG |
287 | */ |
288 | ||
d36b49b9 | 289 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 290 | |
d36b49b9 TG |
291 | static __initdata volatile int lapic_cal_loops = -1; |
292 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
293 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
294 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
295 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 296 | |
d36b49b9 TG |
297 | /* |
298 | * Temporary interrupt handler. | |
299 | */ | |
300 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
301 | { | |
302 | unsigned long long tsc = 0; | |
303 | long tapic = apic_read(APIC_TMCCT); | |
304 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 305 | |
d36b49b9 TG |
306 | if (cpu_has_tsc) |
307 | rdtscll(tsc); | |
308 | ||
309 | switch (lapic_cal_loops++) { | |
310 | case 0: | |
311 | lapic_cal_t1 = tapic; | |
312 | lapic_cal_tsc1 = tsc; | |
313 | lapic_cal_pm1 = pm; | |
314 | lapic_cal_j1 = jiffies; | |
315 | break; | |
e05d723f | 316 | |
d36b49b9 TG |
317 | case LAPIC_CAL_LOOPS: |
318 | lapic_cal_t2 = tapic; | |
319 | lapic_cal_tsc2 = tsc; | |
320 | if (pm < lapic_cal_pm1) | |
321 | pm += ACPI_PM_OVRRUN; | |
322 | lapic_cal_pm2 = pm; | |
323 | lapic_cal_j2 = jiffies; | |
324 | break; | |
325 | } | |
326 | } | |
1da177e4 | 327 | |
d36b49b9 TG |
328 | /* |
329 | * Setup the boot APIC | |
330 | * | |
331 | * Calibrate and verify the result. | |
332 | */ | |
333 | void __init setup_boot_APIC_clock(void) | |
334 | { | |
335 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
336 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
337 | const long pm_thresh = pm_100ms/100; | |
338 | void (*real_handler)(struct clock_event_device *dev); | |
339 | unsigned long deltaj; | |
340 | long delta, deltapm; | |
1da177e4 | 341 | |
d36b49b9 TG |
342 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
343 | "calibrating APIC timer ...\n"); | |
1da177e4 | 344 | |
d36b49b9 TG |
345 | local_irq_disable(); |
346 | ||
347 | /* Replace the global interrupt handler */ | |
348 | real_handler = global_clock_event->event_handler; | |
349 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 350 | |
1da177e4 | 351 | /* |
d36b49b9 TG |
352 | * Setup the APIC counter to 1e9. There is no way the lapic |
353 | * can underflow in the 100ms detection time frame | |
1da177e4 | 354 | */ |
d36b49b9 | 355 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 356 | |
d36b49b9 TG |
357 | /* Let the interrupts run */ |
358 | local_irq_enable(); | |
359 | ||
360 | while(lapic_cal_loops <= LAPIC_CAL_LOOPS); | |
361 | ||
362 | local_irq_disable(); | |
363 | ||
364 | /* Restore the real event handler */ | |
365 | global_clock_event->event_handler = real_handler; | |
366 | ||
367 | /* Build delta t1-t2 as apic timer counts down */ | |
368 | delta = lapic_cal_t1 - lapic_cal_t2; | |
369 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
370 | ||
371 | /* Check, if the PM timer is available */ | |
372 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
373 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
374 | ||
375 | if (deltapm) { | |
376 | unsigned long mult; | |
377 | u64 res; | |
378 | ||
379 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
380 | ||
381 | if (deltapm > (pm_100ms - pm_thresh) && | |
382 | deltapm < (pm_100ms + pm_thresh)) { | |
383 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
384 | } else { | |
385 | res = (((u64) deltapm) * mult) >> 22; | |
386 | do_div(res, 1000000); | |
387 | printk(KERN_WARNING "APIC calibration not consistent " | |
388 | "with PM Timer: %ldms instead of 100ms\n", | |
389 | (long)res); | |
390 | /* Correct the lapic counter value */ | |
391 | res = (((u64) delta ) * pm_100ms); | |
392 | do_div(res, deltapm); | |
393 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
394 | "%lu (%ld)\n", (unsigned long) res, delta); | |
395 | delta = (long) res; | |
396 | } | |
397 | } | |
e05d723f | 398 | |
e9e2cdb4 | 399 | /* Calculate the scaled math multiplication factor */ |
d36b49b9 | 400 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32); |
e9e2cdb4 TG |
401 | lapic_clockevent.max_delta_ns = |
402 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
403 | lapic_clockevent.min_delta_ns = | |
404 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
405 | ||
d36b49b9 TG |
406 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
407 | ||
408 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 409 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
410 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
411 | calibration_result); | |
e9e2cdb4 | 412 | |
d36b49b9 TG |
413 | if (cpu_has_tsc) { |
414 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 415 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
416 | "%ld.%04ld MHz.\n", |
417 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
418 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
419 | } | |
e05d723f TG |
420 | |
421 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
422 | "%u.%04u MHz.\n", |
423 | calibration_result / (1000000 / HZ), | |
424 | calibration_result % (1000000 / HZ)); | |
e05d723f | 425 | |
1da177e4 | 426 | |
d36b49b9 | 427 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
e05d723f | 428 | |
1da177e4 | 429 | /* |
d36b49b9 | 430 | * Setup the apic timer manually |
1da177e4 | 431 | */ |
d36b49b9 TG |
432 | local_apic_timer_verify_ok = 1; |
433 | levt->event_handler = lapic_cal_handler; | |
434 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
435 | lapic_cal_loops = -1; | |
436 | ||
437 | /* Let the interrupts run */ | |
438 | local_irq_enable(); | |
439 | ||
440 | while(lapic_cal_loops <= LAPIC_CAL_LOOPS); | |
441 | ||
442 | local_irq_disable(); | |
443 | ||
444 | /* Stop the lapic timer */ | |
445 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
446 | ||
447 | local_irq_enable(); | |
448 | ||
449 | /* Jiffies delta */ | |
450 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
451 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
452 | ||
453 | /* Check, if the PM timer is available */ | |
454 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
455 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
456 | ||
457 | local_apic_timer_verify_ok = 0; | |
458 | ||
459 | if (deltapm) { | |
460 | if (deltapm > (pm_100ms - pm_thresh) && | |
461 | deltapm < (pm_100ms + pm_thresh)) { | |
462 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
463 | /* Check, if the jiffies result is consistent */ | |
464 | if (deltaj < LAPIC_CAL_LOOPS-2 || | |
465 | deltaj > LAPIC_CAL_LOOPS+2) { | |
466 | /* | |
467 | * Not sure, what we can do about this one. | |
468 | * When high resultion timers are active | |
469 | * and the lapic timer does not stop in C3 | |
470 | * we are fine. Otherwise more trouble might | |
471 | * be waiting. -- tglx | |
472 | */ | |
473 | printk(KERN_WARNING "Global event device %s " | |
474 | "has wrong frequency " | |
475 | "(%lu ticks instead of %d)\n", | |
476 | global_clock_event->name, deltaj, | |
477 | LAPIC_CAL_LOOPS); | |
478 | } | |
479 | local_apic_timer_verify_ok = 1; | |
480 | } | |
481 | } else { | |
482 | /* Check, if the jiffies result is consistent */ | |
483 | if (deltaj >= LAPIC_CAL_LOOPS-2 && | |
484 | deltaj <= LAPIC_CAL_LOOPS+2) { | |
485 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
486 | local_apic_timer_verify_ok = 1; | |
487 | } | |
488 | } | |
e05d723f | 489 | |
d36b49b9 TG |
490 | if (!local_apic_timer_verify_ok) { |
491 | printk(KERN_WARNING | |
492 | "APIC timer disabled due to verification failure.\n"); | |
493 | /* No broadcast on UP ! */ | |
494 | if (num_possible_cpus() == 1) | |
495 | return; | |
a5f5e43e TG |
496 | } else { |
497 | /* | |
498 | * If nmi_watchdog is set to IO_APIC, we need the | |
499 | * PIT/HPET going. Otherwise register lapic as a dummy | |
500 | * device. | |
501 | */ | |
502 | if (nmi_watchdog != NMI_IO_APIC) | |
503 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
504 | } | |
d36b49b9 TG |
505 | |
506 | /* Setup the lapic or request the broadcast */ | |
507 | setup_APIC_timer(); | |
e05d723f | 508 | } |
1da177e4 | 509 | |
e05d723f TG |
510 | void __devinit setup_secondary_APIC_clock(void) |
511 | { | |
e9e2cdb4 | 512 | setup_APIC_timer(); |
e05d723f | 513 | } |
1da177e4 | 514 | |
e05d723f | 515 | /* |
e9e2cdb4 | 516 | * The guts of the apic timer interrupt |
e05d723f | 517 | */ |
e9e2cdb4 | 518 | static void local_apic_timer_interrupt(void) |
e05d723f | 519 | { |
e9e2cdb4 TG |
520 | int cpu = smp_processor_id(); |
521 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
522 | |
523 | /* | |
d36b49b9 TG |
524 | * Normally we should not be here till LAPIC has been initialized but |
525 | * in some cases like kdump, its possible that there is a pending LAPIC | |
526 | * timer interrupt from previous kernel's context and is delivered in | |
527 | * new kernel the moment interrupts are enabled. | |
e05d723f | 528 | * |
d36b49b9 TG |
529 | * Interrupts are enabled early and LAPIC is setup much later, hence |
530 | * its possible that when we get here evt->event_handler is NULL. | |
531 | * Check for event_handler being NULL and discard the interrupt as | |
532 | * spurious. | |
1da177e4 | 533 | */ |
e9e2cdb4 TG |
534 | if (!evt->event_handler) { |
535 | printk(KERN_WARNING | |
536 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
537 | /* Switch it off */ | |
538 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
539 | return; | |
540 | } | |
541 | ||
542 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
543 | ||
544 | evt->event_handler(evt); | |
e05d723f TG |
545 | } |
546 | ||
547 | /* | |
548 | * Local APIC timer interrupt. This is the most natural way for doing | |
549 | * local interrupts, but local timer interrupts can be emulated by | |
550 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
551 | * | |
552 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
553 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
554 | */ | |
555 | ||
e9e2cdb4 | 556 | void fastcall smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
557 | { |
558 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
559 | |
560 | /* | |
e05d723f TG |
561 | * NOTE! We'd better ACK the irq immediately, |
562 | * because timer handling can be slow. | |
1da177e4 | 563 | */ |
e05d723f | 564 | ack_APIC_irq(); |
1a75a3f0 | 565 | /* |
e05d723f TG |
566 | * update_process_times() expects us to have done irq_enter(). |
567 | * Besides, if we don't timer interrupts ignore the global | |
568 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 569 | */ |
e05d723f | 570 | irq_enter(); |
e9e2cdb4 | 571 | local_apic_timer_interrupt(); |
e05d723f | 572 | irq_exit(); |
1a75a3f0 | 573 | |
e9e2cdb4 | 574 | set_irq_regs(old_regs); |
e05d723f TG |
575 | } |
576 | ||
577 | int setup_profiling_timer(unsigned int multiplier) | |
578 | { | |
579 | return -EINVAL; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Local APIC start and shutdown | |
584 | */ | |
585 | ||
586 | /** | |
587 | * clear_local_APIC - shutdown the local APIC | |
588 | * | |
589 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
590 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
591 | * leftovers during boot. | |
592 | */ | |
593 | void clear_local_APIC(void) | |
594 | { | |
595 | int maxlvt = lapic_get_maxlvt(); | |
596 | unsigned long v; | |
1da177e4 LT |
597 | |
598 | /* | |
e05d723f TG |
599 | * Masking an LVT entry can trigger a local APIC error |
600 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 601 | */ |
e05d723f TG |
602 | if (maxlvt >= 3) { |
603 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
604 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
605 | } | |
1da177e4 | 606 | /* |
e05d723f TG |
607 | * Careful: we have to set masks only first to deassert |
608 | * any level-triggered sources. | |
1da177e4 | 609 | */ |
e05d723f TG |
610 | v = apic_read(APIC_LVTT); |
611 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
612 | v = apic_read(APIC_LVT0); | |
613 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
614 | v = apic_read(APIC_LVT1); | |
615 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
616 | if (maxlvt >= 4) { | |
617 | v = apic_read(APIC_LVTPC); | |
618 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 619 | } |
1da177e4 | 620 | |
e05d723f TG |
621 | /* lets not touch this if we didn't frob it */ |
622 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
623 | if (maxlvt >= 5) { | |
624 | v = apic_read(APIC_LVTTHMR); | |
625 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
626 | } | |
627 | #endif | |
1da177e4 | 628 | /* |
e05d723f | 629 | * Clean APIC state for other OSs: |
1da177e4 | 630 | */ |
e05d723f TG |
631 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
632 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
633 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
634 | if (maxlvt >= 3) | |
635 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
636 | if (maxlvt >= 4) | |
637 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 638 | |
e05d723f TG |
639 | #ifdef CONFIG_X86_MCE_P4THERMAL |
640 | if (maxlvt >= 5) | |
641 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
642 | #endif | |
643 | /* Integrated APIC (!82489DX) ? */ | |
644 | if (lapic_is_integrated()) { | |
1da177e4 | 645 | if (maxlvt > 3) |
e05d723f | 646 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 647 | apic_write(APIC_ESR, 0); |
e05d723f | 648 | apic_read(APIC_ESR); |
1da177e4 | 649 | } |
e05d723f | 650 | } |
1da177e4 | 651 | |
e05d723f TG |
652 | /** |
653 | * disable_local_APIC - clear and disable the local APIC | |
654 | */ | |
655 | void disable_local_APIC(void) | |
656 | { | |
657 | unsigned long value; | |
658 | ||
659 | clear_local_APIC(); | |
660 | ||
661 | /* | |
662 | * Disable APIC (implies clearing of registers | |
663 | * for 82489DX!). | |
664 | */ | |
665 | value = apic_read(APIC_SPIV); | |
666 | value &= ~APIC_SPIV_APIC_ENABLED; | |
667 | apic_write_around(APIC_SPIV, value); | |
668 | ||
669 | /* | |
670 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
671 | * restore the disabled state. | |
672 | */ | |
673 | if (enabled_via_apicbase) { | |
674 | unsigned int l, h; | |
675 | ||
676 | rdmsr(MSR_IA32_APICBASE, l, h); | |
677 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
678 | wrmsr(MSR_IA32_APICBASE, l, h); | |
679 | } | |
1da177e4 LT |
680 | } |
681 | ||
682 | /* | |
e05d723f TG |
683 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
684 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
685 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 686 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
687 | */ |
688 | void lapic_shutdown(void) | |
689 | { | |
67963132 MS |
690 | unsigned long flags; |
691 | ||
77f72b19 | 692 | if (!cpu_has_apic) |
1da177e4 LT |
693 | return; |
694 | ||
67963132 | 695 | local_irq_save(flags); |
77f72b19 ZM |
696 | clear_local_APIC(); |
697 | ||
698 | if (enabled_via_apicbase) | |
699 | disable_local_APIC(); | |
700 | ||
67963132 | 701 | local_irq_restore(flags); |
1da177e4 LT |
702 | } |
703 | ||
e05d723f TG |
704 | /* |
705 | * This is to verify that we're looking at a real local APIC. | |
706 | * Check these against your board if the CPUs aren't getting | |
707 | * started for no apparent reason. | |
708 | */ | |
709 | int __init verify_local_APIC(void) | |
1da177e4 | 710 | { |
e05d723f | 711 | unsigned int reg0, reg1; |
1da177e4 | 712 | |
e05d723f TG |
713 | /* |
714 | * The version register is read-only in a real APIC. | |
715 | */ | |
716 | reg0 = apic_read(APIC_LVR); | |
717 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
718 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
719 | reg1 = apic_read(APIC_LVR); | |
720 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
721 | ||
722 | /* | |
723 | * The two version reads above should print the same | |
724 | * numbers. If the second one is different, then we | |
725 | * poke at a non-APIC. | |
726 | */ | |
727 | if (reg1 != reg0) | |
1da177e4 LT |
728 | return 0; |
729 | ||
e05d723f TG |
730 | /* |
731 | * Check if the version looks reasonably. | |
732 | */ | |
733 | reg1 = GET_APIC_VERSION(reg0); | |
734 | if (reg1 == 0x00 || reg1 == 0xff) | |
735 | return 0; | |
736 | reg1 = lapic_get_maxlvt(); | |
737 | if (reg1 < 0x02 || reg1 == 0xff) | |
738 | return 0; | |
f990fff4 | 739 | |
e05d723f TG |
740 | /* |
741 | * The ID register is read/write in a real APIC. | |
742 | */ | |
743 | reg0 = apic_read(APIC_ID); | |
744 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
745 | ||
746 | /* | |
747 | * The next two are just to see if we have sane values. | |
748 | * They're only really relevant if we're in Virtual Wire | |
749 | * compatibility mode, but most boxes are anymore. | |
750 | */ | |
751 | reg0 = apic_read(APIC_LVT0); | |
752 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
753 | reg1 = apic_read(APIC_LVT1); | |
754 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
755 | ||
756 | return 1; | |
1da177e4 LT |
757 | } |
758 | ||
e05d723f TG |
759 | /** |
760 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
761 | */ | |
762 | void __init sync_Arb_IDs(void) | |
1da177e4 | 763 | { |
e05d723f TG |
764 | /* |
765 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
766 | * needed on AMD. | |
767 | */ | |
768 | if (modern_apic()) | |
769 | return; | |
770 | /* | |
771 | * Wait for idle. | |
772 | */ | |
773 | apic_wait_icr_idle(); | |
1da177e4 | 774 | |
e05d723f TG |
775 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
776 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
777 | | APIC_DM_INIT); | |
778 | } | |
1da177e4 | 779 | |
e05d723f TG |
780 | /* |
781 | * An initial setup of the virtual wire mode. | |
782 | */ | |
783 | void __init init_bsp_APIC(void) | |
784 | { | |
785 | unsigned long value; | |
f990fff4 | 786 | |
e05d723f TG |
787 | /* |
788 | * Don't do the setup now if we have a SMP BIOS as the | |
789 | * through-I/O-APIC virtual wire mode might be active. | |
790 | */ | |
791 | if (smp_found_config || !cpu_has_apic) | |
792 | return; | |
1da177e4 LT |
793 | |
794 | /* | |
e05d723f | 795 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 796 | */ |
e05d723f | 797 | clear_local_APIC(); |
1da177e4 | 798 | |
e05d723f TG |
799 | /* |
800 | * Enable APIC. | |
801 | */ | |
802 | value = apic_read(APIC_SPIV); | |
803 | value &= ~APIC_VECTOR_MASK; | |
804 | value |= APIC_SPIV_APIC_ENABLED; | |
805 | ||
806 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
807 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
808 | (boot_cpu_data.x86 == 15)) | |
809 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
810 | else | |
811 | value |= APIC_SPIV_FOCUS_DISABLED; | |
812 | value |= SPURIOUS_APIC_VECTOR; | |
813 | apic_write_around(APIC_SPIV, value); | |
814 | ||
815 | /* | |
816 | * Set up the virtual wire mode. | |
817 | */ | |
818 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
819 | value = APIC_DM_NMI; | |
820 | if (!lapic_is_integrated()) /* 82489DX */ | |
821 | value |= APIC_LVT_LEVEL_TRIGGER; | |
822 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
823 | } |
824 | ||
e05d723f TG |
825 | /** |
826 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 827 | */ |
e05d723f TG |
828 | void __devinit setup_local_APIC(void) |
829 | { | |
830 | unsigned long oldvalue, value, maxlvt, integrated; | |
831 | int i, j; | |
1da177e4 | 832 | |
e05d723f TG |
833 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
834 | if (esr_disable) { | |
835 | apic_write(APIC_ESR, 0); | |
836 | apic_write(APIC_ESR, 0); | |
837 | apic_write(APIC_ESR, 0); | |
838 | apic_write(APIC_ESR, 0); | |
839 | } | |
1da177e4 | 840 | |
e05d723f | 841 | integrated = lapic_is_integrated(); |
1da177e4 | 842 | |
e05d723f TG |
843 | /* |
844 | * Double-check whether this APIC is really registered. | |
845 | */ | |
846 | if (!apic_id_registered()) | |
847 | BUG(); | |
1da177e4 | 848 | |
e05d723f TG |
849 | /* |
850 | * Intel recommends to set DFR, LDR and TPR before enabling | |
851 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
852 | * document number 292116). So here it goes... | |
853 | */ | |
854 | init_apic_ldr(); | |
1da177e4 | 855 | |
e05d723f TG |
856 | /* |
857 | * Set Task Priority to 'accept all'. We never change this | |
858 | * later on. | |
859 | */ | |
860 | value = apic_read(APIC_TASKPRI); | |
861 | value &= ~APIC_TPRI_MASK; | |
862 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 863 | |
e05d723f TG |
864 | /* |
865 | * After a crash, we no longer service the interrupts and a pending | |
866 | * interrupt from previous kernel might still have ISR bit set. | |
867 | * | |
868 | * Most probably by now CPU has serviced that pending interrupt and | |
869 | * it might not have done the ack_APIC_irq() because it thought, | |
870 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
871 | * does not clear the ISR bit and cpu thinks it has already serivced | |
872 | * the interrupt. Hence a vector might get locked. It was noticed | |
873 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
874 | */ | |
875 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
876 | value = apic_read(APIC_ISR + i*0x10); | |
877 | for (j = 31; j >= 0; j--) { | |
878 | if (value & (1<<j)) | |
879 | ack_APIC_irq(); | |
880 | } | |
881 | } | |
1da177e4 | 882 | |
e05d723f TG |
883 | /* |
884 | * Now that we are all set up, enable the APIC | |
885 | */ | |
886 | value = apic_read(APIC_SPIV); | |
887 | value &= ~APIC_VECTOR_MASK; | |
888 | /* | |
889 | * Enable APIC | |
890 | */ | |
891 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 892 | |
e05d723f TG |
893 | /* |
894 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
895 | * certain networking cards. If high frequency interrupts are | |
896 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
897 | * entry is masked/unmasked at a high rate as well then sooner or | |
898 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
899 | * from the device. If focus CPU is disabled then the hang goes | |
900 | * away, oh well :-( | |
901 | * | |
902 | * [ This bug can be reproduced easily with a level-triggered | |
903 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
904 | * BX chipset. ] | |
905 | */ | |
906 | /* | |
907 | * Actually disabling the focus CPU check just makes the hang less | |
908 | * frequent as it makes the interrupt distributon model be more | |
909 | * like LRU than MRU (the short-term load is more even across CPUs). | |
910 | * See also the comment in end_level_ioapic_irq(). --macro | |
911 | */ | |
1da177e4 | 912 | |
e05d723f TG |
913 | /* Enable focus processor (bit==0) */ |
914 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 915 | |
e05d723f TG |
916 | /* |
917 | * Set spurious IRQ vector | |
918 | */ | |
919 | value |= SPURIOUS_APIC_VECTOR; | |
920 | apic_write_around(APIC_SPIV, value); | |
921 | ||
922 | /* | |
923 | * Set up LVT0, LVT1: | |
924 | * | |
925 | * set up through-local-APIC on the BP's LINT0. This is not | |
926 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
927 | * we delegate interrupts to the 8259A. | |
928 | */ | |
929 | /* | |
930 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
931 | */ | |
932 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
933 | if (!smp_processor_id() && (pic_mode || !value)) { | |
934 | value = APIC_DM_EXTINT; | |
935 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
936 | smp_processor_id()); | |
937 | } else { | |
938 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
939 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
940 | smp_processor_id()); | |
941 | } | |
942 | apic_write_around(APIC_LVT0, value); | |
943 | ||
944 | /* | |
945 | * only the BP should see the LINT1 NMI signal, obviously. | |
946 | */ | |
947 | if (!smp_processor_id()) | |
948 | value = APIC_DM_NMI; | |
949 | else | |
950 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
951 | if (!integrated) /* 82489DX */ | |
952 | value |= APIC_LVT_LEVEL_TRIGGER; | |
953 | apic_write_around(APIC_LVT1, value); | |
954 | ||
955 | if (integrated && !esr_disable) { /* !82489DX */ | |
956 | maxlvt = lapic_get_maxlvt(); | |
957 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
958 | apic_write(APIC_ESR, 0); | |
959 | oldvalue = apic_read(APIC_ESR); | |
960 | ||
961 | /* enables sending errors */ | |
962 | value = ERROR_APIC_VECTOR; | |
963 | apic_write_around(APIC_LVTERR, value); | |
964 | /* | |
965 | * spec says clear errors after enabling vector. | |
966 | */ | |
967 | if (maxlvt > 3) | |
968 | apic_write(APIC_ESR, 0); | |
969 | value = apic_read(APIC_ESR); | |
970 | if (value != oldvalue) | |
971 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
972 | "vector: 0x%08lx after: 0x%08lx\n", | |
973 | oldvalue, value); | |
974 | } else { | |
975 | if (esr_disable) | |
976 | /* | |
977 | * Something untraceble is creating bad interrupts on | |
978 | * secondary quads ... for the moment, just leave the | |
979 | * ESR disabled - we can't do anything useful with the | |
980 | * errors anyway - mbligh | |
981 | */ | |
982 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
983 | else | |
984 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
985 | } | |
1da177e4 | 986 | |
e9e2cdb4 TG |
987 | /* Disable the local apic timer */ |
988 | value = apic_read(APIC_LVTT); | |
989 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
990 | apic_write_around(APIC_LVTT, value); | |
991 | ||
e05d723f TG |
992 | setup_apic_nmi_watchdog(NULL); |
993 | apic_pm_activate(); | |
1da177e4 LT |
994 | } |
995 | ||
e05d723f TG |
996 | /* |
997 | * Detect and initialize APIC | |
998 | */ | |
1da177e4 LT |
999 | static int __init detect_init_APIC (void) |
1000 | { | |
1001 | u32 h, l, features; | |
1da177e4 LT |
1002 | |
1003 | /* Disabled by kernel option? */ | |
1004 | if (enable_local_apic < 0) | |
1005 | return -1; | |
1006 | ||
1da177e4 LT |
1007 | switch (boot_cpu_data.x86_vendor) { |
1008 | case X86_VENDOR_AMD: | |
1009 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1010 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1011 | break; |
1012 | goto no_apic; | |
1013 | case X86_VENDOR_INTEL: | |
1014 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1015 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1016 | break; | |
1017 | goto no_apic; | |
1018 | default: | |
1019 | goto no_apic; | |
1020 | } | |
1021 | ||
1022 | if (!cpu_has_apic) { | |
1023 | /* | |
e05d723f TG |
1024 | * Over-ride BIOS and try to enable the local APIC only if |
1025 | * "lapic" specified. | |
1da177e4 LT |
1026 | */ |
1027 | if (enable_local_apic <= 0) { | |
e05d723f | 1028 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1029 | "you can enable it with \"lapic\"\n"); |
1030 | return -1; | |
1031 | } | |
1032 | /* | |
e05d723f TG |
1033 | * Some BIOSes disable the local APIC in the APIC_BASE |
1034 | * MSR. This can only be done in software for Intel P6 or later | |
1035 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1036 | */ |
1037 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1038 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1039 | printk(KERN_INFO |
1040 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1041 | l &= ~MSR_IA32_APICBASE_BASE; |
1042 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1043 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1044 | enabled_via_apicbase = 1; | |
1045 | } | |
1046 | } | |
1047 | /* | |
1048 | * The APIC feature bit should now be enabled | |
1049 | * in `cpuid' | |
1050 | */ | |
1051 | features = cpuid_edx(1); | |
1052 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1053 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1054 | return -1; |
1055 | } | |
1056 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1057 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1058 | ||
1059 | /* The BIOS may have set up the APIC at some other address */ | |
1060 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1061 | if (l & MSR_IA32_APICBASE_ENABLE) |
1062 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1063 | |
e05d723f TG |
1064 | if (nmi_watchdog != NMI_NONE) |
1065 | nmi_watchdog = NMI_LOCAL_APIC; | |
1da177e4 | 1066 | |
e05d723f | 1067 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1068 | |
e05d723f | 1069 | apic_pm_activate(); |
1da177e4 | 1070 | |
e05d723f | 1071 | return 0; |
1da177e4 | 1072 | |
e05d723f TG |
1073 | no_apic: |
1074 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1075 | return -1; | |
1076 | } | |
1da177e4 | 1077 | |
e05d723f TG |
1078 | /** |
1079 | * init_apic_mappings - initialize APIC mappings | |
1080 | */ | |
1081 | void __init init_apic_mappings(void) | |
1da177e4 | 1082 | { |
e05d723f | 1083 | unsigned long apic_phys; |
1da177e4 | 1084 | |
1da177e4 | 1085 | /* |
e05d723f TG |
1086 | * If no local APIC can be found then set up a fake all |
1087 | * zeroes page to simulate the local APIC and another | |
1088 | * one for the IO-APIC. | |
1da177e4 | 1089 | */ |
e05d723f TG |
1090 | if (!smp_found_config && detect_init_APIC()) { |
1091 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1092 | apic_phys = __pa(apic_phys); | |
1093 | } else | |
1094 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1095 | |
e05d723f TG |
1096 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1097 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1098 | apic_phys); | |
1da177e4 | 1099 | |
e05d723f TG |
1100 | /* |
1101 | * Fetch the APIC ID of the BSP in case we have a | |
1102 | * default configuration (or the MP table is broken). | |
1103 | */ | |
1104 | if (boot_cpu_physical_apicid == -1U) | |
1105 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 | 1106 | |
e05d723f TG |
1107 | #ifdef CONFIG_X86_IO_APIC |
1108 | { | |
1109 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
1110 | int i; | |
1da177e4 | 1111 | |
e05d723f TG |
1112 | for (i = 0; i < nr_ioapics; i++) { |
1113 | if (smp_found_config) { | |
1114 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
1115 | if (!ioapic_phys) { | |
1116 | printk(KERN_ERR | |
1117 | "WARNING: bogus zero IO-APIC " | |
1118 | "address found in MPTABLE, " | |
1119 | "disabling IO/APIC support!\n"); | |
1120 | smp_found_config = 0; | |
1121 | skip_ioapic_setup = 1; | |
1122 | goto fake_ioapic_page; | |
1123 | } | |
1124 | } else { | |
1125 | fake_ioapic_page: | |
1126 | ioapic_phys = (unsigned long) | |
1127 | alloc_bootmem_pages(PAGE_SIZE); | |
1128 | ioapic_phys = __pa(ioapic_phys); | |
1129 | } | |
1130 | set_fixmap_nocache(idx, ioapic_phys); | |
1131 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
1132 | __fix_to_virt(idx), ioapic_phys); | |
1133 | idx++; | |
1134 | } | |
1da177e4 | 1135 | } |
e05d723f | 1136 | #endif |
1da177e4 LT |
1137 | } |
1138 | ||
e05d723f TG |
1139 | /* |
1140 | * This initializes the IO-APIC and APIC hardware if this is | |
1141 | * a UP kernel. | |
1142 | */ | |
1143 | int __init APIC_init_uniprocessor (void) | |
1da177e4 | 1144 | { |
e05d723f TG |
1145 | if (enable_local_apic < 0) |
1146 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1da177e4 | 1147 | |
e05d723f TG |
1148 | if (!smp_found_config && !cpu_has_apic) |
1149 | return -1; | |
6eb0a0fd | 1150 | |
e05d723f TG |
1151 | /* |
1152 | * Complain if the BIOS pretends there is one. | |
1153 | */ | |
1154 | if (!cpu_has_apic && | |
1155 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1156 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1157 | boot_cpu_physical_apicid); | |
1158 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1159 | return -1; | |
6eb0a0fd | 1160 | } |
6eb0a0fd | 1161 | |
e05d723f | 1162 | verify_local_APIC(); |
6eb0a0fd | 1163 | |
e05d723f | 1164 | connect_bsp_APIC(); |
6eb0a0fd | 1165 | |
e05d723f TG |
1166 | /* |
1167 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1168 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1169 | * might be zero if read from MP tables. Get it from LAPIC. | |
1170 | */ | |
1171 | #ifdef CONFIG_CRASH_DUMP | |
1172 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1173 | #endif | |
1174 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
1da177e4 | 1175 | |
e05d723f | 1176 | setup_local_APIC(); |
1da177e4 | 1177 | |
e05d723f TG |
1178 | #ifdef CONFIG_X86_IO_APIC |
1179 | if (smp_found_config) | |
1180 | if (!skip_ioapic_setup && nr_ioapics) | |
1181 | setup_IO_APIC(); | |
1da177e4 | 1182 | #endif |
e05d723f | 1183 | setup_boot_clock(); |
1da177e4 | 1184 | |
e05d723f | 1185 | return 0; |
1da177e4 LT |
1186 | } |
1187 | ||
1188 | /* | |
e05d723f | 1189 | * APIC command line parameters |
1da177e4 | 1190 | */ |
e05d723f | 1191 | static int __init parse_lapic(char *arg) |
6eb0a0fd | 1192 | { |
e05d723f TG |
1193 | enable_local_apic = 1; |
1194 | return 0; | |
6eb0a0fd | 1195 | } |
e05d723f | 1196 | early_param("lapic", parse_lapic); |
6eb0a0fd | 1197 | |
e05d723f | 1198 | static int __init parse_nolapic(char *arg) |
6eb0a0fd | 1199 | { |
e05d723f TG |
1200 | enable_local_apic = -1; |
1201 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1202 | return 0; | |
6eb0a0fd | 1203 | } |
e05d723f | 1204 | early_param("nolapic", parse_nolapic); |
6eb0a0fd | 1205 | |
e05d723f | 1206 | static int __init apic_set_verbosity(char *str) |
5a07a30c | 1207 | { |
e05d723f TG |
1208 | if (strcmp("debug", str) == 0) |
1209 | apic_verbosity = APIC_DEBUG; | |
1210 | else if (strcmp("verbose", str) == 0) | |
1211 | apic_verbosity = APIC_VERBOSE; | |
1212 | return 1; | |
5a07a30c VP |
1213 | } |
1214 | ||
e05d723f TG |
1215 | __setup("apic=", apic_set_verbosity); |
1216 | ||
1217 | ||
1218 | /* | |
1219 | * Local APIC interrupts | |
1220 | */ | |
1221 | ||
1da177e4 LT |
1222 | /* |
1223 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1224 | */ | |
e9e2cdb4 | 1225 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1226 | { |
1227 | unsigned long v; | |
1228 | ||
1229 | irq_enter(); | |
1230 | /* | |
1231 | * Check if this really is a spurious interrupt and ACK it | |
1232 | * if it is a vectored one. Just in case... | |
1233 | * Spurious interrupts should not be ACKed. | |
1234 | */ | |
1235 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1236 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1237 | ack_APIC_irq(); | |
1238 | ||
1239 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1240 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1241 | "should never happen.\n", smp_processor_id()); | |
1da177e4 LT |
1242 | irq_exit(); |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * This interrupt should never happen with our APIC/SMP architecture | |
1247 | */ | |
e9e2cdb4 | 1248 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1249 | { |
1250 | unsigned long v, v1; | |
1251 | ||
1252 | irq_enter(); | |
1253 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1254 | v = apic_read(APIC_ESR); | |
1255 | apic_write(APIC_ESR, 0); | |
1256 | v1 = apic_read(APIC_ESR); | |
1257 | ack_APIC_irq(); | |
1258 | atomic_inc(&irq_err_count); | |
1259 | ||
1260 | /* Here is what the APIC error bits mean: | |
1261 | 0: Send CS error | |
1262 | 1: Receive CS error | |
1263 | 2: Send accept error | |
1264 | 3: Receive accept error | |
1265 | 4: Reserved | |
1266 | 5: Send illegal vector | |
1267 | 6: Received illegal vector | |
1268 | 7: Illegal register address | |
1269 | */ | |
1270 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
e05d723f | 1271 | smp_processor_id(), v , v1); |
1da177e4 LT |
1272 | irq_exit(); |
1273 | } | |
1274 | ||
1275 | /* | |
e05d723f | 1276 | * Initialize APIC interrupts |
1da177e4 | 1277 | */ |
e05d723f | 1278 | void __init apic_intr_init(void) |
1da177e4 | 1279 | { |
e05d723f TG |
1280 | #ifdef CONFIG_SMP |
1281 | smp_intr_init(); | |
1282 | #endif | |
1283 | /* self generated IPI for local APIC timer */ | |
1284 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
1da177e4 | 1285 | |
e05d723f TG |
1286 | /* IPI vectors for APIC spurious and error interrupts */ |
1287 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
1288 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1289 | |
e05d723f TG |
1290 | /* thermal monitor LVT interrupt */ |
1291 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1292 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
1293 | #endif | |
1294 | } | |
1295 | ||
1296 | /** | |
1297 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1298 | */ | |
1299 | void __init connect_bsp_APIC(void) | |
1300 | { | |
1301 | if (pic_mode) { | |
1302 | /* | |
1303 | * Do not trust the local APIC being empty at bootup. | |
1304 | */ | |
1305 | clear_local_APIC(); | |
1306 | /* | |
1307 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1308 | * local APIC to INT and NMI lines. | |
1309 | */ | |
1310 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1311 | "enabling APIC mode.\n"); | |
1312 | outb(0x70, 0x22); | |
1313 | outb(0x01, 0x23); | |
1da177e4 | 1314 | } |
e05d723f TG |
1315 | enable_apic_mode(); |
1316 | } | |
1da177e4 | 1317 | |
e05d723f TG |
1318 | /** |
1319 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1320 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1321 | * | |
1322 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1323 | * APIC is disabled. | |
1324 | */ | |
1325 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1326 | { | |
1327 | if (pic_mode) { | |
1328 | /* | |
1329 | * Put the board back into PIC mode (has an effect only on | |
1330 | * certain older boards). Note that APIC interrupts, including | |
1331 | * IPIs, won't work beyond this point! The only exception are | |
1332 | * INIT IPIs. | |
1333 | */ | |
1334 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1335 | "entering PIC mode.\n"); | |
1336 | outb(0x70, 0x22); | |
1337 | outb(0x00, 0x23); | |
1338 | } else { | |
1339 | /* Go back to Virtual Wire compatibility mode */ | |
1340 | unsigned long value; | |
1da177e4 | 1341 | |
e05d723f TG |
1342 | /* For the spurious interrupt use vector F, and enable it */ |
1343 | value = apic_read(APIC_SPIV); | |
1344 | value &= ~APIC_VECTOR_MASK; | |
1345 | value |= APIC_SPIV_APIC_ENABLED; | |
1346 | value |= 0xf; | |
1347 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1348 | |
e05d723f TG |
1349 | if (!virt_wire_setup) { |
1350 | /* | |
1351 | * For LVT0 make it edge triggered, active high, | |
1352 | * external and enabled | |
1353 | */ | |
1354 | value = apic_read(APIC_LVT0); | |
1355 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1356 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1357 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
1358 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1359 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1360 | apic_write_around(APIC_LVT0, value); | |
1361 | } else { | |
1362 | /* Disable LVT0 */ | |
1363 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1364 | } | |
1da177e4 | 1365 | |
e05d723f TG |
1366 | /* |
1367 | * For LVT1 make it edge triggered, active high, nmi and | |
1368 | * enabled | |
1369 | */ | |
1370 | value = apic_read(APIC_LVT1); | |
1371 | value &= ~( | |
1372 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1373 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1374 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1375 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1376 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1377 | apic_write_around(APIC_LVT1, value); | |
1378 | } | |
1379 | } | |
1da177e4 | 1380 | |
e05d723f TG |
1381 | /* |
1382 | * Power management | |
1383 | */ | |
1384 | #ifdef CONFIG_PM | |
1385 | ||
1386 | static struct { | |
1387 | int active; | |
1388 | /* r/w apic fields */ | |
1389 | unsigned int apic_id; | |
1390 | unsigned int apic_taskpri; | |
1391 | unsigned int apic_ldr; | |
1392 | unsigned int apic_dfr; | |
1393 | unsigned int apic_spiv; | |
1394 | unsigned int apic_lvtt; | |
1395 | unsigned int apic_lvtpc; | |
1396 | unsigned int apic_lvt0; | |
1397 | unsigned int apic_lvt1; | |
1398 | unsigned int apic_lvterr; | |
1399 | unsigned int apic_tmict; | |
1400 | unsigned int apic_tdcr; | |
1401 | unsigned int apic_thmr; | |
1402 | } apic_pm_state; | |
1403 | ||
1404 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1405 | { | |
1406 | unsigned long flags; | |
1407 | int maxlvt; | |
1408 | ||
1409 | if (!apic_pm_state.active) | |
1410 | return 0; | |
1411 | ||
1412 | maxlvt = lapic_get_maxlvt(); | |
1413 | ||
1414 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1415 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1416 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1417 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1418 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1419 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1420 | if (maxlvt >= 4) | |
1421 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1422 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1423 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1424 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1425 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1426 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1427 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1428 | if (maxlvt >= 5) | |
1429 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1430 | #endif |
1e4c85f9 | 1431 | |
e05d723f TG |
1432 | local_irq_save(flags); |
1433 | disable_local_APIC(); | |
1434 | local_irq_restore(flags); | |
1e4c85f9 | 1435 | return 0; |
1da177e4 | 1436 | } |
1a3f239d | 1437 | |
e05d723f | 1438 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1439 | { |
e05d723f TG |
1440 | unsigned int l, h; |
1441 | unsigned long flags; | |
1442 | int maxlvt; | |
1443 | ||
1444 | if (!apic_pm_state.active) | |
1445 | return 0; | |
1446 | ||
1447 | maxlvt = lapic_get_maxlvt(); | |
1448 | ||
1449 | local_irq_save(flags); | |
1450 | ||
1451 | /* | |
1452 | * Make sure the APICBASE points to the right address | |
1453 | * | |
1454 | * FIXME! This will be wrong if we ever support suspend on | |
1455 | * SMP! We'll need to do this as part of the CPU restore! | |
1456 | */ | |
1457 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1458 | l &= ~MSR_IA32_APICBASE_BASE; | |
1459 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1460 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1461 | ||
1462 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1463 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1464 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1465 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1466 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1467 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1468 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1469 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1470 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1471 | if (maxlvt >= 5) | |
1472 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1473 | #endif | |
1474 | if (maxlvt >= 4) | |
1475 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1476 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1477 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1478 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1479 | apic_write(APIC_ESR, 0); | |
1480 | apic_read(APIC_ESR); | |
1481 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1482 | apic_write(APIC_ESR, 0); | |
1483 | apic_read(APIC_ESR); | |
1484 | local_irq_restore(flags); | |
1a3f239d RR |
1485 | return 0; |
1486 | } | |
1a3f239d | 1487 | |
e05d723f TG |
1488 | /* |
1489 | * This device has no shutdown method - fully functioning local APICs | |
1490 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1491 | */ | |
1492 | ||
1493 | static struct sysdev_class lapic_sysclass = { | |
1494 | set_kset_name("lapic"), | |
1495 | .resume = lapic_resume, | |
1496 | .suspend = lapic_suspend, | |
1497 | }; | |
1498 | ||
1499 | static struct sys_device device_lapic = { | |
1500 | .id = 0, | |
1501 | .cls = &lapic_sysclass, | |
1502 | }; | |
1503 | ||
1504 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1505 | { |
e05d723f | 1506 | apic_pm_state.active = 1; |
1a3f239d | 1507 | } |
1a3f239d | 1508 | |
e05d723f TG |
1509 | static int __init init_lapic_sysfs(void) |
1510 | { | |
1511 | int error; | |
1512 | ||
1513 | if (!cpu_has_apic) | |
1514 | return 0; | |
1515 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1516 | ||
1517 | error = sysdev_class_register(&lapic_sysclass); | |
1518 | if (!error) | |
1519 | error = sysdev_register(&device_lapic); | |
1520 | return error; | |
1521 | } | |
1522 | device_initcall(init_lapic_sysfs); | |
1523 | ||
1524 | #else /* CONFIG_PM */ | |
1525 | ||
1526 | static void apic_pm_activate(void) { } | |
1527 | ||
1528 | #endif /* CONFIG_PM */ |