[mirror_ubuntu-artful-kernel.git] / arch / i386 / kernel / cpu / amd.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/processor.h>

#include "cpu.h"

/*
 *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *	misexecution of code under Linux. Owners of such processors should
 *	contact AMD for precise details and a CPU swap.
 *
 *	See	http://www.multimania.com/poulot/k6bug.html
 *		http://www.amd.com/K6/k6docs/revgd.html
 *
 *	The following test is erm.. interesting. AMD neglected to up
 *	the chip setting when fixing the bug but they also tweaked some
 *	performance at the same time..
 */
 
extern void vide(void);
__asm__(".align 4\nvide: ret");

static void __init init_amd(struct cpuinfo_x86 *c)
{
	u32 l, h;
	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	int r;

#ifdef CONFIG_SMP
	unsigned long long value;

	/* Disable TLB flush filter by setting HWCR.FFDIS on K8
	 * bit 6 of msr C001_0015
	 *
	 * Errata 63 for SH-B3 steppings
	 * Errata 122 for all steppings (F+ have it disabled by default)
	 */
	if (c->x86 == 15) {
		rdmsrl(MSR_K7_HWCR, value);
		value |= 1 << 6;
		wrmsrl(MSR_K7_HWCR, value);
	}
#endif

	/*
	 *	FIXME: We should handle the K5 here. Set up the write
	 *	range and also turn on MSR 83 bits 4 and 31 (write alloc,
	 *	no bus pipeline)
	 */

	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
	clear_bit(0*32+31, c->x86_capability);
	
	r = get_model_name(c);

	switch(c->x86)
	{
		case 4:
		/*
		 * General Systems BIOSen alias the cpu frequency registers
		 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
		 * drivers subsequently pokes it, and changes the CPU speed.
		 * Workaround : Remove the unneeded alias.
		 */
#define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
#define CBAR_ENB	(0x80000000)
#define CBAR_KEY	(0X000000CB)
			if (c->x86_model==9 || c->x86_model == 10) {
				if (inl (CBAR) & CBAR_ENB)
					outl (0 | CBAR_KEY, CBAR);
			}
			break;
		case 5:
			if( c->x86_model < 6 )
			{
				/* Based on AMD doc 20734R - June 2000 */
				if ( c->x86_model == 0 ) {
					clear_bit(X86_FEATURE_APIC, c->x86_capability);
					set_bit(X86_FEATURE_PGE, c->x86_capability);
				}
				break;
			}
			
			if ( c->x86_model == 6 && c->x86_mask == 1 ) {
				const int K6_BUG_LOOP = 1000000;
				int n;
				void (*f_vide)(void);
				unsigned long d, d2;
				
				printk(KERN_INFO "AMD K6 stepping B detected - ");
				
				/*
				 * It looks like AMD fixed the 2.6.2 bug and improved indirect 
				 * calls at the same time.
				 */

				n = K6_BUG_LOOP;
				f_vide = vide;
				rdtscl(d);
				while (n--) 
					f_vide();
				rdtscl(d2);
				d = d2-d;
				
				/* Knock these two lines out if it debugs out ok */
				printk(KERN_INFO "AMD K6 stepping B detected - ");
				/* -- cut here -- */
				if (d > 20*K6_BUG_LOOP) 
					printk("system stability may be impaired when more than 32 MB are used.\n");
				else 
					printk("probably OK (after B9730xxxx).\n");
				printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
			}

			/* K6 with old style WHCR */
			if (c->x86_model < 8 ||
			   (c->x86_model== 8 && c->x86_mask < 8)) {
				/* We can only write allocate on the low 508Mb */
				if(mbytes>508)
					mbytes=508;

				rdmsr(MSR_K6_WHCR, l, h);
				if ((l&0x0000FFFF)==0) {
					unsigned long flags;
					l=(1<<0)|((mbytes/4)<<1);
					local_irq_save(flags);
					wbinvd();
					wrmsr(MSR_K6_WHCR, l, h);
					local_irq_restore(flags);
					printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
						mbytes);
				}
				break;
			}

			if ((c->x86_model == 8 && c->x86_mask >7) ||
			     c->x86_model == 9 || c->x86_model == 13) {
				/* The more serious chips .. */

				if(mbytes>4092)
					mbytes=4092;

				rdmsr(MSR_K6_WHCR, l, h);
				if ((l&0xFFFF0000)==0) {
					unsigned long flags;
					l=((mbytes>>2)<<22)|(1<<16);
					local_irq_save(flags);
					wbinvd();
					wrmsr(MSR_K6_WHCR, l, h);
					local_irq_restore(flags);
					printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
						mbytes);
				}

				/*  Set MTRR capability flag if appropriate */
				if (c->x86_model == 13 || c->x86_model == 9 ||
				   (c->x86_model == 8 && c->x86_mask >= 8))
					set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
				break;
			}

			if (c->x86_model == 10) {
				/* AMD Geode LX is model 10 */
				/* placeholder for any needed mods */
				break;
			}
			break;
		case 6: /* An Athlon/Duron */
 
			/* Bit 15 of Athlon specific MSR 15, needs to be 0
 			 * to enable SSE on Palomino/Morgan/Barton CPU's.
			 * If the BIOS didn't enable it already, enable it here.
			 */
			if (c->x86_model >= 6 && c->x86_model <= 10) {
				if (!cpu_has(c, X86_FEATURE_XMM)) {
					printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
					rdmsr(MSR_K7_HWCR, l, h);
					l &= ~0x00008000;
					wrmsr(MSR_K7_HWCR, l, h);
					set_bit(X86_FEATURE_XMM, c->x86_capability);
				}
			}

			/* It's been determined by AMD that Athlons since model 8 stepping 1
			 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
			 * As per AMD technical note 27212 0.2
			 */
			if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
				rdmsr(MSR_K7_CLK_CTL, l, h);
				if ((l & 0xfff00000) != 0x20000000) {
					printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
						((l & 0x000fffff)|0x20000000));
					wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
				}
			}
			break;
	}

	switch (c->x86) {
	case 15:
		set_bit(X86_FEATURE_K8, c->x86_capability);
		break;
	case 6:
		set_bit(X86_FEATURE_K7, c->x86_capability); 
		break;
	}

	display_cacheinfo(c);

	if (cpuid_eax(0x80000000) >= 0x80000008) {
		c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
		if (c->x86_max_cores & (c->x86_max_cores - 1))
			c->x86_max_cores = 1;
	}

#ifdef CONFIG_X86_HT
	/*
	 * On a AMD dual core setup the lower bits of the APIC id
	 * distingush the cores.  Assumes number of cores is a power
	 * of two.
	 */
	if (c->x86_max_cores > 1) {
		int cpu = smp_processor_id();
		unsigned bits = 0;
		while ((1 << bits) < c->x86_max_cores)
			bits++;
		cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
		phys_proc_id[cpu] >>= bits;
		printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
		       cpu, c->x86_max_cores, cpu_core_id[cpu]);
	}
#endif
}

static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
	/* AMD errata T13 (order #21922) */
	if ((c->x86 == 6)) {
		if (c->x86_model == 3 && c->x86_mask == 0)	/* Duron Rev A0 */
			size = 64;
		if (c->x86_model == 4 &&
		    (c->x86_mask==0 || c->x86_mask==1))	/* Tbird rev A1/A2 */
			size = 256;
	}
	return size;
}

static struct cpu_dev amd_cpu_dev __initdata = {
	.c_vendor	= "AMD",
	.c_ident 	= { "AuthenticAMD" },
	.c_models = {
		{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
		  {
			  [3] = "486 DX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4", 
			  [9] = "486 DX/4-WB", 
			  [14] = "Am5x86-WT",
			  [15] = "Am5x86-WB" 
		  }
		},
	},
	.c_init		= init_amd,
	.c_identify	= generic_identify,
	.c_size_cache	= amd_size_cache,
};

int __init amd_init_cpu(void)
{
	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
	return 0;
}

//early_arch_initcall(amd_init_cpu);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/mm.h>
	4	#include <asm/io.h>
	5	#include <asm/processor.h>
	6
	7	#include "cpu.h"
	8
	9	/*
	10	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
	11	* misexecution of code under Linux. Owners of such processors should
	12	* contact AMD for precise details and a CPU swap.
	13	*
	14	* See http://www.multimania.com/poulot/k6bug.html
	15	* http://www.amd.com/K6/k6docs/revgd.html
	16	*
	17	* The following test is erm.. interesting. AMD neglected to up
	18	* the chip setting when fixing the bug but they also tweaked some
	19	* performance at the same time..
	20	*/
	21
	22	extern void vide(void);
	23	__asm__(".align 4\nvide: ret");
	24
	25	static void __init init_amd(struct cpuinfo_x86 *c)
	26	{
	27	u32 l, h;
	28	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	29	int r;
	30
7d318d77	31	#ifdef CONFIG_SMP
3c92c2ba	32	unsigned long long value;
7d318d77 AK	33
	34	/* Disable TLB flush filter by setting HWCR.FFDIS on K8
	35	* bit 6 of msr C001_0015
	36	*
	37	* Errata 63 for SH-B3 steppings
	38	* Errata 122 for all steppings (F+ have it disabled by default)
	39	*/
	40	if (c->x86 == 15) {
	41	rdmsrl(MSR_K7_HWCR, value);
	42	value \|= 1 << 6;
	43	wrmsrl(MSR_K7_HWCR, value);
	44	}
	45	#endif
	46
1da177e4 LT	47	/*
	48	* FIXME: We should handle the K5 here. Set up the write
	49	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
	50	* no bus pipeline)
	51	*/
	52
	53	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	54	3DNow is IDd by bit 31 in extended CPUID (132+31) anyway /
	55	clear_bit(0*32+31, c->x86_capability);
	56
	57	r = get_model_name(c);
	58
	59	switch(c->x86)
	60	{
	61	case 4:
	62	/*
	63	* General Systems BIOSen alias the cpu frequency registers
	64	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
	65	* drivers subsequently pokes it, and changes the CPU speed.
	66	* Workaround : Remove the unneeded alias.
	67	*/
	68	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
	69	#define CBAR_ENB (0x80000000)
	70	#define CBAR_KEY (0X000000CB)
	71	if (c->x86_model==9 \|\| c->x86_model == 10) {
	72	if (inl (CBAR) & CBAR_ENB)
	73	outl (0 \| CBAR_KEY, CBAR);
	74	}
	75	break;
	76	case 5:
	77	if( c->x86_model < 6 )
	78	{
	79	/* Based on AMD doc 20734R - June 2000 */
	80	if ( c->x86_model == 0 ) {
	81	clear_bit(X86_FEATURE_APIC, c->x86_capability);
	82	set_bit(X86_FEATURE_PGE, c->x86_capability);
	83	}
	84	break;
	85	}
	86
	87	if ( c->x86_model == 6 && c->x86_mask == 1 ) {
	88	const int K6_BUG_LOOP = 1000000;
	89	int n;
	90	void (*f_vide)(void);
	91	unsigned long d, d2;
	92
	93	printk(KERN_INFO "AMD K6 stepping B detected - ");
	94
	95	/*
	96	* It looks like AMD fixed the 2.6.2 bug and improved indirect
	97	* calls at the same time.
	98	*/
	99
	100	n = K6_BUG_LOOP;
	101	f_vide = vide;
	102	rdtscl(d);
	103	while (n--)
	104	f_vide();
	105	rdtscl(d2);
	106	d = d2-d;
	107
	108	/* Knock these two lines out if it debugs out ok */
	109	printk(KERN_INFO "AMD K6 stepping B detected - ");
	110	/* -- cut here -- */
111	if (d > 20*K6_BUG_LOOP)
112	printk("system stability may be impaired when more than 32 MB are used.\n");
113	else
114	printk("probably OK (after B9730xxxx).\n");
115	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
116	}
117
118	/* K6 with old style WHCR */
119	if (c->x86_model < 8 \|\|
120	(c->x86_model== 8 && c->x86_mask < 8)) {
121	/* We can only write allocate on the low 508Mb */
122	if(mbytes>508)
123	mbytes=508;
124
125	rdmsr(MSR_K6_WHCR, l, h);
126	if ((l&0x0000FFFF)==0) {
127	unsigned long flags;
128	l=(1<<0)\|((mbytes/4)<<1);
129	local_irq_save(flags);
130	wbinvd();
131	wrmsr(MSR_K6_WHCR, l, h);
132	local_irq_restore(flags);
133	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
134	mbytes);
135	}
136	break;
137	}
138
139	if ((c->x86_model == 8 && c->x86_mask >7) \|\|
140	c->x86_model == 9 \|\| c->x86_model == 13) {
141	/* The more serious chips .. */
142
143	if(mbytes>4092)
144	mbytes=4092;
145
146	rdmsr(MSR_K6_WHCR, l, h);
147	if ((l&0xFFFF0000)==0) {
148	unsigned long flags;
149	l=((mbytes>>2)<<22)\|(1<<16);
150	local_irq_save(flags);
151	wbinvd();
152	wrmsr(MSR_K6_WHCR, l, h);
153	local_irq_restore(flags);
154	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
155	mbytes);
156	}
157
158	/* Set MTRR capability flag if appropriate */
159	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
160	(c->x86_model == 8 && c->x86_mask >= 8))
161	set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
162	break;
163	}
1da177e4	164
f90b8116 JC	165	if (c->x86_model == 10) {
	166	/* AMD Geode LX is model 10 */
	167	/* placeholder for any needed mods */
	168	break;
	169	}
	170	break;
1da177e4 LT	171	case 6: /* An Athlon/Duron */
	172
	173	/* Bit 15 of Athlon specific MSR 15, needs to be 0
	174	* to enable SSE on Palomino/Morgan/Barton CPU's.
	175	* If the BIOS didn't enable it already, enable it here.
	176	*/
	177	if (c->x86_model >= 6 && c->x86_model <= 10) {
	178	if (!cpu_has(c, X86_FEATURE_XMM)) {
	179	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
	180	rdmsr(MSR_K7_HWCR, l, h);
	181	l &= ~0x00008000;
	182	wrmsr(MSR_K7_HWCR, l, h);
	183	set_bit(X86_FEATURE_XMM, c->x86_capability);
	184	}
	185	}
	186
	187	/* It's been determined by AMD that Athlons since model 8 stepping 1
	188	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
	189	* As per AMD technical note 27212 0.2
	190	*/
	191	if ((c->x86_model == 8 && c->x86_mask>=1) \|\| (c->x86_model > 8)) {
	192	rdmsr(MSR_K7_CLK_CTL, l, h);
	193	if ((l & 0xfff00000) != 0x20000000) {
	194	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
	195	((l & 0x000fffff)\|0x20000000));
	196	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
	197	}
	198	}
	199	break;
	200	}
	201
	202	switch (c->x86) {
	203	case 15:
	204	set_bit(X86_FEATURE_K8, c->x86_capability);
	205	break;
	206	case 6:
	207	set_bit(X86_FEATURE_K7, c->x86_capability);
	208	break;
	209	}
	210
	211	display_cacheinfo(c);
3dd9d514 AK	212
3dd9d514 AK	213	if (cpuid_eax(0x80000000) >= 0x80000008) {
94605eff SS	214	c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
	215	if (c->x86_max_cores & (c->x86_max_cores - 1))
	216	c->x86_max_cores = 1;
3dd9d514 AK	217	}
3dd9d514 AK	218
b41e2939	219	#ifdef CONFIG_X86_HT
63518644 AK	220	/*
	221	* On a AMD dual core setup the lower bits of the APIC id
	222	* distingush the cores. Assumes number of cores is a power
	223	* of two.
	224	*/
94605eff	225	if (c->x86_max_cores > 1) {
a158608b	226	int cpu = smp_processor_id();
b41e2939	227	unsigned bits = 0;
94605eff	228	while ((1 << bits) < c->x86_max_cores)
b41e2939 AK	229	bits++;
	230	cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
	231	phys_proc_id[cpu] >>= bits;
63518644	232	printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
94605eff	233	cpu, c->x86_max_cores, cpu_core_id[cpu]);
63518644	234	}
1da177e4	235	#endif
1da177e4 LT	236	}
	237
	238	static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
	239	{
	240	/* AMD errata T13 (order #21922) */
	241	if ((c->x86 == 6)) {
	242	if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
	243	size = 64;
	244	if (c->x86_model == 4 &&
	245	(c->x86_mask==0 \|\| c->x86_mask==1)) /* Tbird rev A1/A2 */
	246	size = 256;
	247	}
	248	return size;
	249	}
	250
	251	static struct cpu_dev amd_cpu_dev __initdata = {
	252	.c_vendor = "AMD",
	253	.c_ident = { "AuthenticAMD" },
	254	.c_models = {
	255	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
	256	{
	257	[3] = "486 DX/2",
	258	[7] = "486 DX/2-WB",
	259	[8] = "486 DX/4",
	260	[9] = "486 DX/4-WB",
	261	[14] = "Am5x86-WT",
	262	[15] = "Am5x86-WB"
	263	}
	264	},
	265	},
	266	.c_init = init_amd,
	267	.c_identify = generic_identify,
	268	.c_size_cache = amd_size_cache,
	269	};
	270
	271	int __init amd_init_cpu(void)
	272	{
	273	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
	274	return 0;
	275	}
	276
	277	//early_arch_initcall(amd_init_cpu);