[mirror_ubuntu-artful-kernel.git] / arch / i386 / kernel / cpu / amd.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/processor.h>

#include "cpu.h"

/*
 *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *	misexecution of code under Linux. Owners of such processors should
 *	contact AMD for precise details and a CPU swap.
 *
 *	See	http://www.multimania.com/poulot/k6bug.html
 *		http://www.amd.com/K6/k6docs/revgd.html
 *
 *	The following test is erm.. interesting. AMD neglected to up
 *	the chip setting when fixing the bug but they also tweaked some
 *	performance at the same time..
 */
 
extern void vide(void);
__asm__(".align 4\nvide: ret");

#define ENABLE_C1E_MASK         0x18000000
#define CPUID_PROCESSOR_SIGNATURE       1
#define CPUID_XFAM              0x0ff00000
#define CPUID_XFAM_K8           0x00000000
#define CPUID_XFAM_10H          0x00100000
#define CPUID_XFAM_11H          0x00200000
#define CPUID_XMOD              0x000f0000
#define CPUID_XMOD_REV_F        0x00040000

/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
static __cpuinit int amd_apic_timer_broken(void)
{
	u32 lo, hi;
	u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
	switch (eax & CPUID_XFAM) {
	case CPUID_XFAM_K8:
		if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
			break;
	case CPUID_XFAM_10H:
	case CPUID_XFAM_11H:
		rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
		if (lo & ENABLE_C1E_MASK)
			return 1;
                break;
        default:
                /* err on the side of caution */
		return 1;
        }
	return 0;
}

int force_mwait __cpuinitdata;

static void __cpuinit init_amd(struct cpuinfo_x86 *c)
{
	u32 l, h;
	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	int r;

#ifdef CONFIG_SMP
	unsigned long long value;

	/* Disable TLB flush filter by setting HWCR.FFDIS on K8
	 * bit 6 of msr C001_0015
	 *
	 * Errata 63 for SH-B3 steppings
	 * Errata 122 for all steppings (F+ have it disabled by default)
	 */
	if (c->x86 == 15) {
		rdmsrl(MSR_K7_HWCR, value);
		value |= 1 << 6;
		wrmsrl(MSR_K7_HWCR, value);
	}
#endif

	/*
	 *	FIXME: We should handle the K5 here. Set up the write
	 *	range and also turn on MSR 83 bits 4 and 31 (write alloc,
	 *	no bus pipeline)
	 */

	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
	clear_bit(0*32+31, c->x86_capability);
	
	r = get_model_name(c);

	switch(c->x86)
	{
		case 4:
		/*
		 * General Systems BIOSen alias the cpu frequency registers
		 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
		 * drivers subsequently pokes it, and changes the CPU speed.
		 * Workaround : Remove the unneeded alias.
		 */
#define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
#define CBAR_ENB	(0x80000000)
#define CBAR_KEY	(0X000000CB)
			if (c->x86_model==9 || c->x86_model == 10) {
				if (inl (CBAR) & CBAR_ENB)
					outl (0 | CBAR_KEY, CBAR);
			}
			break;
		case 5:
			if( c->x86_model < 6 )
			{
				/* Based on AMD doc 20734R - June 2000 */
				if ( c->x86_model == 0 ) {
					clear_bit(X86_FEATURE_APIC, c->x86_capability);
					set_bit(X86_FEATURE_PGE, c->x86_capability);
				}
				break;
			}
			
			if ( c->x86_model == 6 && c->x86_mask == 1 ) {
				const int K6_BUG_LOOP = 1000000;
				int n;
				void (*f_vide)(void);
				unsigned long d, d2;
				
				printk(KERN_INFO "AMD K6 stepping B detected - ");
				
				/*
				 * It looks like AMD fixed the 2.6.2 bug and improved indirect 
				 * calls at the same time.
				 */

				n = K6_BUG_LOOP;
				f_vide = vide;
				rdtscl(d);
				while (n--) 
					f_vide();
				rdtscl(d2);
				d = d2-d;

				if (d > 20*K6_BUG_LOOP) 
					printk("system stability may be impaired when more than 32 MB are used.\n");
				else 
					printk("probably OK (after B9730xxxx).\n");
				printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
			}

			/* K6 with old style WHCR */
			if (c->x86_model < 8 ||
			   (c->x86_model== 8 && c->x86_mask < 8)) {
				/* We can only write allocate on the low 508Mb */
				if(mbytes>508)
					mbytes=508;

				rdmsr(MSR_K6_WHCR, l, h);
				if ((l&0x0000FFFF)==0) {
					unsigned long flags;
					l=(1<<0)|((mbytes/4)<<1);
					local_irq_save(flags);
					wbinvd();
					wrmsr(MSR_K6_WHCR, l, h);
					local_irq_restore(flags);
					printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
						mbytes);
				}
				break;
			}

			if ((c->x86_model == 8 && c->x86_mask >7) ||
			     c->x86_model == 9 || c->x86_model == 13) {
				/* The more serious chips .. */

				if(mbytes>4092)
					mbytes=4092;

				rdmsr(MSR_K6_WHCR, l, h);
				if ((l&0xFFFF0000)==0) {
					unsigned long flags;
					l=((mbytes>>2)<<22)|(1<<16);
					local_irq_save(flags);
					wbinvd();
					wrmsr(MSR_K6_WHCR, l, h);
					local_irq_restore(flags);
					printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
						mbytes);
				}

				/*  Set MTRR capability flag if appropriate */
				if (c->x86_model == 13 || c->x86_model == 9 ||
				   (c->x86_model == 8 && c->x86_mask >= 8))
					set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
				break;
			}

			if (c->x86_model == 10) {
				/* AMD Geode LX is model 10 */
				/* placeholder for any needed mods */
				break;
			}
			break;
		case 6: /* An Athlon/Duron */
 
			/* Bit 15 of Athlon specific MSR 15, needs to be 0
 			 * to enable SSE on Palomino/Morgan/Barton CPU's.
			 * If the BIOS didn't enable it already, enable it here.
			 */
			if (c->x86_model >= 6 && c->x86_model <= 10) {
				if (!cpu_has(c, X86_FEATURE_XMM)) {
					printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
					rdmsr(MSR_K7_HWCR, l, h);
					l &= ~0x00008000;
					wrmsr(MSR_K7_HWCR, l, h);
					set_bit(X86_FEATURE_XMM, c->x86_capability);
				}
			}

			/* It's been determined by AMD that Athlons since model 8 stepping 1
			 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
			 * As per AMD technical note 27212 0.2
			 */
			if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
				rdmsr(MSR_K7_CLK_CTL, l, h);
				if ((l & 0xfff00000) != 0x20000000) {
					printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
						((l & 0x000fffff)|0x20000000));
					wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
				}
			}
			break;
	}

	switch (c->x86) {
	case 15:
	/* Use K8 tuning for Fam10h and Fam11h */
	case 0x10:
	case 0x11:
		set_bit(X86_FEATURE_K8, c->x86_capability);
		break;
	case 6:
		set_bit(X86_FEATURE_K7, c->x86_capability); 
		break;
	}
	if (c->x86 >= 6)
		set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);

	display_cacheinfo(c);

	if (cpuid_eax(0x80000000) >= 0x80000008) {
		c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
	}

	if (cpuid_eax(0x80000000) >= 0x80000007) {
		c->x86_power = cpuid_edx(0x80000007);
		if (c->x86_power & (1<<8))
			set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
	}

#ifdef CONFIG_X86_HT
	/*
	 * On a AMD multi core setup the lower bits of the APIC id
	 * distingush the cores.
	 */
	if (c->x86_max_cores > 1) {
		int cpu = smp_processor_id();
		unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;

		if (bits == 0) {
			while ((1 << bits) < c->x86_max_cores)
				bits++;
		}
		c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
		c->phys_proc_id >>= bits;
		printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
		       cpu, c->x86_max_cores, c->cpu_core_id);
	}
#endif

	if (cpuid_eax(0x80000000) >= 0x80000006) {
		if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
			num_cache_leaves = 4;
		else
			num_cache_leaves = 3;
	}

	if (amd_apic_timer_broken())
		set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);

	if (c->x86 == 0x10 && !force_mwait)
		clear_bit(X86_FEATURE_MWAIT, c->x86_capability);

	/* K6s reports MCEs but don't actually have all the MSRs */
	if (c->x86 < 6)
		clear_bit(X86_FEATURE_MCE, c->x86_capability);
}

static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
	/* AMD errata T13 (order #21922) */
	if ((c->x86 == 6)) {
		if (c->x86_model == 3 && c->x86_mask == 0)	/* Duron Rev A0 */
			size = 64;
		if (c->x86_model == 4 &&
		    (c->x86_mask==0 || c->x86_mask==1))	/* Tbird rev A1/A2 */
			size = 256;
	}
	return size;
}

static struct cpu_dev amd_cpu_dev __cpuinitdata = {
	.c_vendor	= "AMD",
	.c_ident 	= { "AuthenticAMD" },
	.c_models = {
		{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
		  {
			  [3] = "486 DX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4", 
			  [9] = "486 DX/4-WB", 
			  [14] = "Am5x86-WT",
			  [15] = "Am5x86-WB" 
		  }
		},
	},
	.c_init		= init_amd,
	.c_size_cache	= amd_size_cache,
};

int __init amd_init_cpu(void)
{
	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/mm.h>
	4	#include <asm/io.h>
	5	#include <asm/processor.h>
	6
	7	#include "cpu.h"
	8
	9	/*
	10	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
	11	* misexecution of code under Linux. Owners of such processors should
	12	* contact AMD for precise details and a CPU swap.
	13	*
	14	* See http://www.multimania.com/poulot/k6bug.html
	15	* http://www.amd.com/K6/k6docs/revgd.html
	16	*
	17	* The following test is erm.. interesting. AMD neglected to up
	18	* the chip setting when fixing the bug but they also tweaked some
	19	* performance at the same time..
	20	*/
	21
	22	extern void vide(void);
	23	__asm__(".align 4\nvide: ret");
	24
3556ddfa AK	25	#define ENABLE_C1E_MASK 0x18000000
	26	#define CPUID_PROCESSOR_SIGNATURE 1
	27	#define CPUID_XFAM 0x0ff00000
	28	#define CPUID_XFAM_K8 0x00000000
	29	#define CPUID_XFAM_10H 0x00100000
	30	#define CPUID_XFAM_11H 0x00200000
	31	#define CPUID_XMOD 0x000f0000
	32	#define CPUID_XMOD_REV_F 0x00040000
	33
	34	/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
	35	static __cpuinit int amd_apic_timer_broken(void)
	36	{
	37	u32 lo, hi;
	38	u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
	39	switch (eax & CPUID_XFAM) {
	40	case CPUID_XFAM_K8:
	41	if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
	42	break;
	43	case CPUID_XFAM_10H:
	44	case CPUID_XFAM_11H:
	45	rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
	46	if (lo & ENABLE_C1E_MASK)
	47	return 1;
	48	break;
	49	default:
	50	/* err on the side of caution */
	51	return 1;
	52	}
	53	return 0;
	54	}
	55
f039b754 AK	56	int force_mwait __cpuinitdata;
f039b754 AK	57
b4af3f7c	58	static void __cpuinit init_amd(struct cpuinfo_x86 *c)
1da177e4 LT	59	{
	60	u32 l, h;
	61	int mbytes = num_physpages >> (20-PAGE_SHIFT);
	62	int r;
	63
7d318d77	64	#ifdef CONFIG_SMP
3c92c2ba	65	unsigned long long value;
7d318d77 AK	66
	67	/* Disable TLB flush filter by setting HWCR.FFDIS on K8
	68	* bit 6 of msr C001_0015
	69	*
	70	* Errata 63 for SH-B3 steppings
	71	* Errata 122 for all steppings (F+ have it disabled by default)
	72	*/
	73	if (c->x86 == 15) {
	74	rdmsrl(MSR_K7_HWCR, value);
	75	value \|= 1 << 6;
	76	wrmsrl(MSR_K7_HWCR, value);
	77	}
	78	#endif
	79
1da177e4 LT	80	/*
	81	* FIXME: We should handle the K5 here. Set up the write
	82	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
	83	* no bus pipeline)
	84	*/
	85
	86	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	87	3DNow is IDd by bit 31 in extended CPUID (132+31) anyway /
	88	clear_bit(0*32+31, c->x86_capability);
	89
	90	r = get_model_name(c);
	91
	92	switch(c->x86)
	93	{
	94	case 4:
	95	/*
	96	* General Systems BIOSen alias the cpu frequency registers
	97	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
	98	* drivers subsequently pokes it, and changes the CPU speed.
	99	* Workaround : Remove the unneeded alias.
	100	*/
	101	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
	102	#define CBAR_ENB (0x80000000)
	103	#define CBAR_KEY (0X000000CB)
	104	if (c->x86_model==9 \|\| c->x86_model == 10) {
	105	if (inl (CBAR) & CBAR_ENB)
	106	outl (0 \| CBAR_KEY, CBAR);
	107	}
	108	break;
	109	case 5:
	110	if( c->x86_model < 6 )
	111	{
	112	/* Based on AMD doc 20734R - June 2000 */
	113	if ( c->x86_model == 0 ) {
	114	clear_bit(X86_FEATURE_APIC, c->x86_capability);
	115	set_bit(X86_FEATURE_PGE, c->x86_capability);
	116	}
	117	break;
	118	}
	119
	120	if ( c->x86_model == 6 && c->x86_mask == 1 ) {
	121	const int K6_BUG_LOOP = 1000000;
	122	int n;
	123	void (*f_vide)(void);
	124	unsigned long d, d2;
	125
	126	printk(KERN_INFO "AMD K6 stepping B detected - ");
	127
	128	/*
	129	* It looks like AMD fixed the 2.6.2 bug and improved indirect
	130	* calls at the same time.
	131	*/
	132
	133	n = K6_BUG_LOOP;
	134	f_vide = vide;
	135	rdtscl(d);
	136	while (n--)
	137	f_vide();
	138	rdtscl(d2);
	139	d = d2-d;
6df0532e	140
1da177e4 LT	141	if (d > 20*K6_BUG_LOOP)
	142	printk("system stability may be impaired when more than 32 MB are used.\n");
	143	else
	144	printk("probably OK (after B9730xxxx).\n");
	145	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
	146	}
	147
	148	/* K6 with old style WHCR */
	149	if (c->x86_model < 8 \|\|
	150	(c->x86_model== 8 && c->x86_mask < 8)) {
	151	/* We can only write allocate on the low 508Mb */
	152	if(mbytes>508)
	153	mbytes=508;
	154
	155	rdmsr(MSR_K6_WHCR, l, h);
	156	if ((l&0x0000FFFF)==0) {
	157	unsigned long flags;
	158	l=(1<<0)\|((mbytes/4)<<1);
	159	local_irq_save(flags);
	160	wbinvd();
	161	wrmsr(MSR_K6_WHCR, l, h);
	162	local_irq_restore(flags);
	163	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
	164	mbytes);
	165	}
	166	break;
	167	}
	168
	169	if ((c->x86_model == 8 && c->x86_mask >7) \|\|
	170	c->x86_model == 9 \|\| c->x86_model == 13) {
	171	/* The more serious chips .. */
	172
	173	if(mbytes>4092)
	174	mbytes=4092;
	175
	176	rdmsr(MSR_K6_WHCR, l, h);
	177	if ((l&0xFFFF0000)==0) {
	178	unsigned long flags;
	179	l=((mbytes>>2)<<22)\|(1<<16);
	180	local_irq_save(flags);
	181	wbinvd();
	182	wrmsr(MSR_K6_WHCR, l, h);
	183	local_irq_restore(flags);
	184	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
	185	mbytes);
	186	}
	187
	188	/* Set MTRR capability flag if appropriate */
	189	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
	190	(c->x86_model == 8 && c->x86_mask >= 8))
	191	set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
	192	break;
	193	}
1da177e4	194
f90b8116 JC	195	if (c->x86_model == 10) {
	196	/* AMD Geode LX is model 10 */
	197	/* placeholder for any needed mods */
	198	break;
	199	}
	200	break;
1da177e4 LT	201	case 6: /* An Athlon/Duron */
	202
	203	/* Bit 15 of Athlon specific MSR 15, needs to be 0
	204	* to enable SSE on Palomino/Morgan/Barton CPU's.
	205	* If the BIOS didn't enable it already, enable it here.
	206	*/
	207	if (c->x86_model >= 6 && c->x86_model <= 10) {
	208	if (!cpu_has(c, X86_FEATURE_XMM)) {
	209	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
	210	rdmsr(MSR_K7_HWCR, l, h);
	211	l &= ~0x00008000;
	212	wrmsr(MSR_K7_HWCR, l, h);
	213	set_bit(X86_FEATURE_XMM, c->x86_capability);
	214	}
	215	}
	216
	217	/* It's been determined by AMD that Athlons since model 8 stepping 1
	218	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
	219	* As per AMD technical note 27212 0.2
	220	*/
	221	if ((c->x86_model == 8 && c->x86_mask>=1) \|\| (c->x86_model > 8)) {
	222	rdmsr(MSR_K7_CLK_CTL, l, h);
	223	if ((l & 0xfff00000) != 0x20000000) {
	224	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
	225	((l & 0x000fffff)\|0x20000000));
	226	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
	227	}
	228	}
	229	break;
	230	}
	231
	232	switch (c->x86) {
	233	case 15:
398cf2ab AK	234	/* Use K8 tuning for Fam10h and Fam11h */
	235	case 0x10:
	236	case 0x11:
1da177e4 LT	237	set_bit(X86_FEATURE_K8, c->x86_capability);
	238	break;
	239	case 6:
	240	set_bit(X86_FEATURE_K7, c->x86_capability);
	241	break;
	242	}
18bd057b AK	243	if (c->x86 >= 6)
18bd057b AK	244	set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
1da177e4 LT	245
1da177e4 LT	246	display_cacheinfo(c);
3dd9d514 AK	247
3dd9d514 AK	248	if (cpuid_eax(0x80000000) >= 0x80000008) {
94605eff	249	c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
3dd9d514 AK	250	}
3dd9d514 AK	251
39b3a791	252	if (cpuid_eax(0x80000000) >= 0x80000007) {
3f98bc49 AK	253	c->x86_power = cpuid_edx(0x80000007);
	254	if (c->x86_power & (1<<8))
	255	set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
39b3a791 AK	256	}
39b3a791 AK	257
b41e2939	258	#ifdef CONFIG_X86_HT
63518644	259	/*
faee9a5d AK	260	* On a AMD multi core setup the lower bits of the APIC id
faee9a5d AK	261	* distingush the cores.
63518644	262	*/
94605eff	263	if (c->x86_max_cores > 1) {
a158608b	264	int cpu = smp_processor_id();
faee9a5d AK	265	unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
	266
	267	if (bits == 0) {
	268	while ((1 << bits) < c->x86_max_cores)
	269	bits++;
	270	}
4b89aff9 RS	271	c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
4b89aff9 RS	272	c->phys_proc_id >>= bits;
63518644	273	printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
4b89aff9	274	cpu, c->x86_max_cores, c->cpu_core_id);
63518644	275	}
1da177e4	276	#endif
39b3a791	277
67cddd94 AK	278	if (cpuid_eax(0x80000000) >= 0x80000006) {
	279	if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
	280	num_cache_leaves = 4;
	281	else
	282	num_cache_leaves = 3;
	283	}
3556ddfa AK	284
	285	if (amd_apic_timer_broken())
	286	set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);
f039b754 AK	287
	288	if (c->x86 == 0x10 && !force_mwait)
	289	clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
c12ceb76 AK	290
	291	/* K6s reports MCEs but don't actually have all the MSRs */
	292	if (c->x86 < 6)
	293	clear_bit(X86_FEATURE_MCE, c->x86_capability);
1da177e4 LT	294	}
1da177e4 LT	295
e9dff0ee	296	static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
1da177e4 LT	297	{
	298	/* AMD errata T13 (order #21922) */
	299	if ((c->x86 == 6)) {
	300	if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
	301	size = 64;
	302	if (c->x86_model == 4 &&
	303	(c->x86_mask==0 \|\| c->x86_mask==1)) /* Tbird rev A1/A2 */
	304	size = 256;
	305	}
	306	return size;
	307	}
	308
95414930	309	static struct cpu_dev amd_cpu_dev __cpuinitdata = {
1da177e4 LT	310	.c_vendor = "AMD",
	311	.c_ident = { "AuthenticAMD" },
	312	.c_models = {
	313	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
	314	{
	315	[3] = "486 DX/2",
	316	[7] = "486 DX/2-WB",
	317	[8] = "486 DX/4",
	318	[9] = "486 DX/4-WB",
	319	[14] = "Am5x86-WT",
	320	[15] = "Am5x86-WB"
	321	}
	322	},
	323	},
	324	.c_init = init_amd,
1da177e4 LT	325	.c_size_cache = amd_size_cache,
	326	};
	327
	328	int __init amd_init_cpu(void)
	329	{
	330	cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
	331	return 0;
	332	}