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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/semaphore.h> |
9 | #include <asm/processor.h> | |
10 | #include <asm/i387.h> | |
11 | #include <asm/msr.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/mmu_context.h> | |
27b07da7 | 14 | #include <asm/mtrr.h> |
a03a3e28 | 15 | #include <asm/mce.h> |
1da177e4 LT |
16 | #ifdef CONFIG_X86_LOCAL_APIC |
17 | #include <asm/mpspec.h> | |
18 | #include <asm/apic.h> | |
19 | #include <mach_apic.h> | |
20 | #endif | |
62111195 | 21 | #include <asm/pda.h> |
1da177e4 LT |
22 | |
23 | #include "cpu.h" | |
24 | ||
2b932f6c JB |
25 | DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr); |
26 | EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr); | |
27 | ||
62111195 JF |
28 | struct i386_pda *_cpu_pda[NR_CPUS] __read_mostly; |
29 | EXPORT_SYMBOL(_cpu_pda); | |
30 | ||
3bc9b76b | 31 | static int cachesize_override __cpuinitdata = -1; |
4f886511 | 32 | static int disable_x86_fxsr __cpuinitdata; |
3bc9b76b | 33 | static int disable_x86_serial_nr __cpuinitdata = 1; |
4f886511 | 34 | static int disable_x86_sep __cpuinitdata; |
1da177e4 LT |
35 | |
36 | struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; | |
37 | ||
1da177e4 LT |
38 | extern int disable_pse; |
39 | ||
b4af3f7c | 40 | static void __cpuinit default_init(struct cpuinfo_x86 * c) |
1da177e4 LT |
41 | { |
42 | /* Not much we can do here... */ | |
43 | /* Check if at least it has cpuid */ | |
44 | if (c->cpuid_level == -1) { | |
45 | /* No cpuid. It must be an ancient CPU */ | |
46 | if (c->x86 == 4) | |
47 | strcpy(c->x86_model_id, "486"); | |
48 | else if (c->x86 == 3) | |
49 | strcpy(c->x86_model_id, "386"); | |
50 | } | |
51 | } | |
52 | ||
95414930 | 53 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 54 | .c_init = default_init, |
fe38d855 | 55 | .c_vendor = "Unknown", |
1da177e4 | 56 | }; |
9dbeeec9 | 57 | static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu; |
1da177e4 LT |
58 | |
59 | static int __init cachesize_setup(char *str) | |
60 | { | |
61 | get_option (&str, &cachesize_override); | |
62 | return 1; | |
63 | } | |
64 | __setup("cachesize=", cachesize_setup); | |
65 | ||
3bc9b76b | 66 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
67 | { |
68 | unsigned int *v; | |
69 | char *p, *q; | |
70 | ||
71 | if (cpuid_eax(0x80000000) < 0x80000004) | |
72 | return 0; | |
73 | ||
74 | v = (unsigned int *) c->x86_model_id; | |
75 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
76 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
77 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
78 | c->x86_model_id[48] = 0; | |
79 | ||
80 | /* Intel chips right-justify this string for some dumb reason; | |
81 | undo that brain damage */ | |
82 | p = q = &c->x86_model_id[0]; | |
83 | while ( *p == ' ' ) | |
84 | p++; | |
85 | if ( p != q ) { | |
86 | while ( *p ) | |
87 | *q++ = *p++; | |
88 | while ( q <= &c->x86_model_id[48] ) | |
89 | *q++ = '\0'; /* Zero-pad the rest */ | |
90 | } | |
91 | ||
92 | return 1; | |
93 | } | |
94 | ||
95 | ||
3bc9b76b | 96 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
97 | { |
98 | unsigned int n, dummy, ecx, edx, l2size; | |
99 | ||
100 | n = cpuid_eax(0x80000000); | |
101 | ||
102 | if (n >= 0x80000005) { | |
103 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
104 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
105 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
106 | c->x86_cache_size=(ecx>>24)+(edx>>24); | |
107 | } | |
108 | ||
109 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
110 | return; | |
111 | ||
112 | ecx = cpuid_ecx(0x80000006); | |
113 | l2size = ecx >> 16; | |
114 | ||
115 | /* do processor-specific cache resizing */ | |
116 | if (this_cpu->c_size_cache) | |
117 | l2size = this_cpu->c_size_cache(c,l2size); | |
118 | ||
119 | /* Allow user to override all this if necessary. */ | |
120 | if (cachesize_override != -1) | |
121 | l2size = cachesize_override; | |
122 | ||
123 | if ( l2size == 0 ) | |
124 | return; /* Again, no L2 cache is possible */ | |
125 | ||
126 | c->x86_cache_size = l2size; | |
127 | ||
128 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
129 | l2size, ecx & 0xFF); | |
130 | } | |
131 | ||
132 | /* Naming convention should be: <Name> [(<Codename>)] */ | |
133 | /* This table only is used unless init_<vendor>() below doesn't set it; */ | |
134 | /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ | |
135 | ||
136 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 137 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
138 | { |
139 | struct cpu_model_info *info; | |
140 | ||
141 | if ( c->x86_model >= 16 ) | |
142 | return NULL; /* Range check */ | |
143 | ||
144 | if (!this_cpu) | |
145 | return NULL; | |
146 | ||
147 | info = this_cpu->c_models; | |
148 | ||
149 | while (info && info->family) { | |
150 | if (info->family == c->x86) | |
151 | return info->model_names[c->x86_model]; | |
152 | info++; | |
153 | } | |
154 | return NULL; /* Not found */ | |
155 | } | |
156 | ||
157 | ||
3bc9b76b | 158 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
159 | { |
160 | char *v = c->x86_vendor_id; | |
161 | int i; | |
fe38d855 | 162 | static int printed; |
1da177e4 LT |
163 | |
164 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
165 | if (cpu_devs[i]) { | |
166 | if (!strcmp(v,cpu_devs[i]->c_ident[0]) || | |
167 | (cpu_devs[i]->c_ident[1] && | |
168 | !strcmp(v,cpu_devs[i]->c_ident[1]))) { | |
169 | c->x86_vendor = i; | |
170 | if (!early) | |
171 | this_cpu = cpu_devs[i]; | |
fe38d855 | 172 | return; |
1da177e4 LT |
173 | } |
174 | } | |
175 | } | |
fe38d855 CE |
176 | if (!printed) { |
177 | printed++; | |
178 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
179 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
180 | } | |
181 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
182 | this_cpu = &default_cpu; | |
1da177e4 LT |
183 | } |
184 | ||
185 | ||
186 | static int __init x86_fxsr_setup(char * s) | |
187 | { | |
8ccb3dcd | 188 | /* Tell all the other CPU's to not use it... */ |
1da177e4 | 189 | disable_x86_fxsr = 1; |
8ccb3dcd LT |
190 | |
191 | /* | |
192 | * ... and clear the bits early in the boot_cpu_data | |
193 | * so that the bootup process doesn't try to do this | |
194 | * either. | |
195 | */ | |
196 | clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability); | |
197 | clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability); | |
1da177e4 LT |
198 | return 1; |
199 | } | |
200 | __setup("nofxsr", x86_fxsr_setup); | |
201 | ||
202 | ||
4f886511 CE |
203 | static int __init x86_sep_setup(char * s) |
204 | { | |
205 | disable_x86_sep = 1; | |
206 | return 1; | |
207 | } | |
208 | __setup("nosep", x86_sep_setup); | |
209 | ||
210 | ||
1da177e4 LT |
211 | /* Standard macro to see if a specific flag is changeable */ |
212 | static inline int flag_is_changeable_p(u32 flag) | |
213 | { | |
214 | u32 f1, f2; | |
215 | ||
216 | asm("pushfl\n\t" | |
217 | "pushfl\n\t" | |
218 | "popl %0\n\t" | |
219 | "movl %0,%1\n\t" | |
220 | "xorl %2,%0\n\t" | |
221 | "pushl %0\n\t" | |
222 | "popfl\n\t" | |
223 | "pushfl\n\t" | |
224 | "popl %0\n\t" | |
225 | "popfl\n\t" | |
226 | : "=&r" (f1), "=&r" (f2) | |
227 | : "ir" (flag)); | |
228 | ||
229 | return ((f1^f2) & flag) != 0; | |
230 | } | |
231 | ||
232 | ||
233 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 234 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
235 | { |
236 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
237 | } | |
238 | ||
d7cd5611 | 239 | void __init cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 240 | { |
1da177e4 LT |
241 | /* Get vendor name */ |
242 | cpuid(0x00000000, &c->cpuid_level, | |
243 | (int *)&c->x86_vendor_id[0], | |
244 | (int *)&c->x86_vendor_id[8], | |
245 | (int *)&c->x86_vendor_id[4]); | |
246 | ||
1da177e4 LT |
247 | c->x86 = 4; |
248 | if (c->cpuid_level >= 0x00000001) { | |
249 | u32 junk, tfms, cap0, misc; | |
250 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
251 | c->x86 = (tfms >> 8) & 15; | |
252 | c->x86_model = (tfms >> 4) & 15; | |
f5f786d0 | 253 | if (c->x86 == 0xf) |
1da177e4 | 254 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 255 | if (c->x86 >= 0x6) |
1da177e4 | 256 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 LT |
257 | c->x86_mask = tfms & 15; |
258 | if (cap0 & (1<<19)) | |
259 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; | |
260 | } | |
1da177e4 LT |
261 | } |
262 | ||
d7cd5611 RR |
263 | /* Do minimum CPU detection early. |
264 | Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. | |
265 | The others are not touched to avoid unwanted side effects. | |
266 | ||
267 | WARNING: this function is only called on the BP. Don't add code here | |
268 | that is supposed to run on all CPUs. */ | |
269 | static void __init early_cpu_detect(void) | |
270 | { | |
271 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
272 | ||
273 | c->x86_cache_alignment = 32; | |
274 | ||
275 | if (!have_cpuid_p()) | |
276 | return; | |
277 | ||
278 | cpu_detect(c); | |
279 | ||
280 | get_cpu_vendor(c, 1); | |
281 | } | |
282 | ||
68bbc172 | 283 | static void __cpuinit generic_identify(struct cpuinfo_x86 * c) |
1da177e4 LT |
284 | { |
285 | u32 tfms, xlvl; | |
1e9f28fa | 286 | int ebx; |
1da177e4 LT |
287 | |
288 | if (have_cpuid_p()) { | |
289 | /* Get vendor name */ | |
290 | cpuid(0x00000000, &c->cpuid_level, | |
291 | (int *)&c->x86_vendor_id[0], | |
292 | (int *)&c->x86_vendor_id[8], | |
293 | (int *)&c->x86_vendor_id[4]); | |
294 | ||
295 | get_cpu_vendor(c, 0); | |
296 | /* Initialize the standard set of capabilities */ | |
297 | /* Note that the vendor-specific code below might override */ | |
298 | ||
299 | /* Intel-defined flags: level 0x00000001 */ | |
300 | if ( c->cpuid_level >= 0x00000001 ) { | |
301 | u32 capability, excap; | |
1e9f28fa | 302 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
1da177e4 LT |
303 | c->x86_capability[0] = capability; |
304 | c->x86_capability[4] = excap; | |
305 | c->x86 = (tfms >> 8) & 15; | |
306 | c->x86_model = (tfms >> 4) & 15; | |
ed2da193 | 307 | if (c->x86 == 0xf) |
1da177e4 | 308 | c->x86 += (tfms >> 20) & 0xff; |
ed2da193 | 309 | if (c->x86 >= 0x6) |
1da177e4 | 310 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 311 | c->x86_mask = tfms & 15; |
96c52749 | 312 | #ifdef CONFIG_X86_HT |
1e9f28fa SS |
313 | c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); |
314 | #else | |
315 | c->apicid = (ebx >> 24) & 0xFF; | |
316 | #endif | |
770d132f AK |
317 | if (c->x86_capability[0] & (1<<19)) |
318 | c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; | |
1da177e4 LT |
319 | } else { |
320 | /* Have CPUID level 0 only - unheard of */ | |
321 | c->x86 = 4; | |
322 | } | |
323 | ||
324 | /* AMD-defined flags: level 0x80000001 */ | |
325 | xlvl = cpuid_eax(0x80000000); | |
326 | if ( (xlvl & 0xffff0000) == 0x80000000 ) { | |
327 | if ( xlvl >= 0x80000001 ) { | |
328 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
329 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
330 | } | |
331 | if ( xlvl >= 0x80000004 ) | |
332 | get_model_name(c); /* Default name */ | |
333 | } | |
334 | } | |
2e664aa2 AK |
335 | |
336 | early_intel_workaround(c); | |
337 | ||
338 | #ifdef CONFIG_X86_HT | |
4b89aff9 | 339 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
2e664aa2 | 340 | #endif |
1da177e4 LT |
341 | } |
342 | ||
3bc9b76b | 343 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 LT |
344 | { |
345 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { | |
346 | /* Disable processor serial number */ | |
347 | unsigned long lo,hi; | |
348 | rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
349 | lo |= 0x200000; | |
350 | wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
351 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
352 | clear_bit(X86_FEATURE_PN, c->x86_capability); | |
353 | ||
354 | /* Disabling the serial number may affect the cpuid level */ | |
355 | c->cpuid_level = cpuid_eax(0); | |
356 | } | |
357 | } | |
358 | ||
359 | static int __init x86_serial_nr_setup(char *s) | |
360 | { | |
361 | disable_x86_serial_nr = 0; | |
362 | return 1; | |
363 | } | |
364 | __setup("serialnumber", x86_serial_nr_setup); | |
365 | ||
366 | ||
367 | ||
368 | /* | |
369 | * This does the hard work of actually picking apart the CPU stuff... | |
370 | */ | |
3bc9b76b | 371 | void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
372 | { |
373 | int i; | |
374 | ||
375 | c->loops_per_jiffy = loops_per_jiffy; | |
376 | c->x86_cache_size = -1; | |
377 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
378 | c->cpuid_level = -1; /* CPUID not detected */ | |
379 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
380 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
381 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 382 | c->x86_max_cores = 1; |
770d132f | 383 | c->x86_clflush_size = 32; |
1da177e4 LT |
384 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
385 | ||
386 | if (!have_cpuid_p()) { | |
387 | /* First of all, decide if this is a 486 or higher */ | |
388 | /* It's a 486 if we can modify the AC flag */ | |
389 | if ( flag_is_changeable_p(X86_EFLAGS_AC) ) | |
390 | c->x86 = 4; | |
391 | else | |
392 | c->x86 = 3; | |
393 | } | |
394 | ||
395 | generic_identify(c); | |
396 | ||
397 | printk(KERN_DEBUG "CPU: After generic identify, caps:"); | |
398 | for (i = 0; i < NCAPINTS; i++) | |
399 | printk(" %08lx", c->x86_capability[i]); | |
400 | printk("\n"); | |
401 | ||
402 | if (this_cpu->c_identify) { | |
403 | this_cpu->c_identify(c); | |
404 | ||
405 | printk(KERN_DEBUG "CPU: After vendor identify, caps:"); | |
406 | for (i = 0; i < NCAPINTS; i++) | |
407 | printk(" %08lx", c->x86_capability[i]); | |
408 | printk("\n"); | |
409 | } | |
410 | ||
411 | /* | |
412 | * Vendor-specific initialization. In this section we | |
413 | * canonicalize the feature flags, meaning if there are | |
414 | * features a certain CPU supports which CPUID doesn't | |
415 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
416 | * we handle them here. | |
417 | * | |
418 | * At the end of this section, c->x86_capability better | |
419 | * indicate the features this CPU genuinely supports! | |
420 | */ | |
421 | if (this_cpu->c_init) | |
422 | this_cpu->c_init(c); | |
423 | ||
424 | /* Disable the PN if appropriate */ | |
425 | squash_the_stupid_serial_number(c); | |
426 | ||
427 | /* | |
428 | * The vendor-specific functions might have changed features. Now | |
429 | * we do "generic changes." | |
430 | */ | |
431 | ||
432 | /* TSC disabled? */ | |
433 | if ( tsc_disable ) | |
434 | clear_bit(X86_FEATURE_TSC, c->x86_capability); | |
435 | ||
436 | /* FXSR disabled? */ | |
437 | if (disable_x86_fxsr) { | |
438 | clear_bit(X86_FEATURE_FXSR, c->x86_capability); | |
439 | clear_bit(X86_FEATURE_XMM, c->x86_capability); | |
440 | } | |
441 | ||
4f886511 CE |
442 | /* SEP disabled? */ |
443 | if (disable_x86_sep) | |
444 | clear_bit(X86_FEATURE_SEP, c->x86_capability); | |
445 | ||
1da177e4 LT |
446 | if (disable_pse) |
447 | clear_bit(X86_FEATURE_PSE, c->x86_capability); | |
448 | ||
449 | /* If the model name is still unset, do table lookup. */ | |
450 | if ( !c->x86_model_id[0] ) { | |
451 | char *p; | |
452 | p = table_lookup_model(c); | |
453 | if ( p ) | |
454 | strcpy(c->x86_model_id, p); | |
455 | else | |
456 | /* Last resort... */ | |
457 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 458 | c->x86, c->x86_model); |
1da177e4 LT |
459 | } |
460 | ||
461 | /* Now the feature flags better reflect actual CPU features! */ | |
462 | ||
463 | printk(KERN_DEBUG "CPU: After all inits, caps:"); | |
464 | for (i = 0; i < NCAPINTS; i++) | |
465 | printk(" %08lx", c->x86_capability[i]); | |
466 | printk("\n"); | |
467 | ||
468 | /* | |
469 | * On SMP, boot_cpu_data holds the common feature set between | |
470 | * all CPUs; so make sure that we indicate which features are | |
471 | * common between the CPUs. The first time this routine gets | |
472 | * executed, c == &boot_cpu_data. | |
473 | */ | |
474 | if ( c != &boot_cpu_data ) { | |
475 | /* AND the already accumulated flags with these */ | |
476 | for ( i = 0 ; i < NCAPINTS ; i++ ) | |
477 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
478 | } | |
479 | ||
480 | /* Init Machine Check Exception if available. */ | |
1da177e4 | 481 | mcheck_init(c); |
31ab269a | 482 | |
6fe940d6 LS |
483 | if (c == &boot_cpu_data) |
484 | sysenter_setup(); | |
485 | enable_sep_cpu(); | |
3b520b23 SL |
486 | |
487 | if (c == &boot_cpu_data) | |
488 | mtrr_bp_init(); | |
489 | else | |
490 | mtrr_ap_init(); | |
1da177e4 LT |
491 | } |
492 | ||
493 | #ifdef CONFIG_X86_HT | |
3bc9b76b | 494 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
495 | { |
496 | u32 eax, ebx, ecx, edx; | |
94605eff | 497 | int index_msb, core_bits; |
1da177e4 | 498 | |
94605eff SS |
499 | cpuid(1, &eax, &ebx, &ecx, &edx); |
500 | ||
63518644 | 501 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
502 | return; |
503 | ||
1da177e4 LT |
504 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
505 | ||
506 | if (smp_num_siblings == 1) { | |
507 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
508 | } else if (smp_num_siblings > 1 ) { | |
1da177e4 LT |
509 | |
510 | if (smp_num_siblings > NR_CPUS) { | |
4b89aff9 RS |
511 | printk(KERN_WARNING "CPU: Unsupported number of the " |
512 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
513 | smp_num_siblings = 1; |
514 | return; | |
515 | } | |
94605eff SS |
516 | |
517 | index_msb = get_count_order(smp_num_siblings); | |
4b89aff9 | 518 | c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); |
1da177e4 LT |
519 | |
520 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
4b89aff9 | 521 | c->phys_proc_id); |
3dd9d514 | 522 | |
94605eff | 523 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 524 | |
94605eff | 525 | index_msb = get_count_order(smp_num_siblings) ; |
3dd9d514 | 526 | |
94605eff | 527 | core_bits = get_count_order(c->x86_max_cores); |
3dd9d514 | 528 | |
4b89aff9 | 529 | c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) & |
94605eff | 530 | ((1 << core_bits) - 1); |
3dd9d514 | 531 | |
94605eff | 532 | if (c->x86_max_cores > 1) |
3dd9d514 | 533 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", |
4b89aff9 | 534 | c->cpu_core_id); |
1da177e4 LT |
535 | } |
536 | } | |
537 | #endif | |
538 | ||
3bc9b76b | 539 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
540 | { |
541 | char *vendor = NULL; | |
542 | ||
543 | if (c->x86_vendor < X86_VENDOR_NUM) | |
544 | vendor = this_cpu->c_vendor; | |
545 | else if (c->cpuid_level >= 0) | |
546 | vendor = c->x86_vendor_id; | |
547 | ||
548 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
549 | printk("%s ", vendor); | |
550 | ||
551 | if (!c->x86_model_id[0]) | |
552 | printk("%d86", c->x86); | |
553 | else | |
554 | printk("%s", c->x86_model_id); | |
555 | ||
556 | if (c->x86_mask || c->cpuid_level >= 0) | |
557 | printk(" stepping %02x\n", c->x86_mask); | |
558 | else | |
559 | printk("\n"); | |
560 | } | |
561 | ||
3bc9b76b | 562 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 LT |
563 | |
564 | /* This is hacky. :) | |
565 | * We're emulating future behavior. | |
566 | * In the future, the cpu-specific init functions will be called implicitly | |
567 | * via the magic of initcalls. | |
568 | * They will insert themselves into the cpu_devs structure. | |
569 | * Then, when cpu_init() is called, we can just iterate over that array. | |
570 | */ | |
571 | ||
572 | extern int intel_cpu_init(void); | |
573 | extern int cyrix_init_cpu(void); | |
574 | extern int nsc_init_cpu(void); | |
575 | extern int amd_init_cpu(void); | |
576 | extern int centaur_init_cpu(void); | |
577 | extern int transmeta_init_cpu(void); | |
578 | extern int rise_init_cpu(void); | |
579 | extern int nexgen_init_cpu(void); | |
580 | extern int umc_init_cpu(void); | |
581 | ||
582 | void __init early_cpu_init(void) | |
583 | { | |
584 | intel_cpu_init(); | |
585 | cyrix_init_cpu(); | |
586 | nsc_init_cpu(); | |
587 | amd_init_cpu(); | |
588 | centaur_init_cpu(); | |
589 | transmeta_init_cpu(); | |
590 | rise_init_cpu(); | |
591 | nexgen_init_cpu(); | |
592 | umc_init_cpu(); | |
593 | early_cpu_detect(); | |
594 | ||
595 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
596 | /* pse is not compatible with on-the-fly unmapping, | |
597 | * disable it even if the cpus claim to support it. | |
598 | */ | |
599 | clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability); | |
600 | disable_pse = 1; | |
601 | #endif | |
602 | } | |
62111195 | 603 | |
f95d47ca JF |
604 | /* Make sure %gs is initialized properly in idle threads */ |
605 | struct pt_regs * __devinit idle_regs(struct pt_regs *regs) | |
606 | { | |
607 | memset(regs, 0, sizeof(struct pt_regs)); | |
464d1a78 | 608 | regs->xfs = __KERNEL_PDA; |
f95d47ca JF |
609 | return regs; |
610 | } | |
611 | ||
ba10650a | 612 | static __cpuinit int alloc_gdt(int cpu) |
1da177e4 | 613 | { |
2b932f6c | 614 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
62111195 JF |
615 | struct desc_struct *gdt; |
616 | struct i386_pda *pda; | |
1da177e4 | 617 | |
62111195 JF |
618 | gdt = (struct desc_struct *)cpu_gdt_descr->address; |
619 | pda = cpu_pda(cpu); | |
1da177e4 | 620 | |
2b932f6c JB |
621 | /* |
622 | * This is a horrible hack to allocate the GDT. The problem | |
623 | * is that cpu_init() is called really early for the boot CPU | |
624 | * (and hence needs bootmem) but much later for the secondary | |
625 | * CPUs, when bootmem will have gone away | |
626 | */ | |
627 | if (NODE_DATA(0)->bdata->node_bootmem_map) { | |
62111195 JF |
628 | BUG_ON(gdt != NULL || pda != NULL); |
629 | ||
630 | gdt = alloc_bootmem_pages(PAGE_SIZE); | |
631 | pda = alloc_bootmem(sizeof(*pda)); | |
632 | /* alloc_bootmem(_pages) panics on failure, so no check */ | |
633 | ||
2b932f6c | 634 | memset(gdt, 0, PAGE_SIZE); |
62111195 | 635 | memset(pda, 0, sizeof(*pda)); |
2b932f6c | 636 | } else { |
62111195 JF |
637 | /* GDT and PDA might already have been allocated if |
638 | this is a CPU hotplug re-insertion. */ | |
639 | if (gdt == NULL) | |
640 | gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL); | |
641 | ||
642 | if (pda == NULL) | |
643 | pda = kmalloc_node(sizeof(*pda), GFP_KERNEL, cpu_to_node(cpu)); | |
644 | ||
645 | if (unlikely(!gdt || !pda)) { | |
646 | free_pages((unsigned long)gdt, 0); | |
647 | kfree(pda); | |
648 | return 0; | |
2b932f6c JB |
649 | } |
650 | } | |
62111195 JF |
651 | |
652 | cpu_gdt_descr->address = (unsigned long)gdt; | |
653 | cpu_pda(cpu) = pda; | |
654 | ||
655 | return 1; | |
656 | } | |
657 | ||
658 | /* Initial PDA used by boot CPU */ | |
659 | struct i386_pda boot_pda = { | |
660 | ._pda = &boot_pda, | |
b2938f88 | 661 | .cpu_number = 0, |
ec7fcaab | 662 | .pcurrent = &init_task, |
62111195 JF |
663 | }; |
664 | ||
464d1a78 | 665 | static inline void set_kernel_fs(void) |
f95d47ca | 666 | { |
464d1a78 | 667 | /* Set %fs for this CPU's PDA. Memory clobber is to create a |
f95d47ca JF |
668 | barrier with respect to any PDA operations, so the compiler |
669 | doesn't move any before here. */ | |
464d1a78 | 670 | asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_PDA) : "memory"); |
f95d47ca JF |
671 | } |
672 | ||
62111195 JF |
673 | /* Initialize the CPU's GDT and PDA. The boot CPU does this for |
674 | itself, but secondaries find this done for them. */ | |
675 | __cpuinit int init_gdt(int cpu, struct task_struct *idle) | |
676 | { | |
677 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); | |
678 | struct desc_struct *gdt; | |
679 | struct i386_pda *pda; | |
680 | ||
681 | /* For non-boot CPUs, the GDT and PDA should already have been | |
682 | allocated. */ | |
683 | if (!alloc_gdt(cpu)) { | |
684 | printk(KERN_CRIT "CPU%d failed to allocate GDT or PDA\n", cpu); | |
685 | return 0; | |
686 | } | |
687 | ||
688 | gdt = (struct desc_struct *)cpu_gdt_descr->address; | |
689 | pda = cpu_pda(cpu); | |
690 | ||
691 | BUG_ON(gdt == NULL || pda == NULL); | |
692 | ||
1da177e4 LT |
693 | /* |
694 | * Initialize the per-CPU GDT with the boot GDT, | |
695 | * and set up the GDT descriptor: | |
696 | */ | |
251e6912 | 697 | memcpy(gdt, cpu_gdt_table, GDT_SIZE); |
2b932f6c | 698 | cpu_gdt_descr->size = GDT_SIZE - 1; |
1da177e4 | 699 | |
62111195 JF |
700 | pack_descriptor((u32 *)&gdt[GDT_ENTRY_PDA].a, |
701 | (u32 *)&gdt[GDT_ENTRY_PDA].b, | |
702 | (unsigned long)pda, sizeof(*pda) - 1, | |
703 | 0x80 | DESCTYPE_S | 0x2, 0); /* present read-write data segment */ | |
704 | ||
705 | memset(pda, 0, sizeof(*pda)); | |
706 | pda->_pda = pda; | |
b2938f88 | 707 | pda->cpu_number = cpu; |
ec7fcaab | 708 | pda->pcurrent = idle; |
62111195 JF |
709 | |
710 | return 1; | |
711 | } | |
712 | ||
9ee79a3d | 713 | void __cpuinit cpu_set_gdt(int cpu) |
62111195 | 714 | { |
62111195 JF |
715 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
716 | ||
717 | /* Reinit these anyway, even if they've already been done (on | |
718 | the boot CPU, this will transition from the boot gdt+pda to | |
719 | the real ones). */ | |
2b932f6c | 720 | load_gdt(cpu_gdt_descr); |
464d1a78 | 721 | set_kernel_fs(); |
9ee79a3d JB |
722 | } |
723 | ||
724 | /* Common CPU init for both boot and secondary CPUs */ | |
725 | static void __cpuinit _cpu_init(int cpu, struct task_struct *curr) | |
726 | { | |
727 | struct tss_struct * t = &per_cpu(init_tss, cpu); | |
728 | struct thread_struct *thread = &curr->thread; | |
62111195 JF |
729 | |
730 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
731 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
732 | for (;;) local_irq_enable(); | |
733 | } | |
734 | ||
735 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
736 | ||
737 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
738 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
739 | if (tsc_disable && cpu_has_tsc) { | |
740 | printk(KERN_NOTICE "Disabling TSC...\n"); | |
741 | /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/ | |
742 | clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability); | |
743 | set_in_cr4(X86_CR4_TSD); | |
744 | } | |
745 | ||
4d37e7e3 | 746 | load_idt(&idt_descr); |
1da177e4 | 747 | |
1da177e4 LT |
748 | /* |
749 | * Set up and load the per-CPU TSS and LDT | |
750 | */ | |
751 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
752 | curr->active_mm = &init_mm; |
753 | if (curr->mm) | |
754 | BUG(); | |
755 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 LT |
756 | |
757 | load_esp0(t, thread); | |
758 | set_tss_desc(cpu,t); | |
759 | load_TR_desc(); | |
760 | load_LDT(&init_mm.context); | |
761 | ||
22c4e308 | 762 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
763 | /* Set up doublefault TSS pointer in the GDT */ |
764 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 765 | #endif |
1da177e4 | 766 | |
464d1a78 JF |
767 | /* Clear %gs. */ |
768 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
769 | |
770 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
771 | set_debugreg(0, 0); |
772 | set_debugreg(0, 1); | |
773 | set_debugreg(0, 2); | |
774 | set_debugreg(0, 3); | |
775 | set_debugreg(0, 6); | |
776 | set_debugreg(0, 7); | |
1da177e4 LT |
777 | |
778 | /* | |
779 | * Force FPU initialization: | |
780 | */ | |
781 | current_thread_info()->status = 0; | |
782 | clear_used_math(); | |
783 | mxcsr_feature_mask_init(); | |
784 | } | |
e1367daf | 785 | |
62111195 JF |
786 | /* Entrypoint to initialize secondary CPU */ |
787 | void __cpuinit secondary_cpu_init(void) | |
788 | { | |
789 | int cpu = smp_processor_id(); | |
790 | struct task_struct *curr = current; | |
791 | ||
792 | _cpu_init(cpu, curr); | |
793 | } | |
794 | ||
795 | /* | |
796 | * cpu_init() initializes state that is per-CPU. Some data is already | |
797 | * initialized (naturally) in the bootstrap process, such as the GDT | |
798 | * and IDT. We reload them nevertheless, this function acts as a | |
799 | * 'CPU state barrier', nothing should get across. | |
800 | */ | |
801 | void __cpuinit cpu_init(void) | |
802 | { | |
803 | int cpu = smp_processor_id(); | |
804 | struct task_struct *curr = current; | |
805 | ||
806 | /* Set up the real GDT and PDA, so we can transition from the | |
807 | boot versions. */ | |
808 | if (!init_gdt(cpu, curr)) { | |
809 | /* failed to allocate something; not much we can do... */ | |
810 | for (;;) | |
811 | local_irq_enable(); | |
812 | } | |
813 | ||
9ee79a3d | 814 | cpu_set_gdt(cpu); |
62111195 JF |
815 | _cpu_init(cpu, curr); |
816 | } | |
817 | ||
e1367daf | 818 | #ifdef CONFIG_HOTPLUG_CPU |
3bc9b76b | 819 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
820 | { |
821 | int cpu = raw_smp_processor_id(); | |
822 | cpu_clear(cpu, cpu_initialized); | |
823 | ||
824 | /* lazy TLB state */ | |
825 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
826 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
827 | } | |
828 | #endif |