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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/semaphore.h> |
9 | #include <asm/processor.h> | |
10 | #include <asm/i387.h> | |
11 | #include <asm/msr.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/mmu_context.h> | |
14 | #ifdef CONFIG_X86_LOCAL_APIC | |
15 | #include <asm/mpspec.h> | |
16 | #include <asm/apic.h> | |
17 | #include <mach_apic.h> | |
18 | #endif | |
19 | ||
20 | #include "cpu.h" | |
21 | ||
2b932f6c JB |
22 | DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr); |
23 | EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr); | |
24 | ||
1da177e4 LT |
25 | DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]); |
26 | EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack); | |
27 | ||
0bb3184d LS |
28 | static int cachesize_override __devinitdata = -1; |
29 | static int disable_x86_fxsr __devinitdata = 0; | |
30 | static int disable_x86_serial_nr __devinitdata = 1; | |
1da177e4 LT |
31 | |
32 | struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; | |
33 | ||
1da177e4 LT |
34 | extern int disable_pse; |
35 | ||
36 | static void default_init(struct cpuinfo_x86 * c) | |
37 | { | |
38 | /* Not much we can do here... */ | |
39 | /* Check if at least it has cpuid */ | |
40 | if (c->cpuid_level == -1) { | |
41 | /* No cpuid. It must be an ancient CPU */ | |
42 | if (c->x86 == 4) | |
43 | strcpy(c->x86_model_id, "486"); | |
44 | else if (c->x86 == 3) | |
45 | strcpy(c->x86_model_id, "386"); | |
46 | } | |
47 | } | |
48 | ||
49 | static struct cpu_dev default_cpu = { | |
50 | .c_init = default_init, | |
fe38d855 | 51 | .c_vendor = "Unknown", |
1da177e4 LT |
52 | }; |
53 | static struct cpu_dev * this_cpu = &default_cpu; | |
54 | ||
55 | static int __init cachesize_setup(char *str) | |
56 | { | |
57 | get_option (&str, &cachesize_override); | |
58 | return 1; | |
59 | } | |
60 | __setup("cachesize=", cachesize_setup); | |
61 | ||
0bb3184d | 62 | int __devinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
63 | { |
64 | unsigned int *v; | |
65 | char *p, *q; | |
66 | ||
67 | if (cpuid_eax(0x80000000) < 0x80000004) | |
68 | return 0; | |
69 | ||
70 | v = (unsigned int *) c->x86_model_id; | |
71 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
72 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
73 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
74 | c->x86_model_id[48] = 0; | |
75 | ||
76 | /* Intel chips right-justify this string for some dumb reason; | |
77 | undo that brain damage */ | |
78 | p = q = &c->x86_model_id[0]; | |
79 | while ( *p == ' ' ) | |
80 | p++; | |
81 | if ( p != q ) { | |
82 | while ( *p ) | |
83 | *q++ = *p++; | |
84 | while ( q <= &c->x86_model_id[48] ) | |
85 | *q++ = '\0'; /* Zero-pad the rest */ | |
86 | } | |
87 | ||
88 | return 1; | |
89 | } | |
90 | ||
91 | ||
0bb3184d | 92 | void __devinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
93 | { |
94 | unsigned int n, dummy, ecx, edx, l2size; | |
95 | ||
96 | n = cpuid_eax(0x80000000); | |
97 | ||
98 | if (n >= 0x80000005) { | |
99 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
100 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
101 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
102 | c->x86_cache_size=(ecx>>24)+(edx>>24); | |
103 | } | |
104 | ||
105 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
106 | return; | |
107 | ||
108 | ecx = cpuid_ecx(0x80000006); | |
109 | l2size = ecx >> 16; | |
110 | ||
111 | /* do processor-specific cache resizing */ | |
112 | if (this_cpu->c_size_cache) | |
113 | l2size = this_cpu->c_size_cache(c,l2size); | |
114 | ||
115 | /* Allow user to override all this if necessary. */ | |
116 | if (cachesize_override != -1) | |
117 | l2size = cachesize_override; | |
118 | ||
119 | if ( l2size == 0 ) | |
120 | return; /* Again, no L2 cache is possible */ | |
121 | ||
122 | c->x86_cache_size = l2size; | |
123 | ||
124 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
125 | l2size, ecx & 0xFF); | |
126 | } | |
127 | ||
128 | /* Naming convention should be: <Name> [(<Codename>)] */ | |
129 | /* This table only is used unless init_<vendor>() below doesn't set it; */ | |
130 | /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ | |
131 | ||
132 | /* Look up CPU names by table lookup. */ | |
0bb3184d | 133 | static char __devinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
134 | { |
135 | struct cpu_model_info *info; | |
136 | ||
137 | if ( c->x86_model >= 16 ) | |
138 | return NULL; /* Range check */ | |
139 | ||
140 | if (!this_cpu) | |
141 | return NULL; | |
142 | ||
143 | info = this_cpu->c_models; | |
144 | ||
145 | while (info && info->family) { | |
146 | if (info->family == c->x86) | |
147 | return info->model_names[c->x86_model]; | |
148 | info++; | |
149 | } | |
150 | return NULL; /* Not found */ | |
151 | } | |
152 | ||
153 | ||
672289e9 | 154 | static void __devinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
155 | { |
156 | char *v = c->x86_vendor_id; | |
157 | int i; | |
fe38d855 | 158 | static int printed; |
1da177e4 LT |
159 | |
160 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
161 | if (cpu_devs[i]) { | |
162 | if (!strcmp(v,cpu_devs[i]->c_ident[0]) || | |
163 | (cpu_devs[i]->c_ident[1] && | |
164 | !strcmp(v,cpu_devs[i]->c_ident[1]))) { | |
165 | c->x86_vendor = i; | |
166 | if (!early) | |
167 | this_cpu = cpu_devs[i]; | |
fe38d855 | 168 | return; |
1da177e4 LT |
169 | } |
170 | } | |
171 | } | |
fe38d855 CE |
172 | if (!printed) { |
173 | printed++; | |
174 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
175 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
176 | } | |
177 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
178 | this_cpu = &default_cpu; | |
1da177e4 LT |
179 | } |
180 | ||
181 | ||
182 | static int __init x86_fxsr_setup(char * s) | |
183 | { | |
184 | disable_x86_fxsr = 1; | |
185 | return 1; | |
186 | } | |
187 | __setup("nofxsr", x86_fxsr_setup); | |
188 | ||
189 | ||
190 | /* Standard macro to see if a specific flag is changeable */ | |
191 | static inline int flag_is_changeable_p(u32 flag) | |
192 | { | |
193 | u32 f1, f2; | |
194 | ||
195 | asm("pushfl\n\t" | |
196 | "pushfl\n\t" | |
197 | "popl %0\n\t" | |
198 | "movl %0,%1\n\t" | |
199 | "xorl %2,%0\n\t" | |
200 | "pushl %0\n\t" | |
201 | "popfl\n\t" | |
202 | "pushfl\n\t" | |
203 | "popl %0\n\t" | |
204 | "popfl\n\t" | |
205 | : "=&r" (f1), "=&r" (f2) | |
206 | : "ir" (flag)); | |
207 | ||
208 | return ((f1^f2) & flag) != 0; | |
209 | } | |
210 | ||
211 | ||
212 | /* Probe for the CPUID instruction */ | |
0bb3184d | 213 | static int __devinit have_cpuid_p(void) |
1da177e4 LT |
214 | { |
215 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
216 | } | |
217 | ||
218 | /* Do minimum CPU detection early. | |
219 | Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. | |
2e664aa2 AK |
220 | The others are not touched to avoid unwanted side effects. |
221 | ||
222 | WARNING: this function is only called on the BP. Don't add code here | |
223 | that is supposed to run on all CPUs. */ | |
1da177e4 LT |
224 | static void __init early_cpu_detect(void) |
225 | { | |
226 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
227 | ||
228 | c->x86_cache_alignment = 32; | |
229 | ||
230 | if (!have_cpuid_p()) | |
231 | return; | |
232 | ||
233 | /* Get vendor name */ | |
234 | cpuid(0x00000000, &c->cpuid_level, | |
235 | (int *)&c->x86_vendor_id[0], | |
236 | (int *)&c->x86_vendor_id[8], | |
237 | (int *)&c->x86_vendor_id[4]); | |
238 | ||
239 | get_cpu_vendor(c, 1); | |
240 | ||
241 | c->x86 = 4; | |
242 | if (c->cpuid_level >= 0x00000001) { | |
243 | u32 junk, tfms, cap0, misc; | |
244 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
245 | c->x86 = (tfms >> 8) & 15; | |
246 | c->x86_model = (tfms >> 4) & 15; | |
f5f786d0 | 247 | if (c->x86 == 0xf) |
1da177e4 | 248 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 249 | if (c->x86 >= 0x6) |
1da177e4 | 250 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 LT |
251 | c->x86_mask = tfms & 15; |
252 | if (cap0 & (1<<19)) | |
253 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; | |
254 | } | |
1da177e4 LT |
255 | } |
256 | ||
0bb3184d | 257 | void __devinit generic_identify(struct cpuinfo_x86 * c) |
1da177e4 LT |
258 | { |
259 | u32 tfms, xlvl; | |
260 | int junk; | |
261 | ||
262 | if (have_cpuid_p()) { | |
263 | /* Get vendor name */ | |
264 | cpuid(0x00000000, &c->cpuid_level, | |
265 | (int *)&c->x86_vendor_id[0], | |
266 | (int *)&c->x86_vendor_id[8], | |
267 | (int *)&c->x86_vendor_id[4]); | |
268 | ||
269 | get_cpu_vendor(c, 0); | |
270 | /* Initialize the standard set of capabilities */ | |
271 | /* Note that the vendor-specific code below might override */ | |
272 | ||
273 | /* Intel-defined flags: level 0x00000001 */ | |
274 | if ( c->cpuid_level >= 0x00000001 ) { | |
275 | u32 capability, excap; | |
276 | cpuid(0x00000001, &tfms, &junk, &excap, &capability); | |
277 | c->x86_capability[0] = capability; | |
278 | c->x86_capability[4] = excap; | |
279 | c->x86 = (tfms >> 8) & 15; | |
280 | c->x86_model = (tfms >> 4) & 15; | |
ed2da193 | 281 | if (c->x86 == 0xf) |
1da177e4 | 282 | c->x86 += (tfms >> 20) & 0xff; |
ed2da193 | 283 | if (c->x86 >= 0x6) |
1da177e4 | 284 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 LT |
285 | c->x86_mask = tfms & 15; |
286 | } else { | |
287 | /* Have CPUID level 0 only - unheard of */ | |
288 | c->x86 = 4; | |
289 | } | |
290 | ||
291 | /* AMD-defined flags: level 0x80000001 */ | |
292 | xlvl = cpuid_eax(0x80000000); | |
293 | if ( (xlvl & 0xffff0000) == 0x80000000 ) { | |
294 | if ( xlvl >= 0x80000001 ) { | |
295 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
296 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
297 | } | |
298 | if ( xlvl >= 0x80000004 ) | |
299 | get_model_name(c); /* Default name */ | |
300 | } | |
301 | } | |
2e664aa2 AK |
302 | |
303 | early_intel_workaround(c); | |
304 | ||
305 | #ifdef CONFIG_X86_HT | |
306 | phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff; | |
307 | #endif | |
1da177e4 LT |
308 | } |
309 | ||
0bb3184d | 310 | static void __devinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 LT |
311 | { |
312 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { | |
313 | /* Disable processor serial number */ | |
314 | unsigned long lo,hi; | |
315 | rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
316 | lo |= 0x200000; | |
317 | wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
318 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
319 | clear_bit(X86_FEATURE_PN, c->x86_capability); | |
320 | ||
321 | /* Disabling the serial number may affect the cpuid level */ | |
322 | c->cpuid_level = cpuid_eax(0); | |
323 | } | |
324 | } | |
325 | ||
326 | static int __init x86_serial_nr_setup(char *s) | |
327 | { | |
328 | disable_x86_serial_nr = 0; | |
329 | return 1; | |
330 | } | |
331 | __setup("serialnumber", x86_serial_nr_setup); | |
332 | ||
333 | ||
334 | ||
335 | /* | |
336 | * This does the hard work of actually picking apart the CPU stuff... | |
337 | */ | |
0bb3184d | 338 | void __devinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
339 | { |
340 | int i; | |
341 | ||
342 | c->loops_per_jiffy = loops_per_jiffy; | |
343 | c->x86_cache_size = -1; | |
344 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
345 | c->cpuid_level = -1; /* CPUID not detected */ | |
346 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
347 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
348 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 349 | c->x86_max_cores = 1; |
1da177e4 LT |
350 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
351 | ||
352 | if (!have_cpuid_p()) { | |
353 | /* First of all, decide if this is a 486 or higher */ | |
354 | /* It's a 486 if we can modify the AC flag */ | |
355 | if ( flag_is_changeable_p(X86_EFLAGS_AC) ) | |
356 | c->x86 = 4; | |
357 | else | |
358 | c->x86 = 3; | |
359 | } | |
360 | ||
361 | generic_identify(c); | |
362 | ||
363 | printk(KERN_DEBUG "CPU: After generic identify, caps:"); | |
364 | for (i = 0; i < NCAPINTS; i++) | |
365 | printk(" %08lx", c->x86_capability[i]); | |
366 | printk("\n"); | |
367 | ||
368 | if (this_cpu->c_identify) { | |
369 | this_cpu->c_identify(c); | |
370 | ||
371 | printk(KERN_DEBUG "CPU: After vendor identify, caps:"); | |
372 | for (i = 0; i < NCAPINTS; i++) | |
373 | printk(" %08lx", c->x86_capability[i]); | |
374 | printk("\n"); | |
375 | } | |
376 | ||
377 | /* | |
378 | * Vendor-specific initialization. In this section we | |
379 | * canonicalize the feature flags, meaning if there are | |
380 | * features a certain CPU supports which CPUID doesn't | |
381 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
382 | * we handle them here. | |
383 | * | |
384 | * At the end of this section, c->x86_capability better | |
385 | * indicate the features this CPU genuinely supports! | |
386 | */ | |
387 | if (this_cpu->c_init) | |
388 | this_cpu->c_init(c); | |
389 | ||
390 | /* Disable the PN if appropriate */ | |
391 | squash_the_stupid_serial_number(c); | |
392 | ||
393 | /* | |
394 | * The vendor-specific functions might have changed features. Now | |
395 | * we do "generic changes." | |
396 | */ | |
397 | ||
398 | /* TSC disabled? */ | |
399 | if ( tsc_disable ) | |
400 | clear_bit(X86_FEATURE_TSC, c->x86_capability); | |
401 | ||
402 | /* FXSR disabled? */ | |
403 | if (disable_x86_fxsr) { | |
404 | clear_bit(X86_FEATURE_FXSR, c->x86_capability); | |
405 | clear_bit(X86_FEATURE_XMM, c->x86_capability); | |
406 | } | |
407 | ||
408 | if (disable_pse) | |
409 | clear_bit(X86_FEATURE_PSE, c->x86_capability); | |
410 | ||
411 | /* If the model name is still unset, do table lookup. */ | |
412 | if ( !c->x86_model_id[0] ) { | |
413 | char *p; | |
414 | p = table_lookup_model(c); | |
415 | if ( p ) | |
416 | strcpy(c->x86_model_id, p); | |
417 | else | |
418 | /* Last resort... */ | |
419 | sprintf(c->x86_model_id, "%02x/%02x", | |
420 | c->x86_vendor, c->x86_model); | |
421 | } | |
422 | ||
423 | /* Now the feature flags better reflect actual CPU features! */ | |
424 | ||
425 | printk(KERN_DEBUG "CPU: After all inits, caps:"); | |
426 | for (i = 0; i < NCAPINTS; i++) | |
427 | printk(" %08lx", c->x86_capability[i]); | |
428 | printk("\n"); | |
429 | ||
430 | /* | |
431 | * On SMP, boot_cpu_data holds the common feature set between | |
432 | * all CPUs; so make sure that we indicate which features are | |
433 | * common between the CPUs. The first time this routine gets | |
434 | * executed, c == &boot_cpu_data. | |
435 | */ | |
436 | if ( c != &boot_cpu_data ) { | |
437 | /* AND the already accumulated flags with these */ | |
438 | for ( i = 0 ; i < NCAPINTS ; i++ ) | |
439 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
440 | } | |
441 | ||
442 | /* Init Machine Check Exception if available. */ | |
1da177e4 | 443 | mcheck_init(c); |
31ab269a | 444 | |
6fe940d6 LS |
445 | if (c == &boot_cpu_data) |
446 | sysenter_setup(); | |
447 | enable_sep_cpu(); | |
3b520b23 SL |
448 | |
449 | if (c == &boot_cpu_data) | |
450 | mtrr_bp_init(); | |
451 | else | |
452 | mtrr_ap_init(); | |
1da177e4 LT |
453 | } |
454 | ||
455 | #ifdef CONFIG_X86_HT | |
0bb3184d | 456 | void __devinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
457 | { |
458 | u32 eax, ebx, ecx, edx; | |
94605eff | 459 | int index_msb, core_bits; |
1da177e4 LT |
460 | int cpu = smp_processor_id(); |
461 | ||
94605eff SS |
462 | cpuid(1, &eax, &ebx, &ecx, &edx); |
463 | ||
464 | c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); | |
465 | ||
63518644 | 466 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
467 | return; |
468 | ||
1da177e4 LT |
469 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
470 | ||
471 | if (smp_num_siblings == 1) { | |
472 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
473 | } else if (smp_num_siblings > 1 ) { | |
1da177e4 LT |
474 | |
475 | if (smp_num_siblings > NR_CPUS) { | |
476 | printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings); | |
477 | smp_num_siblings = 1; | |
478 | return; | |
479 | } | |
94605eff SS |
480 | |
481 | index_msb = get_count_order(smp_num_siblings); | |
1da177e4 LT |
482 | phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); |
483 | ||
484 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
485 | phys_proc_id[cpu]); | |
3dd9d514 | 486 | |
94605eff | 487 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 488 | |
94605eff | 489 | index_msb = get_count_order(smp_num_siblings) ; |
3dd9d514 | 490 | |
94605eff | 491 | core_bits = get_count_order(c->x86_max_cores); |
3dd9d514 | 492 | |
94605eff SS |
493 | cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) & |
494 | ((1 << core_bits) - 1); | |
3dd9d514 | 495 | |
94605eff | 496 | if (c->x86_max_cores > 1) |
3dd9d514 AK |
497 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", |
498 | cpu_core_id[cpu]); | |
1da177e4 LT |
499 | } |
500 | } | |
501 | #endif | |
502 | ||
0bb3184d | 503 | void __devinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
504 | { |
505 | char *vendor = NULL; | |
506 | ||
507 | if (c->x86_vendor < X86_VENDOR_NUM) | |
508 | vendor = this_cpu->c_vendor; | |
509 | else if (c->cpuid_level >= 0) | |
510 | vendor = c->x86_vendor_id; | |
511 | ||
512 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
513 | printk("%s ", vendor); | |
514 | ||
515 | if (!c->x86_model_id[0]) | |
516 | printk("%d86", c->x86); | |
517 | else | |
518 | printk("%s", c->x86_model_id); | |
519 | ||
520 | if (c->x86_mask || c->cpuid_level >= 0) | |
521 | printk(" stepping %02x\n", c->x86_mask); | |
522 | else | |
523 | printk("\n"); | |
524 | } | |
525 | ||
0bb3184d | 526 | cpumask_t cpu_initialized __devinitdata = CPU_MASK_NONE; |
1da177e4 LT |
527 | |
528 | /* This is hacky. :) | |
529 | * We're emulating future behavior. | |
530 | * In the future, the cpu-specific init functions will be called implicitly | |
531 | * via the magic of initcalls. | |
532 | * They will insert themselves into the cpu_devs structure. | |
533 | * Then, when cpu_init() is called, we can just iterate over that array. | |
534 | */ | |
535 | ||
536 | extern int intel_cpu_init(void); | |
537 | extern int cyrix_init_cpu(void); | |
538 | extern int nsc_init_cpu(void); | |
539 | extern int amd_init_cpu(void); | |
540 | extern int centaur_init_cpu(void); | |
541 | extern int transmeta_init_cpu(void); | |
542 | extern int rise_init_cpu(void); | |
543 | extern int nexgen_init_cpu(void); | |
544 | extern int umc_init_cpu(void); | |
545 | ||
546 | void __init early_cpu_init(void) | |
547 | { | |
548 | intel_cpu_init(); | |
549 | cyrix_init_cpu(); | |
550 | nsc_init_cpu(); | |
551 | amd_init_cpu(); | |
552 | centaur_init_cpu(); | |
553 | transmeta_init_cpu(); | |
554 | rise_init_cpu(); | |
555 | nexgen_init_cpu(); | |
556 | umc_init_cpu(); | |
557 | early_cpu_detect(); | |
558 | ||
559 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
560 | /* pse is not compatible with on-the-fly unmapping, | |
561 | * disable it even if the cpus claim to support it. | |
562 | */ | |
563 | clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability); | |
564 | disable_pse = 1; | |
565 | #endif | |
566 | } | |
567 | /* | |
568 | * cpu_init() initializes state that is per-CPU. Some data is already | |
569 | * initialized (naturally) in the bootstrap process, such as the GDT | |
570 | * and IDT. We reload them nevertheless, this function acts as a | |
571 | * 'CPU state barrier', nothing should get across. | |
572 | */ | |
0bb3184d | 573 | void __devinit cpu_init(void) |
1da177e4 LT |
574 | { |
575 | int cpu = smp_processor_id(); | |
576 | struct tss_struct * t = &per_cpu(init_tss, cpu); | |
577 | struct thread_struct *thread = ¤t->thread; | |
2b932f6c | 578 | struct desc_struct *gdt; |
1da177e4 | 579 | __u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu); |
2b932f6c | 580 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
1da177e4 LT |
581 | |
582 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
583 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
584 | for (;;) local_irq_enable(); | |
585 | } | |
586 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
587 | ||
588 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
589 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
590 | if (tsc_disable && cpu_has_tsc) { | |
591 | printk(KERN_NOTICE "Disabling TSC...\n"); | |
592 | /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/ | |
593 | clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability); | |
594 | set_in_cr4(X86_CR4_TSD); | |
595 | } | |
596 | ||
2b932f6c JB |
597 | /* |
598 | * This is a horrible hack to allocate the GDT. The problem | |
599 | * is that cpu_init() is called really early for the boot CPU | |
600 | * (and hence needs bootmem) but much later for the secondary | |
601 | * CPUs, when bootmem will have gone away | |
602 | */ | |
603 | if (NODE_DATA(0)->bdata->node_bootmem_map) { | |
604 | gdt = (struct desc_struct *)alloc_bootmem_pages(PAGE_SIZE); | |
605 | /* alloc_bootmem_pages panics on failure, so no check */ | |
606 | memset(gdt, 0, PAGE_SIZE); | |
607 | } else { | |
608 | gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL); | |
609 | if (unlikely(!gdt)) { | |
610 | printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu); | |
611 | for (;;) | |
612 | local_irq_enable(); | |
613 | } | |
614 | } | |
615 | ||
1da177e4 LT |
616 | /* |
617 | * Initialize the per-CPU GDT with the boot GDT, | |
618 | * and set up the GDT descriptor: | |
619 | */ | |
251e6912 | 620 | memcpy(gdt, cpu_gdt_table, GDT_SIZE); |
1da177e4 LT |
621 | |
622 | /* Set up GDT entry for 16bit stack */ | |
251e6912 | 623 | *(__u64 *)(&gdt[GDT_ENTRY_ESPFIX_SS]) |= |
1da177e4 LT |
624 | ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) | |
625 | ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) | | |
626 | (CPU_16BIT_STACK_SIZE - 1); | |
627 | ||
2b932f6c JB |
628 | cpu_gdt_descr->size = GDT_SIZE - 1; |
629 | cpu_gdt_descr->address = (unsigned long)gdt; | |
1da177e4 | 630 | |
2b932f6c | 631 | load_gdt(cpu_gdt_descr); |
4d37e7e3 | 632 | load_idt(&idt_descr); |
1da177e4 | 633 | |
1da177e4 LT |
634 | /* |
635 | * Set up and load the per-CPU TSS and LDT | |
636 | */ | |
637 | atomic_inc(&init_mm.mm_count); | |
638 | current->active_mm = &init_mm; | |
639 | if (current->mm) | |
640 | BUG(); | |
641 | enter_lazy_tlb(&init_mm, current); | |
642 | ||
643 | load_esp0(t, thread); | |
644 | set_tss_desc(cpu,t); | |
645 | load_TR_desc(); | |
646 | load_LDT(&init_mm.context); | |
647 | ||
22c4e308 | 648 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
649 | /* Set up doublefault TSS pointer in the GDT */ |
650 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 651 | #endif |
1da177e4 LT |
652 | |
653 | /* Clear %fs and %gs. */ | |
654 | asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs"); | |
655 | ||
656 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
657 | set_debugreg(0, 0); |
658 | set_debugreg(0, 1); | |
659 | set_debugreg(0, 2); | |
660 | set_debugreg(0, 3); | |
661 | set_debugreg(0, 6); | |
662 | set_debugreg(0, 7); | |
1da177e4 LT |
663 | |
664 | /* | |
665 | * Force FPU initialization: | |
666 | */ | |
667 | current_thread_info()->status = 0; | |
668 | clear_used_math(); | |
669 | mxcsr_feature_mask_init(); | |
670 | } | |
e1367daf LS |
671 | |
672 | #ifdef CONFIG_HOTPLUG_CPU | |
673 | void __devinit cpu_uninit(void) | |
674 | { | |
675 | int cpu = raw_smp_processor_id(); | |
676 | cpu_clear(cpu, cpu_initialized); | |
677 | ||
678 | /* lazy TLB state */ | |
679 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
680 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
681 | } | |
682 | #endif |