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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/semaphore.h> |
9 | #include <asm/processor.h> | |
10 | #include <asm/i387.h> | |
11 | #include <asm/msr.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/mmu_context.h> | |
27b07da7 | 14 | #include <asm/mtrr.h> |
a03a3e28 | 15 | #include <asm/mce.h> |
1da177e4 LT |
16 | #ifdef CONFIG_X86_LOCAL_APIC |
17 | #include <asm/mpspec.h> | |
18 | #include <asm/apic.h> | |
19 | #include <mach_apic.h> | |
20 | #endif | |
62111195 | 21 | #include <asm/pda.h> |
1da177e4 LT |
22 | |
23 | #include "cpu.h" | |
24 | ||
2b932f6c JB |
25 | DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr); |
26 | EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr); | |
27 | ||
ae1ee11b RR |
28 | DEFINE_PER_CPU(struct desc_struct, cpu_gdt[GDT_ENTRIES]); |
29 | ||
30 | DEFINE_PER_CPU(struct i386_pda, _cpu_pda); | |
31 | EXPORT_PER_CPU_SYMBOL(_cpu_pda); | |
62111195 | 32 | |
3bc9b76b | 33 | static int cachesize_override __cpuinitdata = -1; |
4f886511 | 34 | static int disable_x86_fxsr __cpuinitdata; |
3bc9b76b | 35 | static int disable_x86_serial_nr __cpuinitdata = 1; |
4f886511 | 36 | static int disable_x86_sep __cpuinitdata; |
1da177e4 LT |
37 | |
38 | struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; | |
39 | ||
1da177e4 LT |
40 | extern int disable_pse; |
41 | ||
b4af3f7c | 42 | static void __cpuinit default_init(struct cpuinfo_x86 * c) |
1da177e4 LT |
43 | { |
44 | /* Not much we can do here... */ | |
45 | /* Check if at least it has cpuid */ | |
46 | if (c->cpuid_level == -1) { | |
47 | /* No cpuid. It must be an ancient CPU */ | |
48 | if (c->x86 == 4) | |
49 | strcpy(c->x86_model_id, "486"); | |
50 | else if (c->x86 == 3) | |
51 | strcpy(c->x86_model_id, "386"); | |
52 | } | |
53 | } | |
54 | ||
95414930 | 55 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 56 | .c_init = default_init, |
fe38d855 | 57 | .c_vendor = "Unknown", |
1da177e4 | 58 | }; |
9dbeeec9 | 59 | static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu; |
1da177e4 LT |
60 | |
61 | static int __init cachesize_setup(char *str) | |
62 | { | |
63 | get_option (&str, &cachesize_override); | |
64 | return 1; | |
65 | } | |
66 | __setup("cachesize=", cachesize_setup); | |
67 | ||
3bc9b76b | 68 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
69 | { |
70 | unsigned int *v; | |
71 | char *p, *q; | |
72 | ||
73 | if (cpuid_eax(0x80000000) < 0x80000004) | |
74 | return 0; | |
75 | ||
76 | v = (unsigned int *) c->x86_model_id; | |
77 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
78 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
79 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
80 | c->x86_model_id[48] = 0; | |
81 | ||
82 | /* Intel chips right-justify this string for some dumb reason; | |
83 | undo that brain damage */ | |
84 | p = q = &c->x86_model_id[0]; | |
85 | while ( *p == ' ' ) | |
86 | p++; | |
87 | if ( p != q ) { | |
88 | while ( *p ) | |
89 | *q++ = *p++; | |
90 | while ( q <= &c->x86_model_id[48] ) | |
91 | *q++ = '\0'; /* Zero-pad the rest */ | |
92 | } | |
93 | ||
94 | return 1; | |
95 | } | |
96 | ||
97 | ||
3bc9b76b | 98 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
99 | { |
100 | unsigned int n, dummy, ecx, edx, l2size; | |
101 | ||
102 | n = cpuid_eax(0x80000000); | |
103 | ||
104 | if (n >= 0x80000005) { | |
105 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
106 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
107 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
108 | c->x86_cache_size=(ecx>>24)+(edx>>24); | |
109 | } | |
110 | ||
111 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
112 | return; | |
113 | ||
114 | ecx = cpuid_ecx(0x80000006); | |
115 | l2size = ecx >> 16; | |
116 | ||
117 | /* do processor-specific cache resizing */ | |
118 | if (this_cpu->c_size_cache) | |
119 | l2size = this_cpu->c_size_cache(c,l2size); | |
120 | ||
121 | /* Allow user to override all this if necessary. */ | |
122 | if (cachesize_override != -1) | |
123 | l2size = cachesize_override; | |
124 | ||
125 | if ( l2size == 0 ) | |
126 | return; /* Again, no L2 cache is possible */ | |
127 | ||
128 | c->x86_cache_size = l2size; | |
129 | ||
130 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
131 | l2size, ecx & 0xFF); | |
132 | } | |
133 | ||
134 | /* Naming convention should be: <Name> [(<Codename>)] */ | |
135 | /* This table only is used unless init_<vendor>() below doesn't set it; */ | |
136 | /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ | |
137 | ||
138 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 139 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
140 | { |
141 | struct cpu_model_info *info; | |
142 | ||
143 | if ( c->x86_model >= 16 ) | |
144 | return NULL; /* Range check */ | |
145 | ||
146 | if (!this_cpu) | |
147 | return NULL; | |
148 | ||
149 | info = this_cpu->c_models; | |
150 | ||
151 | while (info && info->family) { | |
152 | if (info->family == c->x86) | |
153 | return info->model_names[c->x86_model]; | |
154 | info++; | |
155 | } | |
156 | return NULL; /* Not found */ | |
157 | } | |
158 | ||
159 | ||
3bc9b76b | 160 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
161 | { |
162 | char *v = c->x86_vendor_id; | |
163 | int i; | |
fe38d855 | 164 | static int printed; |
1da177e4 LT |
165 | |
166 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
167 | if (cpu_devs[i]) { | |
168 | if (!strcmp(v,cpu_devs[i]->c_ident[0]) || | |
169 | (cpu_devs[i]->c_ident[1] && | |
170 | !strcmp(v,cpu_devs[i]->c_ident[1]))) { | |
171 | c->x86_vendor = i; | |
172 | if (!early) | |
173 | this_cpu = cpu_devs[i]; | |
fe38d855 | 174 | return; |
1da177e4 LT |
175 | } |
176 | } | |
177 | } | |
fe38d855 CE |
178 | if (!printed) { |
179 | printed++; | |
180 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
181 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
182 | } | |
183 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
184 | this_cpu = &default_cpu; | |
1da177e4 LT |
185 | } |
186 | ||
187 | ||
188 | static int __init x86_fxsr_setup(char * s) | |
189 | { | |
8ccb3dcd | 190 | /* Tell all the other CPU's to not use it... */ |
1da177e4 | 191 | disable_x86_fxsr = 1; |
8ccb3dcd LT |
192 | |
193 | /* | |
194 | * ... and clear the bits early in the boot_cpu_data | |
195 | * so that the bootup process doesn't try to do this | |
196 | * either. | |
197 | */ | |
198 | clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability); | |
199 | clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability); | |
1da177e4 LT |
200 | return 1; |
201 | } | |
202 | __setup("nofxsr", x86_fxsr_setup); | |
203 | ||
204 | ||
4f886511 CE |
205 | static int __init x86_sep_setup(char * s) |
206 | { | |
207 | disable_x86_sep = 1; | |
208 | return 1; | |
209 | } | |
210 | __setup("nosep", x86_sep_setup); | |
211 | ||
212 | ||
1da177e4 LT |
213 | /* Standard macro to see if a specific flag is changeable */ |
214 | static inline int flag_is_changeable_p(u32 flag) | |
215 | { | |
216 | u32 f1, f2; | |
217 | ||
218 | asm("pushfl\n\t" | |
219 | "pushfl\n\t" | |
220 | "popl %0\n\t" | |
221 | "movl %0,%1\n\t" | |
222 | "xorl %2,%0\n\t" | |
223 | "pushl %0\n\t" | |
224 | "popfl\n\t" | |
225 | "pushfl\n\t" | |
226 | "popl %0\n\t" | |
227 | "popfl\n\t" | |
228 | : "=&r" (f1), "=&r" (f2) | |
229 | : "ir" (flag)); | |
230 | ||
231 | return ((f1^f2) & flag) != 0; | |
232 | } | |
233 | ||
234 | ||
235 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 236 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
237 | { |
238 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
239 | } | |
240 | ||
d7cd5611 | 241 | void __init cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 242 | { |
1da177e4 LT |
243 | /* Get vendor name */ |
244 | cpuid(0x00000000, &c->cpuid_level, | |
245 | (int *)&c->x86_vendor_id[0], | |
246 | (int *)&c->x86_vendor_id[8], | |
247 | (int *)&c->x86_vendor_id[4]); | |
248 | ||
1da177e4 LT |
249 | c->x86 = 4; |
250 | if (c->cpuid_level >= 0x00000001) { | |
251 | u32 junk, tfms, cap0, misc; | |
252 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
253 | c->x86 = (tfms >> 8) & 15; | |
254 | c->x86_model = (tfms >> 4) & 15; | |
f5f786d0 | 255 | if (c->x86 == 0xf) |
1da177e4 | 256 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 257 | if (c->x86 >= 0x6) |
1da177e4 | 258 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 LT |
259 | c->x86_mask = tfms & 15; |
260 | if (cap0 & (1<<19)) | |
261 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; | |
262 | } | |
1da177e4 LT |
263 | } |
264 | ||
d7cd5611 RR |
265 | /* Do minimum CPU detection early. |
266 | Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. | |
267 | The others are not touched to avoid unwanted side effects. | |
268 | ||
269 | WARNING: this function is only called on the BP. Don't add code here | |
270 | that is supposed to run on all CPUs. */ | |
271 | static void __init early_cpu_detect(void) | |
272 | { | |
273 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
274 | ||
275 | c->x86_cache_alignment = 32; | |
276 | ||
277 | if (!have_cpuid_p()) | |
278 | return; | |
279 | ||
280 | cpu_detect(c); | |
281 | ||
282 | get_cpu_vendor(c, 1); | |
283 | } | |
284 | ||
68bbc172 | 285 | static void __cpuinit generic_identify(struct cpuinfo_x86 * c) |
1da177e4 LT |
286 | { |
287 | u32 tfms, xlvl; | |
1e9f28fa | 288 | int ebx; |
1da177e4 LT |
289 | |
290 | if (have_cpuid_p()) { | |
291 | /* Get vendor name */ | |
292 | cpuid(0x00000000, &c->cpuid_level, | |
293 | (int *)&c->x86_vendor_id[0], | |
294 | (int *)&c->x86_vendor_id[8], | |
295 | (int *)&c->x86_vendor_id[4]); | |
296 | ||
297 | get_cpu_vendor(c, 0); | |
298 | /* Initialize the standard set of capabilities */ | |
299 | /* Note that the vendor-specific code below might override */ | |
300 | ||
301 | /* Intel-defined flags: level 0x00000001 */ | |
302 | if ( c->cpuid_level >= 0x00000001 ) { | |
303 | u32 capability, excap; | |
1e9f28fa | 304 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
1da177e4 LT |
305 | c->x86_capability[0] = capability; |
306 | c->x86_capability[4] = excap; | |
307 | c->x86 = (tfms >> 8) & 15; | |
308 | c->x86_model = (tfms >> 4) & 15; | |
ed2da193 | 309 | if (c->x86 == 0xf) |
1da177e4 | 310 | c->x86 += (tfms >> 20) & 0xff; |
ed2da193 | 311 | if (c->x86 >= 0x6) |
1da177e4 | 312 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 313 | c->x86_mask = tfms & 15; |
96c52749 | 314 | #ifdef CONFIG_X86_HT |
1e9f28fa SS |
315 | c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); |
316 | #else | |
317 | c->apicid = (ebx >> 24) & 0xFF; | |
318 | #endif | |
770d132f AK |
319 | if (c->x86_capability[0] & (1<<19)) |
320 | c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; | |
1da177e4 LT |
321 | } else { |
322 | /* Have CPUID level 0 only - unheard of */ | |
323 | c->x86 = 4; | |
324 | } | |
325 | ||
326 | /* AMD-defined flags: level 0x80000001 */ | |
327 | xlvl = cpuid_eax(0x80000000); | |
328 | if ( (xlvl & 0xffff0000) == 0x80000000 ) { | |
329 | if ( xlvl >= 0x80000001 ) { | |
330 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
331 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
332 | } | |
333 | if ( xlvl >= 0x80000004 ) | |
334 | get_model_name(c); /* Default name */ | |
335 | } | |
336 | } | |
2e664aa2 AK |
337 | |
338 | early_intel_workaround(c); | |
339 | ||
340 | #ifdef CONFIG_X86_HT | |
4b89aff9 | 341 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
2e664aa2 | 342 | #endif |
1da177e4 LT |
343 | } |
344 | ||
3bc9b76b | 345 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 LT |
346 | { |
347 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { | |
348 | /* Disable processor serial number */ | |
349 | unsigned long lo,hi; | |
350 | rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
351 | lo |= 0x200000; | |
352 | wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
353 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
354 | clear_bit(X86_FEATURE_PN, c->x86_capability); | |
355 | ||
356 | /* Disabling the serial number may affect the cpuid level */ | |
357 | c->cpuid_level = cpuid_eax(0); | |
358 | } | |
359 | } | |
360 | ||
361 | static int __init x86_serial_nr_setup(char *s) | |
362 | { | |
363 | disable_x86_serial_nr = 0; | |
364 | return 1; | |
365 | } | |
366 | __setup("serialnumber", x86_serial_nr_setup); | |
367 | ||
368 | ||
369 | ||
370 | /* | |
371 | * This does the hard work of actually picking apart the CPU stuff... | |
372 | */ | |
3bc9b76b | 373 | void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
374 | { |
375 | int i; | |
376 | ||
377 | c->loops_per_jiffy = loops_per_jiffy; | |
378 | c->x86_cache_size = -1; | |
379 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
380 | c->cpuid_level = -1; /* CPUID not detected */ | |
381 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
382 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
383 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 384 | c->x86_max_cores = 1; |
770d132f | 385 | c->x86_clflush_size = 32; |
1da177e4 LT |
386 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
387 | ||
388 | if (!have_cpuid_p()) { | |
389 | /* First of all, decide if this is a 486 or higher */ | |
390 | /* It's a 486 if we can modify the AC flag */ | |
391 | if ( flag_is_changeable_p(X86_EFLAGS_AC) ) | |
392 | c->x86 = 4; | |
393 | else | |
394 | c->x86 = 3; | |
395 | } | |
396 | ||
397 | generic_identify(c); | |
398 | ||
399 | printk(KERN_DEBUG "CPU: After generic identify, caps:"); | |
400 | for (i = 0; i < NCAPINTS; i++) | |
401 | printk(" %08lx", c->x86_capability[i]); | |
402 | printk("\n"); | |
403 | ||
404 | if (this_cpu->c_identify) { | |
405 | this_cpu->c_identify(c); | |
406 | ||
407 | printk(KERN_DEBUG "CPU: After vendor identify, caps:"); | |
408 | for (i = 0; i < NCAPINTS; i++) | |
409 | printk(" %08lx", c->x86_capability[i]); | |
410 | printk("\n"); | |
411 | } | |
412 | ||
413 | /* | |
414 | * Vendor-specific initialization. In this section we | |
415 | * canonicalize the feature flags, meaning if there are | |
416 | * features a certain CPU supports which CPUID doesn't | |
417 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
418 | * we handle them here. | |
419 | * | |
420 | * At the end of this section, c->x86_capability better | |
421 | * indicate the features this CPU genuinely supports! | |
422 | */ | |
423 | if (this_cpu->c_init) | |
424 | this_cpu->c_init(c); | |
425 | ||
426 | /* Disable the PN if appropriate */ | |
427 | squash_the_stupid_serial_number(c); | |
428 | ||
429 | /* | |
430 | * The vendor-specific functions might have changed features. Now | |
431 | * we do "generic changes." | |
432 | */ | |
433 | ||
434 | /* TSC disabled? */ | |
435 | if ( tsc_disable ) | |
436 | clear_bit(X86_FEATURE_TSC, c->x86_capability); | |
437 | ||
438 | /* FXSR disabled? */ | |
439 | if (disable_x86_fxsr) { | |
440 | clear_bit(X86_FEATURE_FXSR, c->x86_capability); | |
441 | clear_bit(X86_FEATURE_XMM, c->x86_capability); | |
442 | } | |
443 | ||
4f886511 CE |
444 | /* SEP disabled? */ |
445 | if (disable_x86_sep) | |
446 | clear_bit(X86_FEATURE_SEP, c->x86_capability); | |
447 | ||
1da177e4 LT |
448 | if (disable_pse) |
449 | clear_bit(X86_FEATURE_PSE, c->x86_capability); | |
450 | ||
451 | /* If the model name is still unset, do table lookup. */ | |
452 | if ( !c->x86_model_id[0] ) { | |
453 | char *p; | |
454 | p = table_lookup_model(c); | |
455 | if ( p ) | |
456 | strcpy(c->x86_model_id, p); | |
457 | else | |
458 | /* Last resort... */ | |
459 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 460 | c->x86, c->x86_model); |
1da177e4 LT |
461 | } |
462 | ||
463 | /* Now the feature flags better reflect actual CPU features! */ | |
464 | ||
465 | printk(KERN_DEBUG "CPU: After all inits, caps:"); | |
466 | for (i = 0; i < NCAPINTS; i++) | |
467 | printk(" %08lx", c->x86_capability[i]); | |
468 | printk("\n"); | |
469 | ||
470 | /* | |
471 | * On SMP, boot_cpu_data holds the common feature set between | |
472 | * all CPUs; so make sure that we indicate which features are | |
473 | * common between the CPUs. The first time this routine gets | |
474 | * executed, c == &boot_cpu_data. | |
475 | */ | |
476 | if ( c != &boot_cpu_data ) { | |
477 | /* AND the already accumulated flags with these */ | |
478 | for ( i = 0 ; i < NCAPINTS ; i++ ) | |
479 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
480 | } | |
481 | ||
482 | /* Init Machine Check Exception if available. */ | |
1da177e4 | 483 | mcheck_init(c); |
31ab269a | 484 | |
6fe940d6 LS |
485 | if (c == &boot_cpu_data) |
486 | sysenter_setup(); | |
487 | enable_sep_cpu(); | |
3b520b23 SL |
488 | |
489 | if (c == &boot_cpu_data) | |
490 | mtrr_bp_init(); | |
491 | else | |
492 | mtrr_ap_init(); | |
1da177e4 LT |
493 | } |
494 | ||
495 | #ifdef CONFIG_X86_HT | |
3bc9b76b | 496 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
497 | { |
498 | u32 eax, ebx, ecx, edx; | |
94605eff | 499 | int index_msb, core_bits; |
1da177e4 | 500 | |
94605eff SS |
501 | cpuid(1, &eax, &ebx, &ecx, &edx); |
502 | ||
63518644 | 503 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
504 | return; |
505 | ||
1da177e4 LT |
506 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
507 | ||
508 | if (smp_num_siblings == 1) { | |
509 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
510 | } else if (smp_num_siblings > 1 ) { | |
1da177e4 LT |
511 | |
512 | if (smp_num_siblings > NR_CPUS) { | |
4b89aff9 RS |
513 | printk(KERN_WARNING "CPU: Unsupported number of the " |
514 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
515 | smp_num_siblings = 1; |
516 | return; | |
517 | } | |
94605eff SS |
518 | |
519 | index_msb = get_count_order(smp_num_siblings); | |
4b89aff9 | 520 | c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); |
1da177e4 LT |
521 | |
522 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
4b89aff9 | 523 | c->phys_proc_id); |
3dd9d514 | 524 | |
94605eff | 525 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 526 | |
94605eff | 527 | index_msb = get_count_order(smp_num_siblings) ; |
3dd9d514 | 528 | |
94605eff | 529 | core_bits = get_count_order(c->x86_max_cores); |
3dd9d514 | 530 | |
4b89aff9 | 531 | c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) & |
94605eff | 532 | ((1 << core_bits) - 1); |
3dd9d514 | 533 | |
94605eff | 534 | if (c->x86_max_cores > 1) |
3dd9d514 | 535 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", |
4b89aff9 | 536 | c->cpu_core_id); |
1da177e4 LT |
537 | } |
538 | } | |
539 | #endif | |
540 | ||
3bc9b76b | 541 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
542 | { |
543 | char *vendor = NULL; | |
544 | ||
545 | if (c->x86_vendor < X86_VENDOR_NUM) | |
546 | vendor = this_cpu->c_vendor; | |
547 | else if (c->cpuid_level >= 0) | |
548 | vendor = c->x86_vendor_id; | |
549 | ||
550 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
551 | printk("%s ", vendor); | |
552 | ||
553 | if (!c->x86_model_id[0]) | |
554 | printk("%d86", c->x86); | |
555 | else | |
556 | printk("%s", c->x86_model_id); | |
557 | ||
558 | if (c->x86_mask || c->cpuid_level >= 0) | |
559 | printk(" stepping %02x\n", c->x86_mask); | |
560 | else | |
561 | printk("\n"); | |
562 | } | |
563 | ||
3bc9b76b | 564 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 LT |
565 | |
566 | /* This is hacky. :) | |
567 | * We're emulating future behavior. | |
568 | * In the future, the cpu-specific init functions will be called implicitly | |
569 | * via the magic of initcalls. | |
570 | * They will insert themselves into the cpu_devs structure. | |
571 | * Then, when cpu_init() is called, we can just iterate over that array. | |
572 | */ | |
573 | ||
574 | extern int intel_cpu_init(void); | |
575 | extern int cyrix_init_cpu(void); | |
576 | extern int nsc_init_cpu(void); | |
577 | extern int amd_init_cpu(void); | |
578 | extern int centaur_init_cpu(void); | |
579 | extern int transmeta_init_cpu(void); | |
580 | extern int rise_init_cpu(void); | |
581 | extern int nexgen_init_cpu(void); | |
582 | extern int umc_init_cpu(void); | |
583 | ||
584 | void __init early_cpu_init(void) | |
585 | { | |
586 | intel_cpu_init(); | |
587 | cyrix_init_cpu(); | |
588 | nsc_init_cpu(); | |
589 | amd_init_cpu(); | |
590 | centaur_init_cpu(); | |
591 | transmeta_init_cpu(); | |
592 | rise_init_cpu(); | |
593 | nexgen_init_cpu(); | |
594 | umc_init_cpu(); | |
595 | early_cpu_detect(); | |
596 | ||
597 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
598 | /* pse is not compatible with on-the-fly unmapping, | |
599 | * disable it even if the cpus claim to support it. | |
600 | */ | |
601 | clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability); | |
602 | disable_pse = 1; | |
603 | #endif | |
604 | } | |
62111195 | 605 | |
f95d47ca JF |
606 | /* Make sure %gs is initialized properly in idle threads */ |
607 | struct pt_regs * __devinit idle_regs(struct pt_regs *regs) | |
608 | { | |
609 | memset(regs, 0, sizeof(struct pt_regs)); | |
464d1a78 | 610 | regs->xfs = __KERNEL_PDA; |
f95d47ca JF |
611 | return regs; |
612 | } | |
613 | ||
62111195 JF |
614 | /* Initial PDA used by boot CPU */ |
615 | struct i386_pda boot_pda = { | |
616 | ._pda = &boot_pda, | |
b2938f88 | 617 | .cpu_number = 0, |
ec7fcaab | 618 | .pcurrent = &init_task, |
62111195 JF |
619 | }; |
620 | ||
464d1a78 | 621 | static inline void set_kernel_fs(void) |
f95d47ca | 622 | { |
464d1a78 | 623 | /* Set %fs for this CPU's PDA. Memory clobber is to create a |
f95d47ca JF |
624 | barrier with respect to any PDA operations, so the compiler |
625 | doesn't move any before here. */ | |
464d1a78 | 626 | asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_PDA) : "memory"); |
f95d47ca JF |
627 | } |
628 | ||
ae1ee11b RR |
629 | /* Initialize the CPU's GDT and PDA. This is either the boot CPU doing itself |
630 | (still using cpu_gdt_table), or a CPU doing it for a secondary which | |
631 | will soon come up. */ | |
632 | __cpuinit void init_gdt(int cpu, struct task_struct *idle) | |
62111195 JF |
633 | { |
634 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); | |
ae1ee11b RR |
635 | struct desc_struct *gdt = per_cpu(cpu_gdt, cpu); |
636 | struct i386_pda *pda = &per_cpu(_cpu_pda, cpu); | |
62111195 | 637 | |
251e6912 | 638 | memcpy(gdt, cpu_gdt_table, GDT_SIZE); |
ae1ee11b | 639 | cpu_gdt_descr->address = (unsigned long)gdt; |
2b932f6c | 640 | cpu_gdt_descr->size = GDT_SIZE - 1; |
1da177e4 | 641 | |
62111195 JF |
642 | pack_descriptor((u32 *)&gdt[GDT_ENTRY_PDA].a, |
643 | (u32 *)&gdt[GDT_ENTRY_PDA].b, | |
644 | (unsigned long)pda, sizeof(*pda) - 1, | |
645 | 0x80 | DESCTYPE_S | 0x2, 0); /* present read-write data segment */ | |
646 | ||
647 | memset(pda, 0, sizeof(*pda)); | |
648 | pda->_pda = pda; | |
b2938f88 | 649 | pda->cpu_number = cpu; |
ec7fcaab | 650 | pda->pcurrent = idle; |
62111195 JF |
651 | } |
652 | ||
9ee79a3d | 653 | void __cpuinit cpu_set_gdt(int cpu) |
62111195 | 654 | { |
62111195 JF |
655 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
656 | ||
2b932f6c | 657 | load_gdt(cpu_gdt_descr); |
464d1a78 | 658 | set_kernel_fs(); |
9ee79a3d JB |
659 | } |
660 | ||
661 | /* Common CPU init for both boot and secondary CPUs */ | |
662 | static void __cpuinit _cpu_init(int cpu, struct task_struct *curr) | |
663 | { | |
664 | struct tss_struct * t = &per_cpu(init_tss, cpu); | |
665 | struct thread_struct *thread = &curr->thread; | |
62111195 JF |
666 | |
667 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
668 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
669 | for (;;) local_irq_enable(); | |
670 | } | |
671 | ||
672 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
673 | ||
674 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
675 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
676 | if (tsc_disable && cpu_has_tsc) { | |
677 | printk(KERN_NOTICE "Disabling TSC...\n"); | |
678 | /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/ | |
679 | clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability); | |
680 | set_in_cr4(X86_CR4_TSD); | |
681 | } | |
682 | ||
4d37e7e3 | 683 | load_idt(&idt_descr); |
1da177e4 | 684 | |
1da177e4 LT |
685 | /* |
686 | * Set up and load the per-CPU TSS and LDT | |
687 | */ | |
688 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
689 | curr->active_mm = &init_mm; |
690 | if (curr->mm) | |
691 | BUG(); | |
692 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 LT |
693 | |
694 | load_esp0(t, thread); | |
695 | set_tss_desc(cpu,t); | |
696 | load_TR_desc(); | |
697 | load_LDT(&init_mm.context); | |
698 | ||
22c4e308 | 699 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
700 | /* Set up doublefault TSS pointer in the GDT */ |
701 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 702 | #endif |
1da177e4 | 703 | |
464d1a78 JF |
704 | /* Clear %gs. */ |
705 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
706 | |
707 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
708 | set_debugreg(0, 0); |
709 | set_debugreg(0, 1); | |
710 | set_debugreg(0, 2); | |
711 | set_debugreg(0, 3); | |
712 | set_debugreg(0, 6); | |
713 | set_debugreg(0, 7); | |
1da177e4 LT |
714 | |
715 | /* | |
716 | * Force FPU initialization: | |
717 | */ | |
718 | current_thread_info()->status = 0; | |
719 | clear_used_math(); | |
720 | mxcsr_feature_mask_init(); | |
721 | } | |
e1367daf | 722 | |
62111195 JF |
723 | /* Entrypoint to initialize secondary CPU */ |
724 | void __cpuinit secondary_cpu_init(void) | |
725 | { | |
726 | int cpu = smp_processor_id(); | |
727 | struct task_struct *curr = current; | |
728 | ||
729 | _cpu_init(cpu, curr); | |
730 | } | |
731 | ||
732 | /* | |
733 | * cpu_init() initializes state that is per-CPU. Some data is already | |
734 | * initialized (naturally) in the bootstrap process, such as the GDT | |
735 | * and IDT. We reload them nevertheless, this function acts as a | |
736 | * 'CPU state barrier', nothing should get across. | |
737 | */ | |
738 | void __cpuinit cpu_init(void) | |
739 | { | |
740 | int cpu = smp_processor_id(); | |
741 | struct task_struct *curr = current; | |
742 | ||
743 | /* Set up the real GDT and PDA, so we can transition from the | |
ae1ee11b RR |
744 | boot_gdt_table & boot_pda. */ |
745 | init_gdt(cpu, curr); | |
9ee79a3d | 746 | cpu_set_gdt(cpu); |
62111195 JF |
747 | _cpu_init(cpu, curr); |
748 | } | |
749 | ||
e1367daf | 750 | #ifdef CONFIG_HOTPLUG_CPU |
3bc9b76b | 751 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
752 | { |
753 | int cpu = raw_smp_processor_id(); | |
754 | cpu_clear(cpu, cpu_initialized); | |
755 | ||
756 | /* lazy TLB state */ | |
757 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
758 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
759 | } | |
760 | #endif |