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CommitLineData
1da177e4
LT
1#include <linux/init.h>
2#include <linux/string.h>
3#include <linux/delay.h>
4#include <linux/smp.h>
5#include <linux/module.h>
6#include <linux/percpu.h>
2b932f6c 7#include <linux/bootmem.h>
1da177e4
LT
8#include <asm/semaphore.h>
9#include <asm/processor.h>
10#include <asm/i387.h>
11#include <asm/msr.h>
12#include <asm/io.h>
13#include <asm/mmu_context.h>
27b07da7 14#include <asm/mtrr.h>
a03a3e28 15#include <asm/mce.h>
1da177e4
LT
16#ifdef CONFIG_X86_LOCAL_APIC
17#include <asm/mpspec.h>
18#include <asm/apic.h>
19#include <mach_apic.h>
20#endif
62111195 21#include <asm/pda.h>
1da177e4
LT
22
23#include "cpu.h"
24
2b932f6c
JB
25DEFINE_PER_CPU(struct Xgt_desc_struct, cpu_gdt_descr);
26EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr);
27
62111195
JF
28struct i386_pda *_cpu_pda[NR_CPUS] __read_mostly;
29EXPORT_SYMBOL(_cpu_pda);
30
3bc9b76b 31static int cachesize_override __cpuinitdata = -1;
4f886511 32static int disable_x86_fxsr __cpuinitdata;
3bc9b76b 33static int disable_x86_serial_nr __cpuinitdata = 1;
4f886511 34static int disable_x86_sep __cpuinitdata;
1da177e4
LT
35
36struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
37
1da177e4
LT
38extern int disable_pse;
39
b4af3f7c 40static void __cpuinit default_init(struct cpuinfo_x86 * c)
1da177e4
LT
41{
42 /* Not much we can do here... */
43 /* Check if at least it has cpuid */
44 if (c->cpuid_level == -1) {
45 /* No cpuid. It must be an ancient CPU */
46 if (c->x86 == 4)
47 strcpy(c->x86_model_id, "486");
48 else if (c->x86 == 3)
49 strcpy(c->x86_model_id, "386");
50 }
51}
52
95414930 53static struct cpu_dev __cpuinitdata default_cpu = {
1da177e4 54 .c_init = default_init,
fe38d855 55 .c_vendor = "Unknown",
1da177e4
LT
56};
57static struct cpu_dev * this_cpu = &default_cpu;
58
59static int __init cachesize_setup(char *str)
60{
61 get_option (&str, &cachesize_override);
62 return 1;
63}
64__setup("cachesize=", cachesize_setup);
65
3bc9b76b 66int __cpuinit get_model_name(struct cpuinfo_x86 *c)
1da177e4
LT
67{
68 unsigned int *v;
69 char *p, *q;
70
71 if (cpuid_eax(0x80000000) < 0x80000004)
72 return 0;
73
74 v = (unsigned int *) c->x86_model_id;
75 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
76 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
77 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
78 c->x86_model_id[48] = 0;
79
80 /* Intel chips right-justify this string for some dumb reason;
81 undo that brain damage */
82 p = q = &c->x86_model_id[0];
83 while ( *p == ' ' )
84 p++;
85 if ( p != q ) {
86 while ( *p )
87 *q++ = *p++;
88 while ( q <= &c->x86_model_id[48] )
89 *q++ = '\0'; /* Zero-pad the rest */
90 }
91
92 return 1;
93}
94
95
3bc9b76b 96void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
1da177e4
LT
97{
98 unsigned int n, dummy, ecx, edx, l2size;
99
100 n = cpuid_eax(0x80000000);
101
102 if (n >= 0x80000005) {
103 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
104 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
105 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
106 c->x86_cache_size=(ecx>>24)+(edx>>24);
107 }
108
109 if (n < 0x80000006) /* Some chips just has a large L1. */
110 return;
111
112 ecx = cpuid_ecx(0x80000006);
113 l2size = ecx >> 16;
114
115 /* do processor-specific cache resizing */
116 if (this_cpu->c_size_cache)
117 l2size = this_cpu->c_size_cache(c,l2size);
118
119 /* Allow user to override all this if necessary. */
120 if (cachesize_override != -1)
121 l2size = cachesize_override;
122
123 if ( l2size == 0 )
124 return; /* Again, no L2 cache is possible */
125
126 c->x86_cache_size = l2size;
127
128 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
129 l2size, ecx & 0xFF);
130}
131
132/* Naming convention should be: <Name> [(<Codename>)] */
133/* This table only is used unless init_<vendor>() below doesn't set it; */
134/* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
135
136/* Look up CPU names by table lookup. */
3bc9b76b 137static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
1da177e4
LT
138{
139 struct cpu_model_info *info;
140
141 if ( c->x86_model >= 16 )
142 return NULL; /* Range check */
143
144 if (!this_cpu)
145 return NULL;
146
147 info = this_cpu->c_models;
148
149 while (info && info->family) {
150 if (info->family == c->x86)
151 return info->model_names[c->x86_model];
152 info++;
153 }
154 return NULL; /* Not found */
155}
156
157
3bc9b76b 158static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
1da177e4
LT
159{
160 char *v = c->x86_vendor_id;
161 int i;
fe38d855 162 static int printed;
1da177e4
LT
163
164 for (i = 0; i < X86_VENDOR_NUM; i++) {
165 if (cpu_devs[i]) {
166 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
167 (cpu_devs[i]->c_ident[1] &&
168 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
169 c->x86_vendor = i;
170 if (!early)
171 this_cpu = cpu_devs[i];
fe38d855 172 return;
1da177e4
LT
173 }
174 }
175 }
fe38d855
CE
176 if (!printed) {
177 printed++;
178 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
179 printk(KERN_ERR "CPU: Your system may be unstable.\n");
180 }
181 c->x86_vendor = X86_VENDOR_UNKNOWN;
182 this_cpu = &default_cpu;
1da177e4
LT
183}
184
185
186static int __init x86_fxsr_setup(char * s)
187{
8ccb3dcd 188 /* Tell all the other CPU's to not use it... */
1da177e4 189 disable_x86_fxsr = 1;
8ccb3dcd
LT
190
191 /*
192 * ... and clear the bits early in the boot_cpu_data
193 * so that the bootup process doesn't try to do this
194 * either.
195 */
196 clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability);
197 clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability);
1da177e4
LT
198 return 1;
199}
200__setup("nofxsr", x86_fxsr_setup);
201
202
4f886511
CE
203static int __init x86_sep_setup(char * s)
204{
205 disable_x86_sep = 1;
206 return 1;
207}
208__setup("nosep", x86_sep_setup);
209
210
1da177e4
LT
211/* Standard macro to see if a specific flag is changeable */
212static inline int flag_is_changeable_p(u32 flag)
213{
214 u32 f1, f2;
215
216 asm("pushfl\n\t"
217 "pushfl\n\t"
218 "popl %0\n\t"
219 "movl %0,%1\n\t"
220 "xorl %2,%0\n\t"
221 "pushl %0\n\t"
222 "popfl\n\t"
223 "pushfl\n\t"
224 "popl %0\n\t"
225 "popfl\n\t"
226 : "=&r" (f1), "=&r" (f2)
227 : "ir" (flag));
228
229 return ((f1^f2) & flag) != 0;
230}
231
232
233/* Probe for the CPUID instruction */
3bc9b76b 234static int __cpuinit have_cpuid_p(void)
1da177e4
LT
235{
236 return flag_is_changeable_p(X86_EFLAGS_ID);
237}
238
239/* Do minimum CPU detection early.
240 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
2e664aa2
AK
241 The others are not touched to avoid unwanted side effects.
242
243 WARNING: this function is only called on the BP. Don't add code here
244 that is supposed to run on all CPUs. */
1da177e4
LT
245static void __init early_cpu_detect(void)
246{
247 struct cpuinfo_x86 *c = &boot_cpu_data;
248
249 c->x86_cache_alignment = 32;
250
251 if (!have_cpuid_p())
252 return;
253
254 /* Get vendor name */
255 cpuid(0x00000000, &c->cpuid_level,
256 (int *)&c->x86_vendor_id[0],
257 (int *)&c->x86_vendor_id[8],
258 (int *)&c->x86_vendor_id[4]);
259
260 get_cpu_vendor(c, 1);
261
262 c->x86 = 4;
263 if (c->cpuid_level >= 0x00000001) {
264 u32 junk, tfms, cap0, misc;
265 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
266 c->x86 = (tfms >> 8) & 15;
267 c->x86_model = (tfms >> 4) & 15;
f5f786d0 268 if (c->x86 == 0xf)
1da177e4 269 c->x86 += (tfms >> 20) & 0xff;
f5f786d0 270 if (c->x86 >= 0x6)
1da177e4 271 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4
LT
272 c->x86_mask = tfms & 15;
273 if (cap0 & (1<<19))
274 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
275 }
1da177e4
LT
276}
277
68bbc172 278static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
1da177e4
LT
279{
280 u32 tfms, xlvl;
1e9f28fa 281 int ebx;
1da177e4
LT
282
283 if (have_cpuid_p()) {
284 /* Get vendor name */
285 cpuid(0x00000000, &c->cpuid_level,
286 (int *)&c->x86_vendor_id[0],
287 (int *)&c->x86_vendor_id[8],
288 (int *)&c->x86_vendor_id[4]);
289
290 get_cpu_vendor(c, 0);
291 /* Initialize the standard set of capabilities */
292 /* Note that the vendor-specific code below might override */
293
294 /* Intel-defined flags: level 0x00000001 */
295 if ( c->cpuid_level >= 0x00000001 ) {
296 u32 capability, excap;
1e9f28fa 297 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
1da177e4
LT
298 c->x86_capability[0] = capability;
299 c->x86_capability[4] = excap;
300 c->x86 = (tfms >> 8) & 15;
301 c->x86_model = (tfms >> 4) & 15;
ed2da193 302 if (c->x86 == 0xf)
1da177e4 303 c->x86 += (tfms >> 20) & 0xff;
ed2da193 304 if (c->x86 >= 0x6)
1da177e4 305 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1da177e4 306 c->x86_mask = tfms & 15;
96c52749 307#ifdef CONFIG_X86_HT
1e9f28fa
SS
308 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
309#else
310 c->apicid = (ebx >> 24) & 0xFF;
311#endif
1da177e4
LT
312 } else {
313 /* Have CPUID level 0 only - unheard of */
314 c->x86 = 4;
315 }
316
317 /* AMD-defined flags: level 0x80000001 */
318 xlvl = cpuid_eax(0x80000000);
319 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
320 if ( xlvl >= 0x80000001 ) {
321 c->x86_capability[1] = cpuid_edx(0x80000001);
322 c->x86_capability[6] = cpuid_ecx(0x80000001);
323 }
324 if ( xlvl >= 0x80000004 )
325 get_model_name(c); /* Default name */
326 }
327 }
2e664aa2
AK
328
329 early_intel_workaround(c);
330
331#ifdef CONFIG_X86_HT
4b89aff9 332 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
2e664aa2 333#endif
1da177e4
LT
334}
335
3bc9b76b 336static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
1da177e4
LT
337{
338 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
339 /* Disable processor serial number */
340 unsigned long lo,hi;
341 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
342 lo |= 0x200000;
343 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
344 printk(KERN_NOTICE "CPU serial number disabled.\n");
345 clear_bit(X86_FEATURE_PN, c->x86_capability);
346
347 /* Disabling the serial number may affect the cpuid level */
348 c->cpuid_level = cpuid_eax(0);
349 }
350}
351
352static int __init x86_serial_nr_setup(char *s)
353{
354 disable_x86_serial_nr = 0;
355 return 1;
356}
357__setup("serialnumber", x86_serial_nr_setup);
358
359
360
361/*
362 * This does the hard work of actually picking apart the CPU stuff...
363 */
3bc9b76b 364void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1da177e4
LT
365{
366 int i;
367
368 c->loops_per_jiffy = loops_per_jiffy;
369 c->x86_cache_size = -1;
370 c->x86_vendor = X86_VENDOR_UNKNOWN;
371 c->cpuid_level = -1; /* CPUID not detected */
372 c->x86_model = c->x86_mask = 0; /* So far unknown... */
373 c->x86_vendor_id[0] = '\0'; /* Unset */
374 c->x86_model_id[0] = '\0'; /* Unset */
94605eff 375 c->x86_max_cores = 1;
1da177e4
LT
376 memset(&c->x86_capability, 0, sizeof c->x86_capability);
377
378 if (!have_cpuid_p()) {
379 /* First of all, decide if this is a 486 or higher */
380 /* It's a 486 if we can modify the AC flag */
381 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
382 c->x86 = 4;
383 else
384 c->x86 = 3;
385 }
386
387 generic_identify(c);
388
389 printk(KERN_DEBUG "CPU: After generic identify, caps:");
390 for (i = 0; i < NCAPINTS; i++)
391 printk(" %08lx", c->x86_capability[i]);
392 printk("\n");
393
394 if (this_cpu->c_identify) {
395 this_cpu->c_identify(c);
396
397 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
398 for (i = 0; i < NCAPINTS; i++)
399 printk(" %08lx", c->x86_capability[i]);
400 printk("\n");
401 }
402
403 /*
404 * Vendor-specific initialization. In this section we
405 * canonicalize the feature flags, meaning if there are
406 * features a certain CPU supports which CPUID doesn't
407 * tell us, CPUID claiming incorrect flags, or other bugs,
408 * we handle them here.
409 *
410 * At the end of this section, c->x86_capability better
411 * indicate the features this CPU genuinely supports!
412 */
413 if (this_cpu->c_init)
414 this_cpu->c_init(c);
415
416 /* Disable the PN if appropriate */
417 squash_the_stupid_serial_number(c);
418
419 /*
420 * The vendor-specific functions might have changed features. Now
421 * we do "generic changes."
422 */
423
424 /* TSC disabled? */
425 if ( tsc_disable )
426 clear_bit(X86_FEATURE_TSC, c->x86_capability);
427
428 /* FXSR disabled? */
429 if (disable_x86_fxsr) {
430 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
431 clear_bit(X86_FEATURE_XMM, c->x86_capability);
432 }
433
4f886511
CE
434 /* SEP disabled? */
435 if (disable_x86_sep)
436 clear_bit(X86_FEATURE_SEP, c->x86_capability);
437
1da177e4
LT
438 if (disable_pse)
439 clear_bit(X86_FEATURE_PSE, c->x86_capability);
440
441 /* If the model name is still unset, do table lookup. */
442 if ( !c->x86_model_id[0] ) {
443 char *p;
444 p = table_lookup_model(c);
445 if ( p )
446 strcpy(c->x86_model_id, p);
447 else
448 /* Last resort... */
449 sprintf(c->x86_model_id, "%02x/%02x",
54a20f8c 450 c->x86, c->x86_model);
1da177e4
LT
451 }
452
453 /* Now the feature flags better reflect actual CPU features! */
454
455 printk(KERN_DEBUG "CPU: After all inits, caps:");
456 for (i = 0; i < NCAPINTS; i++)
457 printk(" %08lx", c->x86_capability[i]);
458 printk("\n");
459
460 /*
461 * On SMP, boot_cpu_data holds the common feature set between
462 * all CPUs; so make sure that we indicate which features are
463 * common between the CPUs. The first time this routine gets
464 * executed, c == &boot_cpu_data.
465 */
466 if ( c != &boot_cpu_data ) {
467 /* AND the already accumulated flags with these */
468 for ( i = 0 ; i < NCAPINTS ; i++ )
469 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
470 }
471
472 /* Init Machine Check Exception if available. */
1da177e4 473 mcheck_init(c);
31ab269a 474
6fe940d6
LS
475 if (c == &boot_cpu_data)
476 sysenter_setup();
477 enable_sep_cpu();
3b520b23
SL
478
479 if (c == &boot_cpu_data)
480 mtrr_bp_init();
481 else
482 mtrr_ap_init();
1da177e4
LT
483}
484
485#ifdef CONFIG_X86_HT
3bc9b76b 486void __cpuinit detect_ht(struct cpuinfo_x86 *c)
1da177e4
LT
487{
488 u32 eax, ebx, ecx, edx;
94605eff 489 int index_msb, core_bits;
1da177e4 490
94605eff
SS
491 cpuid(1, &eax, &ebx, &ecx, &edx);
492
63518644 493 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
1da177e4
LT
494 return;
495
1da177e4
LT
496 smp_num_siblings = (ebx & 0xff0000) >> 16;
497
498 if (smp_num_siblings == 1) {
499 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
500 } else if (smp_num_siblings > 1 ) {
1da177e4
LT
501
502 if (smp_num_siblings > NR_CPUS) {
4b89aff9
RS
503 printk(KERN_WARNING "CPU: Unsupported number of the "
504 "siblings %d", smp_num_siblings);
1da177e4
LT
505 smp_num_siblings = 1;
506 return;
507 }
94605eff
SS
508
509 index_msb = get_count_order(smp_num_siblings);
4b89aff9 510 c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
1da177e4
LT
511
512 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
4b89aff9 513 c->phys_proc_id);
3dd9d514 514
94605eff 515 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
3dd9d514 516
94605eff 517 index_msb = get_count_order(smp_num_siblings) ;
3dd9d514 518
94605eff 519 core_bits = get_count_order(c->x86_max_cores);
3dd9d514 520
4b89aff9 521 c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
94605eff 522 ((1 << core_bits) - 1);
3dd9d514 523
94605eff 524 if (c->x86_max_cores > 1)
3dd9d514 525 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
4b89aff9 526 c->cpu_core_id);
1da177e4
LT
527 }
528}
529#endif
530
3bc9b76b 531void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1da177e4
LT
532{
533 char *vendor = NULL;
534
535 if (c->x86_vendor < X86_VENDOR_NUM)
536 vendor = this_cpu->c_vendor;
537 else if (c->cpuid_level >= 0)
538 vendor = c->x86_vendor_id;
539
540 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
541 printk("%s ", vendor);
542
543 if (!c->x86_model_id[0])
544 printk("%d86", c->x86);
545 else
546 printk("%s", c->x86_model_id);
547
548 if (c->x86_mask || c->cpuid_level >= 0)
549 printk(" stepping %02x\n", c->x86_mask);
550 else
551 printk("\n");
552}
553
3bc9b76b 554cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
1da177e4
LT
555
556/* This is hacky. :)
557 * We're emulating future behavior.
558 * In the future, the cpu-specific init functions will be called implicitly
559 * via the magic of initcalls.
560 * They will insert themselves into the cpu_devs structure.
561 * Then, when cpu_init() is called, we can just iterate over that array.
562 */
563
564extern int intel_cpu_init(void);
565extern int cyrix_init_cpu(void);
566extern int nsc_init_cpu(void);
567extern int amd_init_cpu(void);
568extern int centaur_init_cpu(void);
569extern int transmeta_init_cpu(void);
570extern int rise_init_cpu(void);
571extern int nexgen_init_cpu(void);
572extern int umc_init_cpu(void);
573
574void __init early_cpu_init(void)
575{
576 intel_cpu_init();
577 cyrix_init_cpu();
578 nsc_init_cpu();
579 amd_init_cpu();
580 centaur_init_cpu();
581 transmeta_init_cpu();
582 rise_init_cpu();
583 nexgen_init_cpu();
584 umc_init_cpu();
585 early_cpu_detect();
586
587#ifdef CONFIG_DEBUG_PAGEALLOC
588 /* pse is not compatible with on-the-fly unmapping,
589 * disable it even if the cpus claim to support it.
590 */
591 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
592 disable_pse = 1;
593#endif
594}
62111195 595
f95d47ca
JF
596/* Make sure %gs is initialized properly in idle threads */
597struct pt_regs * __devinit idle_regs(struct pt_regs *regs)
598{
599 memset(regs, 0, sizeof(struct pt_regs));
600 regs->xgs = __KERNEL_PDA;
601 return regs;
602}
603
62111195 604__cpuinit int alloc_gdt(int cpu)
1da177e4 605{
2b932f6c 606 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
62111195
JF
607 struct desc_struct *gdt;
608 struct i386_pda *pda;
1da177e4 609
62111195
JF
610 gdt = (struct desc_struct *)cpu_gdt_descr->address;
611 pda = cpu_pda(cpu);
1da177e4 612
2b932f6c
JB
613 /*
614 * This is a horrible hack to allocate the GDT. The problem
615 * is that cpu_init() is called really early for the boot CPU
616 * (and hence needs bootmem) but much later for the secondary
617 * CPUs, when bootmem will have gone away
618 */
619 if (NODE_DATA(0)->bdata->node_bootmem_map) {
62111195
JF
620 BUG_ON(gdt != NULL || pda != NULL);
621
622 gdt = alloc_bootmem_pages(PAGE_SIZE);
623 pda = alloc_bootmem(sizeof(*pda));
624 /* alloc_bootmem(_pages) panics on failure, so no check */
625
2b932f6c 626 memset(gdt, 0, PAGE_SIZE);
62111195 627 memset(pda, 0, sizeof(*pda));
2b932f6c 628 } else {
62111195
JF
629 /* GDT and PDA might already have been allocated if
630 this is a CPU hotplug re-insertion. */
631 if (gdt == NULL)
632 gdt = (struct desc_struct *)get_zeroed_page(GFP_KERNEL);
633
634 if (pda == NULL)
635 pda = kmalloc_node(sizeof(*pda), GFP_KERNEL, cpu_to_node(cpu));
636
637 if (unlikely(!gdt || !pda)) {
638 free_pages((unsigned long)gdt, 0);
639 kfree(pda);
640 return 0;
2b932f6c
JB
641 }
642 }
62111195
JF
643
644 cpu_gdt_descr->address = (unsigned long)gdt;
645 cpu_pda(cpu) = pda;
646
647 return 1;
648}
649
650/* Initial PDA used by boot CPU */
651struct i386_pda boot_pda = {
652 ._pda = &boot_pda,
b2938f88 653 .cpu_number = 0,
ec7fcaab 654 .pcurrent = &init_task,
62111195
JF
655};
656
f95d47ca
JF
657static inline void set_kernel_gs(void)
658{
659 /* Set %gs for this CPU's PDA. Memory clobber is to create a
660 barrier with respect to any PDA operations, so the compiler
661 doesn't move any before here. */
662 asm volatile ("mov %0, %%gs" : : "r" (__KERNEL_PDA) : "memory");
663}
664
62111195
JF
665/* Initialize the CPU's GDT and PDA. The boot CPU does this for
666 itself, but secondaries find this done for them. */
667__cpuinit int init_gdt(int cpu, struct task_struct *idle)
668{
669 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
670 struct desc_struct *gdt;
671 struct i386_pda *pda;
672
673 /* For non-boot CPUs, the GDT and PDA should already have been
674 allocated. */
675 if (!alloc_gdt(cpu)) {
676 printk(KERN_CRIT "CPU%d failed to allocate GDT or PDA\n", cpu);
677 return 0;
678 }
679
680 gdt = (struct desc_struct *)cpu_gdt_descr->address;
681 pda = cpu_pda(cpu);
682
683 BUG_ON(gdt == NULL || pda == NULL);
684
1da177e4
LT
685 /*
686 * Initialize the per-CPU GDT with the boot GDT,
687 * and set up the GDT descriptor:
688 */
251e6912 689 memcpy(gdt, cpu_gdt_table, GDT_SIZE);
2b932f6c 690 cpu_gdt_descr->size = GDT_SIZE - 1;
1da177e4 691
62111195
JF
692 pack_descriptor((u32 *)&gdt[GDT_ENTRY_PDA].a,
693 (u32 *)&gdt[GDT_ENTRY_PDA].b,
694 (unsigned long)pda, sizeof(*pda) - 1,
695 0x80 | DESCTYPE_S | 0x2, 0); /* present read-write data segment */
696
697 memset(pda, 0, sizeof(*pda));
698 pda->_pda = pda;
b2938f88 699 pda->cpu_number = cpu;
ec7fcaab 700 pda->pcurrent = idle;
62111195
JF
701
702 return 1;
703}
704
705/* Common CPU init for both boot and secondary CPUs */
706static void __cpuinit _cpu_init(int cpu, struct task_struct *curr)
707{
708 struct tss_struct * t = &per_cpu(init_tss, cpu);
709 struct thread_struct *thread = &curr->thread;
710 struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu);
711
712 /* Reinit these anyway, even if they've already been done (on
713 the boot CPU, this will transition from the boot gdt+pda to
714 the real ones). */
2b932f6c 715 load_gdt(cpu_gdt_descr);
f95d47ca 716 set_kernel_gs();
62111195
JF
717
718 if (cpu_test_and_set(cpu, cpu_initialized)) {
719 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
720 for (;;) local_irq_enable();
721 }
722
723 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
724
725 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
726 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
727 if (tsc_disable && cpu_has_tsc) {
728 printk(KERN_NOTICE "Disabling TSC...\n");
729 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
730 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
731 set_in_cr4(X86_CR4_TSD);
732 }
733
4d37e7e3 734 load_idt(&idt_descr);
1da177e4 735
1da177e4
LT
736 /*
737 * Set up and load the per-CPU TSS and LDT
738 */
739 atomic_inc(&init_mm.mm_count);
62111195
JF
740 curr->active_mm = &init_mm;
741 if (curr->mm)
742 BUG();
743 enter_lazy_tlb(&init_mm, curr);
1da177e4
LT
744
745 load_esp0(t, thread);
746 set_tss_desc(cpu,t);
747 load_TR_desc();
748 load_LDT(&init_mm.context);
749
22c4e308 750#ifdef CONFIG_DOUBLEFAULT
1da177e4
LT
751 /* Set up doublefault TSS pointer in the GDT */
752 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
22c4e308 753#endif
1da177e4 754
f95d47ca
JF
755 /* Clear %fs. */
756 asm volatile ("mov %0, %%fs" : : "r" (0));
1da177e4
LT
757
758 /* Clear all 6 debug registers: */
4bb0d3ec
ZA
759 set_debugreg(0, 0);
760 set_debugreg(0, 1);
761 set_debugreg(0, 2);
762 set_debugreg(0, 3);
763 set_debugreg(0, 6);
764 set_debugreg(0, 7);
1da177e4
LT
765
766 /*
767 * Force FPU initialization:
768 */
769 current_thread_info()->status = 0;
770 clear_used_math();
771 mxcsr_feature_mask_init();
772}
e1367daf 773
62111195
JF
774/* Entrypoint to initialize secondary CPU */
775void __cpuinit secondary_cpu_init(void)
776{
777 int cpu = smp_processor_id();
778 struct task_struct *curr = current;
779
780 _cpu_init(cpu, curr);
781}
782
783/*
784 * cpu_init() initializes state that is per-CPU. Some data is already
785 * initialized (naturally) in the bootstrap process, such as the GDT
786 * and IDT. We reload them nevertheless, this function acts as a
787 * 'CPU state barrier', nothing should get across.
788 */
789void __cpuinit cpu_init(void)
790{
791 int cpu = smp_processor_id();
792 struct task_struct *curr = current;
793
794 /* Set up the real GDT and PDA, so we can transition from the
795 boot versions. */
796 if (!init_gdt(cpu, curr)) {
797 /* failed to allocate something; not much we can do... */
798 for (;;)
799 local_irq_enable();
800 }
801
802 _cpu_init(cpu, curr);
803}
804
e1367daf 805#ifdef CONFIG_HOTPLUG_CPU
3bc9b76b 806void __cpuinit cpu_uninit(void)
e1367daf
LS
807{
808 int cpu = raw_smp_processor_id();
809 cpu_clear(cpu, cpu_initialized);
810
811 /* lazy TLB state */
812 per_cpu(cpu_tlbstate, cpu).state = 0;
813 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
814}
815#endif