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1da177e4 LT |
1 | /* |
2 | * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk> | |
3 | * (C) 2002 Padraig Brady. <padraig@antefacto.com> | |
4 | * | |
5 | * Licensed under the terms of the GNU GPL License version 2. | |
6 | * Based upon datasheets & sample CPUs kindly provided by VIA. | |
7 | * | |
8 | * VIA have currently 3 different versions of Longhaul. | |
9 | * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147. | |
10 | * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0. | |
11 | * Version 2 of longhaul is the same as v1, but adds voltage scaling. | |
12 | * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C) | |
13 | * voltage scaling support has currently been disabled in this driver | |
14 | * until we have code that gets it right. | |
15 | * Version 3 of longhaul got renamed to Powersaver and redesigned | |
16 | * to use the POWERSAVER MSR at 0x110a. | |
17 | * It is present in Ezra-T (C5M), Nehemiah (C5X) and above. | |
18 | * It's pretty much the same feature wise to longhaul v2, though | |
19 | * there is provision for scaling FSB too, but this doesn't work | |
20 | * too well in practice so we don't even try to use this. | |
21 | * | |
22 | * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* | |
23 | */ | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/cpufreq.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/string.h> | |
3be6a48f | 32 | #include <linux/pci.h> |
1da177e4 LT |
33 | |
34 | #include <asm/msr.h> | |
35 | #include <asm/timex.h> | |
36 | #include <asm/io.h> | |
37 | ||
38 | #include "longhaul.h" | |
39 | ||
40 | #define PFX "longhaul: " | |
41 | ||
42 | #define TYPE_LONGHAUL_V1 1 | |
43 | #define TYPE_LONGHAUL_V2 2 | |
44 | #define TYPE_POWERSAVER 3 | |
45 | ||
46 | #define CPU_SAMUEL 1 | |
47 | #define CPU_SAMUEL2 2 | |
48 | #define CPU_EZRA 3 | |
49 | #define CPU_EZRA_T 4 | |
50 | #define CPU_NEHEMIAH 5 | |
51 | ||
52 | static int cpu_model; | |
53 | static unsigned int numscales=16, numvscales; | |
54 | static unsigned int fsb; | |
55 | static int minvid, maxvid; | |
56 | static unsigned int minmult, maxmult; | |
57 | static int can_scale_voltage; | |
58 | static int vrmrev; | |
59 | ||
60 | /* Module parameters */ | |
61 | static int dont_scale_voltage; | |
62 | ||
63 | ||
64 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg) | |
65 | ||
66 | ||
1da177e4 LT |
67 | /* Clock ratios multiplied by 10 */ |
68 | static int clock_ratio[32]; | |
69 | static int eblcr_table[32]; | |
70 | static int voltage_table[32]; | |
71 | static unsigned int highest_speed, lowest_speed; /* kHz */ | |
72 | static int longhaul_version; | |
73 | static struct cpufreq_frequency_table *longhaul_table; | |
74 | ||
75 | #ifdef CONFIG_CPU_FREQ_DEBUG | |
76 | static char speedbuffer[8]; | |
77 | ||
78 | static char *print_speed(int speed) | |
79 | { | |
80 | if (speed > 1000) { | |
81 | if (speed%1000 == 0) | |
82 | sprintf (speedbuffer, "%dGHz", speed/1000); | |
83 | else | |
84 | sprintf (speedbuffer, "%d.%dGHz", speed/1000, (speed%1000)/100); | |
85 | } else | |
86 | sprintf (speedbuffer, "%dMHz", speed); | |
87 | ||
88 | return speedbuffer; | |
89 | } | |
90 | #endif | |
91 | ||
92 | ||
93 | static unsigned int calc_speed(int mult) | |
94 | { | |
95 | int khz; | |
96 | khz = (mult/10)*fsb; | |
97 | if (mult%10) | |
98 | khz += fsb/2; | |
99 | khz *= 1000; | |
100 | return khz; | |
101 | } | |
102 | ||
103 | ||
104 | static int longhaul_get_cpu_mult(void) | |
105 | { | |
106 | unsigned long invalue=0,lo, hi; | |
107 | ||
108 | rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi); | |
109 | invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22; | |
110 | if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) { | |
111 | if (lo & (1<<27)) | |
112 | invalue+=16; | |
113 | } | |
114 | return eblcr_table[invalue]; | |
115 | } | |
116 | ||
117 | ||
118 | static void do_powersaver(union msr_longhaul *longhaul, | |
119 | unsigned int clock_ratio_index) | |
120 | { | |
3be6a48f | 121 | struct pci_dev *dev; |
11746314 DJ |
122 | unsigned long flags; |
123 | unsigned int tmp_mask; | |
124 | int version; | |
3be6a48f DJ |
125 | int i; |
126 | u16 pci_cmd; | |
127 | u16 cmd_state[64]; | |
1da177e4 LT |
128 | |
129 | switch (cpu_model) { | |
130 | case CPU_EZRA_T: | |
131 | version = 3; | |
132 | break; | |
133 | case CPU_NEHEMIAH: | |
134 | version = 0xf; | |
135 | break; | |
136 | default: | |
137 | return; | |
138 | } | |
139 | ||
140 | rdmsrl(MSR_VIA_LONGHAUL, longhaul->val); | |
141 | longhaul->bits.SoftBusRatio = clock_ratio_index & 0xf; | |
142 | longhaul->bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4; | |
143 | longhaul->bits.EnableSoftBusRatio = 1; | |
144 | longhaul->bits.RevisionKey = 0; | |
3be6a48f DJ |
145 | |
146 | preempt_disable(); | |
147 | local_irq_save(flags); | |
148 | ||
149 | /* | |
150 | * get current pci bus master state for all devices | |
151 | * and clear bus master bit | |
152 | */ | |
153 | dev = NULL; | |
154 | i = 0; | |
155 | do { | |
156 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
157 | if (dev != NULL) { | |
158 | pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); | |
159 | cmd_state[i++] = pci_cmd; | |
160 | pci_cmd &= ~PCI_COMMAND_MASTER; | |
161 | pci_write_config_word(dev, PCI_COMMAND, pci_cmd); | |
162 | } | |
163 | } while (dev != NULL); | |
164 | ||
11746314 DJ |
165 | tmp_mask=inb(0x21); /* works on C3. save mask. */ |
166 | outb(0xFE,0x21); /* TMR0 only */ | |
167 | outb(0xFF,0x80); /* delay */ | |
168 | ||
4bb0d3ec | 169 | safe_halt(); |
3be6a48f | 170 | wrmsrl(MSR_VIA_LONGHAUL, longhaul->val); |
4bb0d3ec | 171 | halt(); |
3be6a48f DJ |
172 | |
173 | local_irq_disable(); | |
1da177e4 | 174 | |
11746314 DJ |
175 | outb(tmp_mask,0x21); /* restore mask */ |
176 | ||
3be6a48f DJ |
177 | /* restore pci bus master state for all devices */ |
178 | dev = NULL; | |
179 | i = 0; | |
180 | do { | |
181 | dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); | |
182 | if (dev != NULL) { | |
183 | pci_cmd = cmd_state[i++]; | |
184 | pci_write_config_byte(dev, PCI_COMMAND, pci_cmd); | |
185 | } | |
186 | } while (dev != NULL); | |
187 | local_irq_restore(flags); | |
188 | preempt_enable(); | |
189 | ||
190 | /* disable bus ratio bit */ | |
1da177e4 LT |
191 | rdmsrl(MSR_VIA_LONGHAUL, longhaul->val); |
192 | longhaul->bits.EnableSoftBusRatio = 0; | |
193 | longhaul->bits.RevisionKey = version; | |
1da177e4 | 194 | wrmsrl(MSR_VIA_LONGHAUL, longhaul->val); |
1da177e4 LT |
195 | } |
196 | ||
197 | /** | |
198 | * longhaul_set_cpu_frequency() | |
199 | * @clock_ratio_index : bitpattern of the new multiplier. | |
200 | * | |
201 | * Sets a new clock ratio. | |
202 | */ | |
203 | ||
204 | static void longhaul_setstate(unsigned int clock_ratio_index) | |
205 | { | |
206 | int speed, mult; | |
207 | struct cpufreq_freqs freqs; | |
208 | union msr_longhaul longhaul; | |
209 | union msr_bcr2 bcr2; | |
210 | static unsigned int old_ratio=-1; | |
211 | ||
212 | if (old_ratio == clock_ratio_index) | |
213 | return; | |
214 | old_ratio = clock_ratio_index; | |
215 | ||
216 | mult = clock_ratio[clock_ratio_index]; | |
217 | if (mult == -1) | |
218 | return; | |
219 | ||
220 | speed = calc_speed(mult); | |
221 | if ((speed > highest_speed) || (speed < lowest_speed)) | |
222 | return; | |
223 | ||
224 | freqs.old = calc_speed(longhaul_get_cpu_mult()); | |
225 | freqs.new = speed; | |
226 | freqs.cpu = 0; /* longhaul.c is UP only driver */ | |
227 | ||
228 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
229 | ||
230 | dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n", | |
231 | fsb, mult/10, mult%10, print_speed(speed/1000)); | |
232 | ||
233 | switch (longhaul_version) { | |
234 | ||
235 | /* | |
236 | * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B]) | |
237 | * Software controlled multipliers only. | |
238 | * | |
239 | * *NB* Until we get voltage scaling working v1 & v2 are the same code. | |
240 | * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C] | |
241 | */ | |
242 | case TYPE_LONGHAUL_V1: | |
243 | case TYPE_LONGHAUL_V2: | |
244 | rdmsrl (MSR_VIA_BCR2, bcr2.val); | |
245 | /* Enable software clock multiplier */ | |
246 | bcr2.bits.ESOFTBF = 1; | |
247 | bcr2.bits.CLOCKMUL = clock_ratio_index; | |
248 | local_irq_disable(); | |
249 | wrmsrl (MSR_VIA_BCR2, bcr2.val); | |
4bb0d3ec | 250 | safe_halt(); |
1da177e4 LT |
251 | |
252 | /* Disable software clock multiplier */ | |
253 | rdmsrl (MSR_VIA_BCR2, bcr2.val); | |
254 | bcr2.bits.ESOFTBF = 0; | |
255 | local_irq_disable(); | |
256 | wrmsrl (MSR_VIA_BCR2, bcr2.val); | |
257 | local_irq_enable(); | |
258 | break; | |
259 | ||
260 | /* | |
261 | * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N]) | |
262 | * We can scale voltage with this too, but that's currently | |
263 | * disabled until we come up with a decent 'match freq to voltage' | |
264 | * algorithm. | |
265 | * When we add voltage scaling, we will also need to do the | |
266 | * voltage/freq setting in order depending on the direction | |
267 | * of scaling (like we do in powernow-k7.c) | |
268 | * Nehemiah can do FSB scaling too, but this has never been proven | |
269 | * to work in practice. | |
270 | */ | |
271 | case TYPE_POWERSAVER: | |
272 | do_powersaver(&longhaul, clock_ratio_index); | |
273 | break; | |
274 | } | |
275 | ||
276 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
277 | } | |
278 | ||
279 | /* | |
280 | * Centaur decided to make life a little more tricky. | |
281 | * Only longhaul v1 is allowed to read EBLCR BSEL[0:1]. | |
282 | * Samuel2 and above have to try and guess what the FSB is. | |
283 | * We do this by assuming we booted at maximum multiplier, and interpolate | |
284 | * between that value multiplied by possible FSBs and cpu_mhz which | |
285 | * was calculated at boot time. Really ugly, but no other way to do this. | |
286 | */ | |
287 | ||
288 | #define ROUNDING 0xf | |
289 | ||
290 | static int _guess(int guess) | |
291 | { | |
292 | int target; | |
293 | ||
294 | target = ((maxmult/10)*guess); | |
295 | if (maxmult%10 != 0) | |
296 | target += (guess/2); | |
297 | target += ROUNDING/2; | |
298 | target &= ~ROUNDING; | |
299 | return target; | |
300 | } | |
301 | ||
302 | ||
303 | static int guess_fsb(void) | |
304 | { | |
305 | int speed = (cpu_khz/1000); | |
306 | int i; | |
307 | int speeds[3] = { 66, 100, 133 }; | |
308 | ||
309 | speed += ROUNDING/2; | |
310 | speed &= ~ROUNDING; | |
311 | ||
312 | for (i=0; i<3; i++) { | |
313 | if (_guess(speeds[i]) == speed) | |
314 | return speeds[i]; | |
315 | } | |
316 | return 0; | |
317 | } | |
318 | ||
319 | ||
320 | static int __init longhaul_get_ranges(void) | |
321 | { | |
322 | unsigned long invalue; | |
323 | unsigned int multipliers[32]= { | |
324 | 50,30,40,100,55,35,45,95,90,70,80,60,120,75,85,65, | |
325 | -1,110,120,-1,135,115,125,105,130,150,160,140,-1,155,-1,145 }; | |
326 | unsigned int j, k = 0; | |
327 | union msr_longhaul longhaul; | |
328 | unsigned long lo, hi; | |
329 | unsigned int eblcr_fsb_table_v1[] = { 66, 133, 100, -1 }; | |
330 | unsigned int eblcr_fsb_table_v2[] = { 133, 100, -1, 66 }; | |
331 | ||
332 | switch (longhaul_version) { | |
333 | case TYPE_LONGHAUL_V1: | |
334 | case TYPE_LONGHAUL_V2: | |
335 | /* Ugh, Longhaul v1 didn't have the min/max MSRs. | |
336 | Assume min=3.0x & max = whatever we booted at. */ | |
337 | minmult = 30; | |
338 | maxmult = longhaul_get_cpu_mult(); | |
339 | rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi); | |
340 | invalue = (lo & (1<<18|1<<19)) >>18; | |
341 | if (cpu_model==CPU_SAMUEL || cpu_model==CPU_SAMUEL2) | |
342 | fsb = eblcr_fsb_table_v1[invalue]; | |
343 | else | |
344 | fsb = guess_fsb(); | |
345 | break; | |
346 | ||
347 | case TYPE_POWERSAVER: | |
348 | /* Ezra-T */ | |
349 | if (cpu_model==CPU_EZRA_T) { | |
350 | rdmsrl (MSR_VIA_LONGHAUL, longhaul.val); | |
351 | invalue = longhaul.bits.MaxMHzBR; | |
352 | if (longhaul.bits.MaxMHzBR4) | |
353 | invalue += 16; | |
354 | maxmult=multipliers[invalue]; | |
355 | ||
356 | invalue = longhaul.bits.MinMHzBR; | |
357 | if (longhaul.bits.MinMHzBR4 == 1) | |
358 | minmult = 30; | |
359 | else | |
360 | minmult = multipliers[invalue]; | |
361 | fsb = eblcr_fsb_table_v2[longhaul.bits.MaxMHzFSB]; | |
362 | break; | |
363 | } | |
364 | ||
365 | /* Nehemiah */ | |
366 | if (cpu_model==CPU_NEHEMIAH) { | |
367 | rdmsrl (MSR_VIA_LONGHAUL, longhaul.val); | |
368 | ||
369 | /* | |
370 | * TODO: This code works, but raises a lot of questions. | |
371 | * - Some Nehemiah's seem to have broken Min/MaxMHzBR's. | |
372 | * We get around this by using a hardcoded multiplier of 4.0x | |
373 | * for the minimimum speed, and the speed we booted up at for the max. | |
374 | * This is done in longhaul_get_cpu_mult() by reading the EBLCR register. | |
375 | * - According to some VIA documentation EBLCR is only | |
376 | * in pre-Nehemiah C3s. How this still works is a mystery. | |
377 | * We're possibly using something undocumented and unsupported, | |
378 | * But it works, so we don't grumble. | |
379 | */ | |
380 | minmult=40; | |
381 | maxmult=longhaul_get_cpu_mult(); | |
382 | ||
383 | /* Starting with the 1.2GHz parts, theres a 200MHz bus. */ | |
384 | if ((cpu_khz/1000) > 1200) | |
385 | fsb = 200; | |
386 | else | |
387 | fsb = eblcr_fsb_table_v2[longhaul.bits.MaxMHzFSB]; | |
388 | break; | |
389 | } | |
390 | } | |
391 | ||
392 | dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n", | |
393 | minmult/10, minmult%10, maxmult/10, maxmult%10); | |
394 | ||
395 | if (fsb == -1) { | |
396 | printk (KERN_INFO PFX "Invalid (reserved) FSB!\n"); | |
397 | return -EINVAL; | |
398 | } | |
399 | ||
400 | highest_speed = calc_speed(maxmult); | |
401 | lowest_speed = calc_speed(minmult); | |
402 | dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb, | |
403 | print_speed(lowest_speed/1000), | |
404 | print_speed(highest_speed/1000)); | |
405 | ||
406 | if (lowest_speed == highest_speed) { | |
407 | printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n"); | |
408 | return -EINVAL; | |
409 | } | |
410 | if (lowest_speed > highest_speed) { | |
411 | printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n", | |
412 | lowest_speed, highest_speed); | |
413 | return -EINVAL; | |
414 | } | |
415 | ||
416 | longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL); | |
417 | if(!longhaul_table) | |
418 | return -ENOMEM; | |
419 | ||
420 | for (j=0; j < numscales; j++) { | |
421 | unsigned int ratio; | |
422 | ratio = clock_ratio[j]; | |
423 | if (ratio == -1) | |
424 | continue; | |
425 | if (ratio > maxmult || ratio < minmult) | |
426 | continue; | |
427 | longhaul_table[k].frequency = calc_speed(ratio); | |
428 | longhaul_table[k].index = j; | |
429 | k++; | |
430 | } | |
431 | ||
432 | longhaul_table[k].frequency = CPUFREQ_TABLE_END; | |
433 | if (!k) { | |
434 | kfree (longhaul_table); | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | ||
442 | static void __init longhaul_setup_voltagescaling(void) | |
443 | { | |
444 | union msr_longhaul longhaul; | |
445 | ||
446 | rdmsrl (MSR_VIA_LONGHAUL, longhaul.val); | |
447 | ||
448 | if (!(longhaul.bits.RevisionID & 1)) | |
449 | return; | |
450 | ||
451 | minvid = longhaul.bits.MinimumVID; | |
452 | maxvid = longhaul.bits.MaximumVID; | |
453 | vrmrev = longhaul.bits.VRMRev; | |
454 | ||
455 | if (minvid == 0 || maxvid == 0) { | |
456 | printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. " | |
457 | "Voltage scaling disabled.\n", | |
458 | minvid/1000, minvid%1000, maxvid/1000, maxvid%1000); | |
459 | return; | |
460 | } | |
461 | ||
462 | if (minvid == maxvid) { | |
463 | printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are " | |
464 | "both %d.%03d. Voltage scaling disabled\n", | |
465 | maxvid/1000, maxvid%1000); | |
466 | return; | |
467 | } | |
468 | ||
469 | if (vrmrev==0) { | |
470 | dprintk ("VRM 8.5 \n"); | |
471 | memcpy (voltage_table, vrm85scales, sizeof(voltage_table)); | |
472 | numvscales = (voltage_table[maxvid]-voltage_table[minvid])/25; | |
473 | } else { | |
474 | dprintk ("Mobile VRM \n"); | |
475 | memcpy (voltage_table, mobilevrmscales, sizeof(voltage_table)); | |
476 | numvscales = (voltage_table[maxvid]-voltage_table[minvid])/5; | |
477 | } | |
478 | ||
479 | /* Current voltage isn't readable at first, so we need to | |
480 | set it to a known value. The spec says to use maxvid */ | |
481 | longhaul.bits.RevisionKey = longhaul.bits.RevisionID; /* FIXME: This is bad. */ | |
482 | longhaul.bits.EnableSoftVID = 1; | |
483 | longhaul.bits.SoftVID = maxvid; | |
484 | wrmsrl (MSR_VIA_LONGHAUL, longhaul.val); | |
485 | ||
486 | minvid = voltage_table[minvid]; | |
487 | maxvid = voltage_table[maxvid]; | |
488 | ||
489 | dprintk ("Min VID=%d.%03d Max VID=%d.%03d, %d possible voltage scales\n", | |
490 | maxvid/1000, maxvid%1000, minvid/1000, minvid%1000, numvscales); | |
491 | ||
492 | can_scale_voltage = 1; | |
493 | } | |
494 | ||
495 | ||
496 | static int longhaul_verify(struct cpufreq_policy *policy) | |
497 | { | |
498 | return cpufreq_frequency_table_verify(policy, longhaul_table); | |
499 | } | |
500 | ||
501 | ||
502 | static int longhaul_target(struct cpufreq_policy *policy, | |
503 | unsigned int target_freq, unsigned int relation) | |
504 | { | |
505 | unsigned int table_index = 0; | |
506 | unsigned int new_clock_ratio = 0; | |
507 | ||
508 | if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index)) | |
509 | return -EINVAL; | |
510 | ||
511 | new_clock_ratio = longhaul_table[table_index].index & 0xFF; | |
512 | ||
513 | longhaul_setstate(new_clock_ratio); | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | ||
519 | static unsigned int longhaul_get(unsigned int cpu) | |
520 | { | |
521 | if (cpu) | |
522 | return 0; | |
523 | return calc_speed(longhaul_get_cpu_mult()); | |
524 | } | |
525 | ||
526 | ||
527 | static int __init longhaul_cpu_init(struct cpufreq_policy *policy) | |
528 | { | |
529 | struct cpuinfo_x86 *c = cpu_data; | |
530 | char *cpuname=NULL; | |
531 | int ret; | |
532 | ||
533 | switch (c->x86_model) { | |
534 | case 6: | |
535 | cpu_model = CPU_SAMUEL; | |
536 | cpuname = "C3 'Samuel' [C5A]"; | |
537 | longhaul_version = TYPE_LONGHAUL_V1; | |
538 | memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio)); | |
539 | memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr)); | |
540 | break; | |
541 | ||
542 | case 7: | |
543 | longhaul_version = TYPE_LONGHAUL_V1; | |
544 | switch (c->x86_mask) { | |
545 | case 0: | |
546 | cpu_model = CPU_SAMUEL2; | |
547 | cpuname = "C3 'Samuel 2' [C5B]"; | |
548 | /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */ | |
549 | memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio)); | |
550 | memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr)); | |
551 | break; | |
552 | case 1 ... 15: | |
553 | if (c->x86_mask < 8) { | |
554 | cpu_model = CPU_SAMUEL2; | |
555 | cpuname = "C3 'Samuel 2' [C5B]"; | |
556 | } else { | |
557 | cpu_model = CPU_EZRA; | |
558 | cpuname = "C3 'Ezra' [C5C]"; | |
559 | } | |
560 | memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio)); | |
561 | memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr)); | |
562 | break; | |
563 | } | |
564 | break; | |
565 | ||
566 | case 8: | |
567 | cpu_model = CPU_EZRA_T; | |
568 | cpuname = "C3 'Ezra-T' [C5M]"; | |
569 | longhaul_version = TYPE_POWERSAVER; | |
570 | numscales=32; | |
571 | memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio)); | |
572 | memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr)); | |
573 | break; | |
574 | ||
575 | case 9: | |
576 | cpu_model = CPU_NEHEMIAH; | |
577 | longhaul_version = TYPE_POWERSAVER; | |
578 | numscales=32; | |
579 | switch (c->x86_mask) { | |
580 | case 0 ... 1: | |
581 | cpuname = "C3 'Nehemiah A' [C5N]"; | |
582 | memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio)); | |
583 | memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr)); | |
584 | break; | |
585 | case 2 ... 4: | |
586 | cpuname = "C3 'Nehemiah B' [C5N]"; | |
587 | memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio)); | |
588 | memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr)); | |
589 | break; | |
590 | case 5 ... 15: | |
591 | cpuname = "C3 'Nehemiah C' [C5N]"; | |
592 | memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio)); | |
593 | memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr)); | |
594 | break; | |
595 | } | |
596 | break; | |
597 | ||
598 | default: | |
599 | cpuname = "Unknown"; | |
600 | break; | |
601 | } | |
602 | ||
603 | printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname); | |
604 | switch (longhaul_version) { | |
605 | case TYPE_LONGHAUL_V1: | |
606 | case TYPE_LONGHAUL_V2: | |
607 | printk ("Longhaul v%d supported.\n", longhaul_version); | |
608 | break; | |
609 | case TYPE_POWERSAVER: | |
610 | printk ("Powersaver supported.\n"); | |
611 | break; | |
612 | }; | |
613 | ||
614 | ret = longhaul_get_ranges(); | |
615 | if (ret != 0) | |
616 | return ret; | |
617 | ||
618 | if ((longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) && | |
619 | (dont_scale_voltage==0)) | |
620 | longhaul_setup_voltagescaling(); | |
621 | ||
622 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | |
6778bae0 | 623 | policy->cpuinfo.transition_latency = 200000; /* nsec */ |
1da177e4 LT |
624 | policy->cur = calc_speed(longhaul_get_cpu_mult()); |
625 | ||
626 | ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table); | |
627 | if (ret) | |
628 | return ret; | |
629 | ||
630 | cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu); | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy) | |
636 | { | |
637 | cpufreq_frequency_table_put_attr(policy->cpu); | |
638 | return 0; | |
639 | } | |
640 | ||
641 | static struct freq_attr* longhaul_attr[] = { | |
642 | &cpufreq_freq_attr_scaling_available_freqs, | |
643 | NULL, | |
644 | }; | |
645 | ||
646 | static struct cpufreq_driver longhaul_driver = { | |
647 | .verify = longhaul_verify, | |
648 | .target = longhaul_target, | |
649 | .get = longhaul_get, | |
650 | .init = longhaul_cpu_init, | |
651 | .exit = __devexit_p(longhaul_cpu_exit), | |
652 | .name = "longhaul", | |
653 | .owner = THIS_MODULE, | |
654 | .attr = longhaul_attr, | |
655 | }; | |
656 | ||
657 | ||
658 | static int __init longhaul_init(void) | |
659 | { | |
660 | struct cpuinfo_x86 *c = cpu_data; | |
661 | ||
662 | if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6) | |
663 | return -ENODEV; | |
664 | ||
665 | switch (c->x86_model) { | |
666 | case 6 ... 9: | |
667 | return cpufreq_register_driver(&longhaul_driver); | |
668 | default: | |
669 | printk (KERN_INFO PFX "Unknown VIA CPU. Contact davej@codemonkey.org.uk\n"); | |
670 | } | |
671 | ||
672 | return -ENODEV; | |
673 | } | |
674 | ||
675 | ||
676 | static void __exit longhaul_exit(void) | |
677 | { | |
678 | int i=0; | |
679 | ||
680 | for (i=0; i < numscales; i++) { | |
681 | if (clock_ratio[i] == maxmult) { | |
682 | longhaul_setstate(i); | |
683 | break; | |
684 | } | |
685 | } | |
686 | ||
687 | cpufreq_unregister_driver(&longhaul_driver); | |
688 | kfree(longhaul_table); | |
689 | } | |
690 | ||
691 | module_param (dont_scale_voltage, int, 0644); | |
692 | MODULE_PARM_DESC(dont_scale_voltage, "Don't scale voltage of processor"); | |
693 | ||
694 | MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>"); | |
695 | MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors."); | |
696 | MODULE_LICENSE ("GPL"); | |
697 | ||
698 | module_init(longhaul_init); | |
699 | module_exit(longhaul_exit); | |
700 |