[mirror_ubuntu-artful-kernel.git] / arch / i386 / kernel / cpu / cpufreq / p4-clockmod.c

/*
 *	Pentium 4/Xeon CPU on demand clock modulation/speed scaling
 *	(C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
 *	(C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
 *	(C) 2002 Arjan van de Ven <arjanv@redhat.com>
 *	(C) 2002 Tora T. Engstad
 *	All Rights Reserved
 *
 *	This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 *
 *      The author(s) of this software shall not be held liable for damages
 *      of any nature resulting due to the use of this software. This
 *      software is provided AS-IS with no warranties.
 *
 *	Date		Errata			Description
 *	20020525	N44, O17	12.5% or 25% DC causes lockup
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/cpumask.h>
#include <linux/sched.h>	/* current / set_cpus_allowed() */

#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/timex.h>

#include "speedstep-lib.h"

#define PFX	"p4-clockmod: "
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)

/*
 * Duty Cycle (3bits), note DC_DISABLE is not specified in
 * intel docs i just use it to mean disable
 */
enum {
	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
};

#define DC_ENTRIES	8


static int has_N44_O17_errata[NR_CPUS];
static unsigned int stock_freq;
static struct cpufreq_driver p4clockmod_driver;
static unsigned int cpufreq_p4_get(unsigned int cpu);

static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
{
	u32 l, h;

	if (!cpu_online(cpu) || (newstate > DC_DISABLE) || (newstate == DC_RESV))
		return -EINVAL;

	rdmsr(MSR_IA32_THERM_STATUS, l, h);

	if (l & 0x01)
		dprintk("CPU#%d currently thermal throttled\n", cpu);

	if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
		newstate = DC_38PT;

	rdmsr(MSR_IA32_THERM_CONTROL, l, h);
	if (newstate == DC_DISABLE) {
		dprintk("CPU#%d disabling modulation\n", cpu);
		wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
	} else {
		dprintk("CPU#%d setting duty cycle to %d%%\n",
			cpu, ((125 * newstate) / 10));
		/* bits 63 - 5	: reserved
		 * bit  4	: enable/disable
		 * bits 3-1	: duty cycle
		 * bit  0	: reserved
		 */
		l = (l & ~14);
		l = l | (1<<4) | ((newstate & 0x7)<<1);
		wrmsr(MSR_IA32_THERM_CONTROL, l, h);
	}

	return 0;
}


static struct cpufreq_frequency_table p4clockmod_table[] = {
	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	{DC_DFLT, 0},
	{DC_25PT, 0},
	{DC_38PT, 0},
	{DC_50PT, 0},
	{DC_64PT, 0},
	{DC_75PT, 0},
	{DC_88PT, 0},
	{DC_DISABLE, 0},
	{DC_RESV, CPUFREQ_TABLE_END},
};


static int cpufreq_p4_target(struct cpufreq_policy *policy,
			     unsigned int target_freq,
			     unsigned int relation)
{
	unsigned int    newstate = DC_RESV;
	struct cpufreq_freqs freqs;
	cpumask_t cpus_allowed;
	int i;

	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
		return -EINVAL;

	freqs.old = cpufreq_p4_get(policy->cpu);
	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;

	if (freqs.new == freqs.old)
		return 0;

	/* notifiers */
	for_each_cpu_mask(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	}

	/* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
	 * Developer's Manual, Volume 3
	 */
	cpus_allowed = current->cpus_allowed;

	for_each_cpu_mask(i, policy->cpus) {
		cpumask_t this_cpu = cpumask_of_cpu(i);

		set_cpus_allowed(current, this_cpu);
		BUG_ON(smp_processor_id() != i);

		cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
	}
	set_cpus_allowed(current, cpus_allowed);

	/* notifiers */
	for_each_cpu_mask(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	}

	return 0;
}


static int cpufreq_p4_verify(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
}


static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
{
	if (c->x86 == 0x06) {
		if (cpu_has(c, X86_FEATURE_EST))
			printk(KERN_WARNING PFX "Warning: EST-capable CPU detected. "
			       "The acpi-cpufreq module offers voltage scaling"
			       " in addition of frequency scaling. You should use "
			       "that instead of p4-clockmod, if possible.\n");
		switch (c->x86_model) {
		case 0x0E: /* Core */
		case 0x0F: /* Core Duo */
			p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
			return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PCORE);
		case 0x0D: /* Pentium M (Dothan) */
			p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
			/* fall through */
		case 0x09: /* Pentium M (Banias) */
			return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
		}
	}

	if (c->x86 != 0xF) {
		printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <cpufreq@lists.linux.org.uk>\n");
		return 0;
	}

	/* on P-4s, the TSC runs with constant frequency independent whether
	 * throttling is active or not. */
	p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;

	if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
		printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
		       "The speedstep-ich or acpi cpufreq modules offer "
		       "voltage scaling in addition of frequency scaling. "
		       "You should use either one instead of p4-clockmod, "
		       "if possible.\n");
		return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
	}

	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
}


static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
	int cpuid = 0;
	unsigned int i;

#ifdef CONFIG_SMP
	policy->cpus = cpu_sibling_map[policy->cpu];
#endif

	/* Errata workaround */
	cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
	switch (cpuid) {
	case 0x0f07:
	case 0x0f0a:
	case 0x0f11:
	case 0x0f12:
		has_N44_O17_errata[policy->cpu] = 1;
		dprintk("has errata -- disabling low frequencies\n");
	}

	/* get max frequency */
	stock_freq = cpufreq_p4_get_frequency(c);
	if (!stock_freq)
		return -EINVAL;

	/* table init */
	for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
		if ((i<2) && (has_N44_O17_errata[policy->cpu]))
			p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			p4clockmod_table[i].frequency = (stock_freq * i)/8;
	}
	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);

	/* cpuinfo and default policy values */
	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
	policy->cpuinfo.transition_latency = 1000000; /* assumed */
	policy->cur = stock_freq;

	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
}


static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static unsigned int cpufreq_p4_get(unsigned int cpu)
{
	cpumask_t cpus_allowed;
	u32 l, h;

	cpus_allowed = current->cpus_allowed;

	set_cpus_allowed(current, cpumask_of_cpu(cpu));
	BUG_ON(smp_processor_id() != cpu);

	rdmsr(MSR_IA32_THERM_CONTROL, l, h);

	set_cpus_allowed(current, cpus_allowed);

	if (l & 0x10) {
		l = l >> 1;
		l &= 0x7;
	} else
		l = DC_DISABLE;

	if (l != DC_DISABLE)
		return (stock_freq * l / 8);

	return stock_freq;
}

static struct freq_attr* p4clockmod_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver p4clockmod_driver = {
	.verify		= cpufreq_p4_verify,
	.target		= cpufreq_p4_target,
	.init		= cpufreq_p4_cpu_init,
	.exit		= cpufreq_p4_cpu_exit,
	.get		= cpufreq_p4_get,
	.name		= "p4-clockmod",
	.owner		= THIS_MODULE,
	.attr		= p4clockmod_attr,
};


static int __init cpufreq_p4_init(void)
{
	struct cpuinfo_x86 *c = cpu_data;
	int ret;

	/*
	 * THERM_CONTROL is architectural for IA32 now, so
	 * we can rely on the capability checks
	 */
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return -ENODEV;

	if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
		!test_bit(X86_FEATURE_ACC, c->x86_capability))
		return -ENODEV;

	ret = cpufreq_register_driver(&p4clockmod_driver);
	if (!ret)
		printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");

	return (ret);
}


static void __exit cpufreq_p4_exit(void)
{
	cpufreq_unregister_driver(&p4clockmod_driver);
}


MODULE_AUTHOR ("Zwane Mwaikambo <zwane@commfireservices.com>");
MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
MODULE_LICENSE ("GPL");

late_initcall(cpufreq_p4_init);
module_exit(cpufreq_p4_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Pentium 4/Xeon CPU on demand clock modulation/speed scaling
	3	* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
	4	* (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
	5	* (C) 2002 Arjan van de Ven <arjanv@redhat.com>
	6	* (C) 2002 Tora T. Engstad
	7	* All Rights Reserved
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* The author(s) of this software shall not be held liable for damages
	15	* of any nature resulting due to the use of this software. This
	16	* software is provided AS-IS with no warranties.
32ee8c3e	17	*
1da177e4 LT	18	* Date Errata Description
	19	* 20020525 N44, O17 12.5% or 25% DC causes lockup
	20	*
	21	*/
	22
1da177e4	23	#include <linux/kernel.h>
32ee8c3e	24	#include <linux/module.h>
1da177e4 LT	25	#include <linux/init.h>
	26	#include <linux/smp.h>
	27	#include <linux/cpufreq.h>
	28	#include <linux/slab.h>
	29	#include <linux/cpumask.h>
4e57b681	30	#include <linux/sched.h> /* current / set_cpus_allowed() */
1da177e4	31
32ee8c3e	32	#include <asm/processor.h>
1da177e4 LT	33	#include <asm/msr.h>
	34	#include <asm/timex.h>
	35
	36	#include "speedstep-lib.h"
	37
	38	#define PFX "p4-clockmod: "
	39	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)
	40
	41	/*
	42	* Duty Cycle (3bits), note DC_DISABLE is not specified in
	43	* intel docs i just use it to mean disable
	44	*/
	45	enum {
	46	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	47	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
	48	};
	49
	50	#define DC_ENTRIES 8
	51
	52
	53	static int has_N44_O17_errata[NR_CPUS];
	54	static unsigned int stock_freq;
	55	static struct cpufreq_driver p4clockmod_driver;
	56	static unsigned int cpufreq_p4_get(unsigned int cpu);
	57
	58	static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
	59	{
	60	u32 l, h;
	61
	62	if (!cpu_online(cpu) \|\| (newstate > DC_DISABLE) \|\| (newstate == DC_RESV))
	63	return -EINVAL;
	64
	65	rdmsr(MSR_IA32_THERM_STATUS, l, h);
	66
	67	if (l & 0x01)
	68	dprintk("CPU#%d currently thermal throttled\n", cpu);
	69
	70	if (has_N44_O17_errata[cpu] && (newstate == DC_25PT \|\| newstate == DC_DFLT))
	71	newstate = DC_38PT;
	72
	73	rdmsr(MSR_IA32_THERM_CONTROL, l, h);
	74	if (newstate == DC_DISABLE) {
	75	dprintk("CPU#%d disabling modulation\n", cpu);
	76	wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
	77	} else {
	78	dprintk("CPU#%d setting duty cycle to %d%%\n",
	79	cpu, ((125 * newstate) / 10));
32ee8c3e	80	/* bits 63 - 5 : reserved
1da177e4 LT	81	* bit 4 : enable/disable
	82	* bits 3-1 : duty cycle
	83	* bit 0 : reserved
	84	*/
	85	l = (l & ~14);
	86	l = l \| (1<<4) \| ((newstate & 0x7)<<1);
	87	wrmsr(MSR_IA32_THERM_CONTROL, l, h);
	88	}
	89
	90	return 0;
	91	}
	92
	93
	94	static struct cpufreq_frequency_table p4clockmod_table[] = {
	95	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	96	{DC_DFLT, 0},
	97	{DC_25PT, 0},
	98	{DC_38PT, 0},
	99	{DC_50PT, 0},
	100	{DC_64PT, 0},
	101	{DC_75PT, 0},
	102	{DC_88PT, 0},
	103	{DC_DISABLE, 0},
	104	{DC_RESV, CPUFREQ_TABLE_END},
	105	};
	106
	107
	108	static int cpufreq_p4_target(struct cpufreq_policy *policy,
	109	unsigned int target_freq,
	110	unsigned int relation)
	111	{
	112	unsigned int newstate = DC_RESV;
	113	struct cpufreq_freqs freqs;
	114	cpumask_t cpus_allowed;
	115	int i;
	116
	117	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
	118	return -EINVAL;
	119
	120	freqs.old = cpufreq_p4_get(policy->cpu);
	121	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
	122
	123	if (freqs.new == freqs.old)
	124	return 0;
	125
	126	/* notifiers */
	127	for_each_cpu_mask(i, policy->cpus) {
	128	freqs.cpu = i;
	129	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	130	}
	131
	132	/* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
32ee8c3e	133	* Developer's Manual, Volume 3
1da177e4 LT	134	*/
	135	cpus_allowed = current->cpus_allowed;
	136
	137	for_each_cpu_mask(i, policy->cpus) {
	138	cpumask_t this_cpu = cpumask_of_cpu(i);
	139
	140	set_cpus_allowed(current, this_cpu);
	141	BUG_ON(smp_processor_id() != i);
	142
	143	cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
	144	}
	145	set_cpus_allowed(current, cpus_allowed);
	146
	147	/* notifiers */
	148	for_each_cpu_mask(i, policy->cpus) {
	149	freqs.cpu = i;
	150	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	151	}
	152
	153	return 0;
	154	}
	155
	156
	157	static int cpufreq_p4_verify(struct cpufreq_policy *policy)
	158	{
	159	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
	160	}
	161
	162
	163	static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
	164	{
4e74663c DB	165	if (c->x86 == 0x06) {
	166	if (cpu_has(c, X86_FEATURE_EST))
	167	printk(KERN_WARNING PFX "Warning: EST-capable CPU detected. "
	168	"The acpi-cpufreq module offers voltage scaling"
	169	" in addition of frequency scaling. You should use "
	170	"that instead of p4-clockmod, if possible.\n");
	171	switch (c->x86_model) {
	172	case 0x0E: /* Core */
	173	case 0x0F: /* Core Duo */
	174	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	175	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PCORE);
	176	case 0x0D: /* Pentium M (Dothan) */
	177	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	178	/* fall through */
	179	case 0x09: /* Pentium M (Banias) */
	180	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
	181	}
1da177e4 LT	182	}
	183
	184	if (c->x86 != 0xF) {
4e74663c	185	printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <cpufreq@lists.linux.org.uk>\n");
1da177e4 LT	186	return 0;
	187	}
	188
	189	/* on P-4s, the TSC runs with constant frequency independent whether
	190	* throttling is active or not. */
	191	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	192
	193	if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
	194	printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
	195	"The speedstep-ich or acpi cpufreq modules offer "
	196	"voltage scaling in addition of frequency scaling. "
	197	"You should use either one instead of p4-clockmod, "
	198	"if possible.\n");
	199	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
	200	}
	201
	202	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
	203	}
	204
32ee8c3e	205
1da177e4 LT	206
	207	static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
	208	{
	209	struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
	210	int cpuid = 0;
	211	unsigned int i;
	212
	213	#ifdef CONFIG_SMP
	214	policy->cpus = cpu_sibling_map[policy->cpu];
	215	#endif
	216
	217	/* Errata workaround */
	218	cpuid = (c->x86 << 8) \| (c->x86_model << 4) \| c->x86_mask;
	219	switch (cpuid) {
	220	case 0x0f07:
	221	case 0x0f0a:
	222	case 0x0f11:
	223	case 0x0f12:
	224	has_N44_O17_errata[policy->cpu] = 1;
	225	dprintk("has errata -- disabling low frequencies\n");
	226	}
32ee8c3e	227
1da177e4 LT	228	/* get max frequency */
	229	stock_freq = cpufreq_p4_get_frequency(c);
	230	if (!stock_freq)
	231	return -EINVAL;
	232
	233	/* table init */
	234	for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
	235	if ((i<2) && (has_N44_O17_errata[policy->cpu]))
	236	p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	237	else
	238	p4clockmod_table[i].frequency = (stock_freq * i)/8;
	239	}
	240	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
32ee8c3e	241
1da177e4 LT	242	/* cpuinfo and default policy values */
	243	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
	244	policy->cpuinfo.transition_latency = 1000000; /* assumed */
	245	policy->cur = stock_freq;
	246
	247	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
	248	}
	249
	250
	251	static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
	252	{
32ee8c3e	253	cpufreq_frequency_table_put_attr(policy->cpu);
1da177e4 LT	254	return 0;
	255	}
	256
	257	static unsigned int cpufreq_p4_get(unsigned int cpu)
	258	{
	259	cpumask_t cpus_allowed;
	260	u32 l, h;
	261
	262	cpus_allowed = current->cpus_allowed;
	263
	264	set_cpus_allowed(current, cpumask_of_cpu(cpu));
	265	BUG_ON(smp_processor_id() != cpu);
	266
	267	rdmsr(MSR_IA32_THERM_CONTROL, l, h);
	268
	269	set_cpus_allowed(current, cpus_allowed);
	270
	271	if (l & 0x10) {
	272	l = l >> 1;
	273	l &= 0x7;
	274	} else
	275	l = DC_DISABLE;
	276
	277	if (l != DC_DISABLE)
	278	return (stock_freq * l / 8);
	279
	280	return stock_freq;
	281	}
	282
	283	static struct freq_attr* p4clockmod_attr[] = {
	284	&cpufreq_freq_attr_scaling_available_freqs,
	285	NULL,
	286	};
	287
	288	static struct cpufreq_driver p4clockmod_driver = {
32ee8c3e	289	.verify = cpufreq_p4_verify,
1da177e4 LT	290	.target = cpufreq_p4_target,
	291	.init = cpufreq_p4_cpu_init,
	292	.exit = cpufreq_p4_cpu_exit,
	293	.get = cpufreq_p4_get,
	294	.name = "p4-clockmod",
	295	.owner = THIS_MODULE,
	296	.attr = p4clockmod_attr,
	297	};
	298
	299
	300	static int __init cpufreq_p4_init(void)
32ee8c3e	301	{
1da177e4 LT	302	struct cpuinfo_x86 *c = cpu_data;
	303	int ret;
	304
	305	/*
32ee8c3e	306	* THERM_CONTROL is architectural for IA32 now, so
1da177e4 LT	307	* we can rely on the capability checks
	308	*/
	309	if (c->x86_vendor != X86_VENDOR_INTEL)
	310	return -ENODEV;
	311
	312	if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) \|\|
	313	!test_bit(X86_FEATURE_ACC, c->x86_capability))
	314	return -ENODEV;
	315
	316	ret = cpufreq_register_driver(&p4clockmod_driver);
	317	if (!ret)
	318	printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
	319
	320	return (ret);
	321	}
	322
	323
	324	static void __exit cpufreq_p4_exit(void)
	325	{
	326	cpufreq_unregister_driver(&p4clockmod_driver);
	327	}
	328
	329
	330	MODULE_AUTHOR ("Zwane Mwaikambo <zwane@commfireservices.com>");
	331	MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
	332	MODULE_LICENSE ("GPL");
	333
	334	late_initcall(cpufreq_p4_init);
	335	module_exit(cpufreq_p4_exit);