[mirror_ubuntu-eoan-kernel.git] / arch / i386 / kernel / cpu / cpufreq / powernow-k8.h

/*
 *  (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
 *  Your use of this code is subject to the terms and conditions of the
 *  GNU general public license version 2. See "COPYING" or
 *  http://www.gnu.org/licenses/gpl.html
 */

struct powernow_k8_data {
	unsigned int cpu;

	u32 numps;  /* number of p-states */
	u32 batps;  /* number of p-states supported on battery */

	/* these values are constant when the PSB is used to determine
	 * vid/fid pairings, but are modified during the ->target() call
	 * when ACPI is used */
	u32 rvo;     /* ramp voltage offset */
	u32 irt;     /* isochronous relief time */
	u32 vidmvs;  /* usable value calculated from mvs */
	u32 vstable; /* voltage stabilization time, units 20 us */
	u32 plllock; /* pll lock time, units 1 us */
        u32 exttype; /* extended interface = 1 */

	/* keep track of the current fid / vid */
	u32 currvid, currfid;

	/* the powernow_table includes all frequency and vid/fid pairings:
	 * fid are the lower 8 bits of the index, vid are the upper 8 bits.
	 * frequency is in kHz */
	struct cpufreq_frequency_table  *powernow_table;

#ifdef CONFIG_X86_POWERNOW_K8_ACPI
	/* the acpi table needs to be kept. it's only available if ACPI was
	 * used to determine valid frequency/vid/fid states */
	struct acpi_processor_performance acpi_data;
#endif
};


/* processor's cpuid instruction support */
#define CPUID_PROCESSOR_SIGNATURE	1	/* function 1 */
#define CPUID_XFAM			0x0ff00000	/* extended family */
#define CPUID_XFAM_K8			0
#define CPUID_XMOD			0x000f0000	/* extended model */
#define CPUID_XMOD_REV_G		0x00060000
#define CPUID_USE_XFAM_XMOD		0x00000f00
#define CPUID_GET_MAX_CAPABILITIES	0x80000000
#define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
#define P_STATE_TRANSITION_CAPABLE	6

/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
/* the register number is placed in ecx, and the data is returned in edx:eax. */

#define MSR_FIDVID_CTL      0xc0010041
#define MSR_FIDVID_STATUS   0xc0010042

/* Field definitions within the FID VID Low Control MSR : */
#define MSR_C_LO_INIT_FID_VID     0x00010000
#define MSR_C_LO_NEW_VID          0x00003f00
#define MSR_C_LO_NEW_FID          0x0000003f
#define MSR_C_LO_VID_SHIFT        8

/* Field definitions within the FID VID High Control MSR : */
#define MSR_C_HI_STP_GNT_TO	  0x000fffff

/* Field definitions within the FID VID Low Status MSR : */
#define MSR_S_LO_CHANGE_PENDING   0x80000000   /* cleared when completed */
#define MSR_S_LO_MAX_RAMP_VID     0x3f000000
#define MSR_S_LO_MAX_FID          0x003f0000
#define MSR_S_LO_START_FID        0x00003f00
#define MSR_S_LO_CURRENT_FID      0x0000003f

/* Field definitions within the FID VID High Status MSR : */
#define MSR_S_HI_MIN_WORKING_VID  0x3f000000
#define MSR_S_HI_MAX_WORKING_VID  0x003f0000
#define MSR_S_HI_START_VID        0x00003f00
#define MSR_S_HI_CURRENT_VID      0x0000003f
#define MSR_C_HI_STP_GNT_BENIGN	  0x00000001

/*
 * There are restrictions frequencies have to follow:
 * - only 1 entry in the low fid table ( <=1.4GHz )
 * - lowest entry in the high fid table must be >= 2 * the entry in the
 *   low fid table
 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
 *   in the low fid table
 * - the parts can only step at <= 200 MHz intervals, odd fid values are
 *   supported in revision G and later revisions.
 * - lowest frequency must be >= interprocessor hypertransport link speed
 *   (only applies to MP systems obviously)
 */

/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
#define LO_FID_TABLE_TOP     7	/* fid values marking the boundary    */
#define HI_FID_TABLE_BOTTOM  8	/* between the low and high tables    */

#define LO_VCOFREQ_TABLE_TOP    1400	/* corresponding vco frequency values */
#define HI_VCOFREQ_TABLE_BOTTOM 1600

#define MIN_FREQ_RESOLUTION  200 /* fids jump by 2 matching freq jumps by 200 */

#define MAX_FID 0x2a	/* Spec only gives FID values as far as 5 GHz */
#define LEAST_VID 0x3e	/* Lowest (numerically highest) useful vid value */

#define MIN_FREQ 800	/* Min and max freqs, per spec */
#define MAX_FREQ 5000

#define INVALID_FID_MASK 0xffffffc0  /* not a valid fid if these bits are set */
#define INVALID_VID_MASK 0xffffffc0  /* not a valid vid if these bits are set */

#define VID_OFF 0x3f

#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */

#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */

#define MAXIMUM_VID_STEPS 1  /* Current cpus only allow a single step of 25mV */
#define VST_UNITS_20US 20   /* Voltage Stabalization Time is in units of 20us */

/*
 * Most values of interest are enocoded in a single field of the _PSS
 * entries: the "control" value.
 */

#define IRT_SHIFT      30
#define RVO_SHIFT      28
#define EXT_TYPE_SHIFT 27
#define PLL_L_SHIFT    20
#define MVS_SHIFT      18
#define VST_SHIFT      11
#define VID_SHIFT       6
#define IRT_MASK        3
#define RVO_MASK        3
#define EXT_TYPE_MASK   1
#define PLL_L_MASK   0x7f
#define MVS_MASK        3
#define VST_MASK     0x7f
#define VID_MASK     0x1f
#define FID_MASK     0x3f


/*
 * Version 1.4 of the PSB table. This table is constructed by BIOS and is
 * to tell the OS's power management driver which VIDs and FIDs are
 * supported by this particular processor.
 * If the data in the PSB / PST is wrong, then this driver will program the
 * wrong values into hardware, which is very likely to lead to a crash.
 */

#define PSB_ID_STRING      "AMDK7PNOW!"
#define PSB_ID_STRING_LEN  10

#define PSB_VERSION_1_4  0x14

struct psb_s {
	u8 signature[10];
	u8 tableversion;
	u8 flags1;
	u16 vstable;
	u8 flags2;
	u8 num_tables;
	u32 cpuid;
	u8 plllocktime;
	u8 maxfid;
	u8 maxvid;
	u8 numps;
};

/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
struct pst_s {
	u8 fid;
	u8 vid;
};

#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg)

static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid);
static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);

static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);

#ifdef CONFIG_SMP
static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
{
}
#else
static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
{
	cpu_set(0, cpu_sharedcore_mask[0]);
}
#endif
Commit	Line	Data
1da177e4	1	/*
841e40b3	2	* (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
1da177e4 LT	3	* Your use of this code is subject to the terms and conditions of the
	4	* GNU general public license version 2. See "COPYING" or
	5	* http://www.gnu.org/licenses/gpl.html
	6	*/
	7
	8	struct powernow_k8_data {
	9	unsigned int cpu;
	10
	11	u32 numps; /* number of p-states */
	12	u32 batps; /* number of p-states supported on battery */
	13
	14	/* these values are constant when the PSB is used to determine
	15	* vid/fid pairings, but are modified during the ->target() call
	16	* when ACPI is used */
	17	u32 rvo; /* ramp voltage offset */
	18	u32 irt; /* isochronous relief time */
	19	u32 vidmvs; /* usable value calculated from mvs */
	20	u32 vstable; /* voltage stabilization time, units 20 us */
	21	u32 plllock; /* pll lock time, units 1 us */
841e40b3	22	u32 exttype; /* extended interface = 1 */
1da177e4 LT	23
	24	/* keep track of the current fid / vid */
	25	u32 currvid, currfid;
	26
	27	/* the powernow_table includes all frequency and vid/fid pairings:
	28	* fid are the lower 8 bits of the index, vid are the upper 8 bits.
	29	* frequency is in kHz */
	30	struct cpufreq_frequency_table *powernow_table;
	31
	32	#ifdef CONFIG_X86_POWERNOW_K8_ACPI
	33	/* the acpi table needs to be kept. it's only available if ACPI was
	34	* used to determine valid frequency/vid/fid states */
	35	struct acpi_processor_performance acpi_data;
	36	#endif
	37	};
	38
	39
	40	/* processor's cpuid instruction support */
	41	#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
	42	#define CPUID_XFAM 0x0ff00000 /* extended family */
	43	#define CPUID_XFAM_K8 0
	44	#define CPUID_XMOD 0x000f0000 /* extended model */
019a61b9	45	#define CPUID_XMOD_REV_G 0x00060000
1da177e4 LT	46	#define CPUID_USE_XFAM_XMOD 0x00000f00
	47	#define CPUID_GET_MAX_CAPABILITIES 0x80000000
	48	#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
	49	#define P_STATE_TRANSITION_CAPABLE 6
	50
	51	/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
	52	/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
	53	/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
	54	/* the register number is placed in ecx, and the data is returned in edx:eax. */
	55
	56	#define MSR_FIDVID_CTL 0xc0010041
	57	#define MSR_FIDVID_STATUS 0xc0010042
	58
	59	/* Field definitions within the FID VID Low Control MSR : */
	60	#define MSR_C_LO_INIT_FID_VID 0x00010000
841e40b3 DJ	61	#define MSR_C_LO_NEW_VID 0x00003f00
841e40b3 DJ	62	#define MSR_C_LO_NEW_FID 0x0000003f
1da177e4 LT	63	#define MSR_C_LO_VID_SHIFT 8
	64
	65	/* Field definitions within the FID VID High Control MSR : */
32ee8c3e	66	#define MSR_C_HI_STP_GNT_TO 0x000fffff
1da177e4 LT	67
1da177e4 LT	68	/* Field definitions within the FID VID Low Status MSR : */
841e40b3 DJ	69	#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
841e40b3 DJ	70	#define MSR_S_LO_MAX_RAMP_VID 0x3f000000
1da177e4 LT	71	#define MSR_S_LO_MAX_FID 0x003f0000
	72	#define MSR_S_LO_START_FID 0x00003f00
	73	#define MSR_S_LO_CURRENT_FID 0x0000003f
	74
	75	/* Field definitions within the FID VID High Status MSR : */
841e40b3 DJ	76	#define MSR_S_HI_MIN_WORKING_VID 0x3f000000
	77	#define MSR_S_HI_MAX_WORKING_VID 0x003f0000
	78	#define MSR_S_HI_START_VID 0x00003f00
	79	#define MSR_S_HI_CURRENT_VID 0x0000003f
	80	#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
1da177e4 LT	81
	82	/*
	83	* There are restrictions frequencies have to follow:
	84	* - only 1 entry in the low fid table ( <=1.4GHz )
	85	* - lowest entry in the high fid table must be >= 2 * the entry in the
	86	* low fid table
	87	* - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
	88	* in the low fid table
019a61b9 LM	89	* - the parts can only step at <= 200 MHz intervals, odd fid values are
019a61b9 LM	90	* supported in revision G and later revisions.
1da177e4 LT	91	* - lowest frequency must be >= interprocessor hypertransport link speed
	92	* (only applies to MP systems obviously)
	93	*/
	94
	95	/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
019a61b9	96	#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
1da177e4 LT	97	#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
	98
	99	#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
	100	#define HI_VCOFREQ_TABLE_BOTTOM 1600
	101
	102	#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
	103
	104	#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
841e40b3	105	#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
1da177e4 LT	106
	107	#define MIN_FREQ 800 /* Min and max freqs, per spec */
	108	#define MAX_FREQ 5000
	109
019a61b9	110	#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
841e40b3 DJ	111	#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
	112
	113	#define VID_OFF 0x3f
1da177e4 LT	114
	115	#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
	116
	117	#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
	118
	119	#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
	120	#define VST_UNITS_20US 20 /* Voltage Stabalization Time is in units of 20us */
	121
	122	/*
	123	* Most values of interest are enocoded in a single field of the _PSS
	124	* entries: the "control" value.
	125	*/
32ee8c3e	126
1da177e4 LT	127	#define IRT_SHIFT 30
1da177e4 LT	128	#define RVO_SHIFT 28
2bcad935	129	#define EXT_TYPE_SHIFT 27
1da177e4 LT	130	#define PLL_L_SHIFT 20
	131	#define MVS_SHIFT 18
	132	#define VST_SHIFT 11
	133	#define VID_SHIFT 6
	134	#define IRT_MASK 3
	135	#define RVO_MASK 3
2bcad935	136	#define EXT_TYPE_MASK 1
1da177e4 LT	137	#define PLL_L_MASK 0x7f
	138	#define MVS_MASK 3
	139	#define VST_MASK 0x7f
	140	#define VID_MASK 0x1f
	141	#define FID_MASK 0x3f
	142
	143
	144	/*
	145	* Version 1.4 of the PSB table. This table is constructed by BIOS and is
	146	* to tell the OS's power management driver which VIDs and FIDs are
	147	* supported by this particular processor.
	148	* If the data in the PSB / PST is wrong, then this driver will program the
	149	* wrong values into hardware, which is very likely to lead to a crash.
	150	*/
	151
	152	#define PSB_ID_STRING "AMDK7PNOW!"
	153	#define PSB_ID_STRING_LEN 10
	154
	155	#define PSB_VERSION_1_4 0x14
	156
	157	struct psb_s {
	158	u8 signature[10];
	159	u8 tableversion;
	160	u8 flags1;
	161	u16 vstable;
	162	u8 flags2;
	163	u8 num_tables;
	164	u32 cpuid;
	165	u8 plllocktime;
	166	u8 maxfid;
	167	u8 maxvid;
	168	u8 numps;
	169	};
	170
	171	/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
	172	struct pst_s {
	173	u8 fid;
	174	u8 vid;
	175	};
	176
	177	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg)
	178
	179	static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid);
	180	static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
	181	static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
	182
	183	static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
065b807c	184
065b807c DJ	185	#ifdef CONFIG_SMP
	186	static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
	187	{
	188	}
	189	#else
	190	static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
	191	{
	192	cpu_set(0, cpu_sharedcore_mask[0]);
	193	}
	194	#endif