]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium | |
3 | * M (part of the Centrino chipset). | |
4 | * | |
5 | * Despite the "SpeedStep" in the name, this is almost entirely unlike | |
6 | * traditional SpeedStep. | |
7 | * | |
8 | * Modelled on speedstep.c | |
9 | * | |
10 | * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org> | |
11 | * | |
12 | * WARNING WARNING WARNING | |
13 | * | |
14 | * This driver manipulates the PERF_CTL MSR, which is only somewhat | |
15 | * documented. While it seems to work on my laptop, it has not been | |
16 | * tested anywhere else, and it may not work for you, do strange | |
17 | * things or simply crash. | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/config.h> | |
4e57b681 | 25 | #include <linux/sched.h> /* current */ |
1da177e4 LT |
26 | #include <linux/delay.h> |
27 | #include <linux/compiler.h> | |
28 | ||
29 | #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI | |
30 | #include <linux/acpi.h> | |
31 | #include <acpi/processor.h> | |
32 | #endif | |
33 | ||
34 | #include <asm/msr.h> | |
35 | #include <asm/processor.h> | |
36 | #include <asm/cpufeature.h> | |
37 | ||
38 | #include "speedstep-est-common.h" | |
39 | ||
40 | #define PFX "speedstep-centrino: " | |
41 | #define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>" | |
42 | ||
43 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg) | |
44 | ||
45 | ||
46 | struct cpu_id | |
47 | { | |
48 | __u8 x86; /* CPU family */ | |
49 | __u8 x86_model; /* model */ | |
50 | __u8 x86_mask; /* stepping */ | |
51 | }; | |
52 | ||
53 | enum { | |
54 | CPU_BANIAS, | |
55 | CPU_DOTHAN_A1, | |
56 | CPU_DOTHAN_A2, | |
57 | CPU_DOTHAN_B0, | |
8282864a DJ |
58 | CPU_MP4HT_D0, |
59 | CPU_MP4HT_E0, | |
1da177e4 LT |
60 | }; |
61 | ||
62 | static const struct cpu_id cpu_ids[] = { | |
63 | [CPU_BANIAS] = { 6, 9, 5 }, | |
64 | [CPU_DOTHAN_A1] = { 6, 13, 1 }, | |
65 | [CPU_DOTHAN_A2] = { 6, 13, 2 }, | |
66 | [CPU_DOTHAN_B0] = { 6, 13, 6 }, | |
8282864a DJ |
67 | [CPU_MP4HT_D0] = {15, 3, 4 }, |
68 | [CPU_MP4HT_E0] = {15, 4, 1 }, | |
1da177e4 | 69 | }; |
38e548ee | 70 | #define N_IDS ARRAY_SIZE(cpu_ids) |
1da177e4 LT |
71 | |
72 | struct cpu_model | |
73 | { | |
74 | const struct cpu_id *cpu_id; | |
75 | const char *model_name; | |
76 | unsigned max_freq; /* max clock in kHz */ | |
77 | ||
78 | struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */ | |
79 | }; | |
80 | static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x); | |
81 | ||
82 | /* Operating points for current CPU */ | |
83 | static struct cpu_model *centrino_model[NR_CPUS]; | |
84 | static const struct cpu_id *centrino_cpu[NR_CPUS]; | |
85 | ||
86 | static struct cpufreq_driver centrino_driver; | |
87 | ||
88 | #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE | |
89 | ||
90 | /* Computes the correct form for IA32_PERF_CTL MSR for a particular | |
91 | frequency/voltage operating point; frequency in MHz, volts in mV. | |
92 | This is stored as "index" in the structure. */ | |
93 | #define OP(mhz, mv) \ | |
94 | { \ | |
95 | .frequency = (mhz) * 1000, \ | |
96 | .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \ | |
97 | } | |
98 | ||
99 | /* | |
100 | * These voltage tables were derived from the Intel Pentium M | |
101 | * datasheet, document 25261202.pdf, Table 5. I have verified they | |
102 | * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium | |
103 | * M. | |
104 | */ | |
105 | ||
106 | /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */ | |
107 | static struct cpufreq_frequency_table banias_900[] = | |
108 | { | |
109 | OP(600, 844), | |
110 | OP(800, 988), | |
111 | OP(900, 1004), | |
112 | { .frequency = CPUFREQ_TABLE_END } | |
113 | }; | |
114 | ||
115 | /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */ | |
116 | static struct cpufreq_frequency_table banias_1000[] = | |
117 | { | |
118 | OP(600, 844), | |
119 | OP(800, 972), | |
120 | OP(900, 988), | |
121 | OP(1000, 1004), | |
122 | { .frequency = CPUFREQ_TABLE_END } | |
123 | }; | |
124 | ||
125 | /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */ | |
126 | static struct cpufreq_frequency_table banias_1100[] = | |
127 | { | |
128 | OP( 600, 956), | |
129 | OP( 800, 1020), | |
130 | OP( 900, 1100), | |
131 | OP(1000, 1164), | |
132 | OP(1100, 1180), | |
133 | { .frequency = CPUFREQ_TABLE_END } | |
134 | }; | |
135 | ||
136 | ||
137 | /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */ | |
138 | static struct cpufreq_frequency_table banias_1200[] = | |
139 | { | |
140 | OP( 600, 956), | |
141 | OP( 800, 1004), | |
142 | OP( 900, 1020), | |
143 | OP(1000, 1100), | |
144 | OP(1100, 1164), | |
145 | OP(1200, 1180), | |
146 | { .frequency = CPUFREQ_TABLE_END } | |
147 | }; | |
148 | ||
149 | /* Intel Pentium M processor 1.30GHz (Banias) */ | |
150 | static struct cpufreq_frequency_table banias_1300[] = | |
151 | { | |
152 | OP( 600, 956), | |
153 | OP( 800, 1260), | |
154 | OP(1000, 1292), | |
155 | OP(1200, 1356), | |
156 | OP(1300, 1388), | |
157 | { .frequency = CPUFREQ_TABLE_END } | |
158 | }; | |
159 | ||
160 | /* Intel Pentium M processor 1.40GHz (Banias) */ | |
161 | static struct cpufreq_frequency_table banias_1400[] = | |
162 | { | |
163 | OP( 600, 956), | |
164 | OP( 800, 1180), | |
165 | OP(1000, 1308), | |
166 | OP(1200, 1436), | |
167 | OP(1400, 1484), | |
168 | { .frequency = CPUFREQ_TABLE_END } | |
169 | }; | |
170 | ||
171 | /* Intel Pentium M processor 1.50GHz (Banias) */ | |
172 | static struct cpufreq_frequency_table banias_1500[] = | |
173 | { | |
174 | OP( 600, 956), | |
175 | OP( 800, 1116), | |
176 | OP(1000, 1228), | |
177 | OP(1200, 1356), | |
178 | OP(1400, 1452), | |
179 | OP(1500, 1484), | |
180 | { .frequency = CPUFREQ_TABLE_END } | |
181 | }; | |
182 | ||
183 | /* Intel Pentium M processor 1.60GHz (Banias) */ | |
184 | static struct cpufreq_frequency_table banias_1600[] = | |
185 | { | |
186 | OP( 600, 956), | |
187 | OP( 800, 1036), | |
188 | OP(1000, 1164), | |
189 | OP(1200, 1276), | |
190 | OP(1400, 1420), | |
191 | OP(1600, 1484), | |
192 | { .frequency = CPUFREQ_TABLE_END } | |
193 | }; | |
194 | ||
195 | /* Intel Pentium M processor 1.70GHz (Banias) */ | |
196 | static struct cpufreq_frequency_table banias_1700[] = | |
197 | { | |
198 | OP( 600, 956), | |
199 | OP( 800, 1004), | |
200 | OP(1000, 1116), | |
201 | OP(1200, 1228), | |
202 | OP(1400, 1308), | |
203 | OP(1700, 1484), | |
204 | { .frequency = CPUFREQ_TABLE_END } | |
205 | }; | |
206 | #undef OP | |
207 | ||
208 | #define _BANIAS(cpuid, max, name) \ | |
209 | { .cpu_id = cpuid, \ | |
210 | .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \ | |
211 | .max_freq = (max)*1000, \ | |
212 | .op_points = banias_##max, \ | |
213 | } | |
214 | #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max) | |
215 | ||
216 | /* CPU models, their operating frequency range, and freq/voltage | |
217 | operating points */ | |
218 | static struct cpu_model models[] = | |
219 | { | |
220 | _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"), | |
221 | BANIAS(1000), | |
222 | BANIAS(1100), | |
223 | BANIAS(1200), | |
224 | BANIAS(1300), | |
225 | BANIAS(1400), | |
226 | BANIAS(1500), | |
227 | BANIAS(1600), | |
228 | BANIAS(1700), | |
229 | ||
230 | /* NULL model_name is a wildcard */ | |
231 | { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL }, | |
232 | { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL }, | |
233 | { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL }, | |
8282864a DJ |
234 | { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL }, |
235 | { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL }, | |
1da177e4 LT |
236 | |
237 | { NULL, } | |
238 | }; | |
239 | #undef _BANIAS | |
240 | #undef BANIAS | |
241 | ||
242 | static int centrino_cpu_init_table(struct cpufreq_policy *policy) | |
243 | { | |
244 | struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu]; | |
245 | struct cpu_model *model; | |
246 | ||
247 | for(model = models; model->cpu_id != NULL; model++) | |
248 | if (centrino_verify_cpu_id(cpu, model->cpu_id) && | |
249 | (model->model_name == NULL || | |
250 | strcmp(cpu->x86_model_id, model->model_name) == 0)) | |
251 | break; | |
252 | ||
253 | if (model->cpu_id == NULL) { | |
254 | /* No match at all */ | |
255 | dprintk(KERN_INFO PFX "no support for CPU model \"%s\": " | |
256 | "send /proc/cpuinfo to " MAINTAINER "\n", | |
257 | cpu->x86_model_id); | |
258 | return -ENOENT; | |
259 | } | |
260 | ||
261 | if (model->op_points == NULL) { | |
262 | /* Matched a non-match */ | |
52c18fd2 | 263 | dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n", |
1da177e4 LT |
264 | cpu->x86_model_id); |
265 | #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI | |
266 | dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n"); | |
267 | #endif | |
268 | return -ENOENT; | |
269 | } | |
270 | ||
271 | centrino_model[policy->cpu] = model; | |
272 | ||
273 | dprintk("found \"%s\": max frequency: %dkHz\n", | |
274 | model->model_name, model->max_freq); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | #else | |
280 | static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; } | |
281 | #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */ | |
282 | ||
283 | static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x) | |
284 | { | |
285 | if ((c->x86 == x->x86) && | |
286 | (c->x86_model == x->x86_model) && | |
287 | (c->x86_mask == x->x86_mask)) | |
288 | return 1; | |
289 | return 0; | |
290 | } | |
291 | ||
292 | /* To be called only after centrino_model is initialized */ | |
293 | static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) | |
294 | { | |
295 | int i; | |
296 | ||
297 | /* | |
298 | * Extract clock in kHz from PERF_CTL value | |
299 | * for centrino, as some DSDTs are buggy. | |
300 | * Ideally, this can be done using the acpi_data structure. | |
301 | */ | |
302 | if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) || | |
303 | (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) || | |
304 | (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) { | |
305 | msr = (msr >> 8) & 0xff; | |
306 | return msr * 100000; | |
307 | } | |
308 | ||
309 | if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points)) | |
310 | return 0; | |
311 | ||
312 | msr &= 0xffff; | |
313 | for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) { | |
314 | if (msr == centrino_model[cpu]->op_points[i].index) | |
315 | return centrino_model[cpu]->op_points[i].frequency; | |
316 | } | |
317 | if (failsafe) | |
318 | return centrino_model[cpu]->op_points[i-1].frequency; | |
319 | else | |
320 | return 0; | |
321 | } | |
322 | ||
323 | /* Return the current CPU frequency in kHz */ | |
324 | static unsigned int get_cur_freq(unsigned int cpu) | |
325 | { | |
326 | unsigned l, h; | |
327 | unsigned clock_freq; | |
328 | cpumask_t saved_mask; | |
329 | ||
330 | saved_mask = current->cpus_allowed; | |
331 | set_cpus_allowed(current, cpumask_of_cpu(cpu)); | |
332 | if (smp_processor_id() != cpu) | |
333 | return 0; | |
334 | ||
335 | rdmsr(MSR_IA32_PERF_STATUS, l, h); | |
336 | clock_freq = extract_clock(l, cpu, 0); | |
337 | ||
338 | if (unlikely(clock_freq == 0)) { | |
339 | /* | |
340 | * On some CPUs, we can see transient MSR values (which are | |
341 | * not present in _PSS), while CPU is doing some automatic | |
342 | * P-state transition (like TM2). Get the last freq set | |
343 | * in PERF_CTL. | |
344 | */ | |
345 | rdmsr(MSR_IA32_PERF_CTL, l, h); | |
346 | clock_freq = extract_clock(l, cpu, 1); | |
347 | } | |
348 | ||
349 | set_cpus_allowed(current, saved_mask); | |
350 | return clock_freq; | |
351 | } | |
352 | ||
353 | ||
354 | #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI | |
355 | ||
356 | static struct acpi_processor_performance p; | |
357 | ||
358 | /* | |
359 | * centrino_cpu_init_acpi - register with ACPI P-States library | |
360 | * | |
361 | * Register with the ACPI P-States library (part of drivers/acpi/processor.c) | |
362 | * in order to determine correct frequency and voltage pairings by reading | |
363 | * the _PSS of the ACPI DSDT or SSDT tables. | |
364 | */ | |
365 | static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) | |
366 | { | |
1da177e4 LT |
367 | unsigned long cur_freq; |
368 | int result = 0, i; | |
369 | unsigned int cpu = policy->cpu; | |
370 | ||
1da177e4 LT |
371 | /* register with ACPI core */ |
372 | if (acpi_processor_register_performance(&p, cpu)) { | |
373 | dprintk(KERN_INFO PFX "obtaining ACPI data failed\n"); | |
374 | return -EIO; | |
375 | } | |
376 | ||
377 | /* verify the acpi_data */ | |
378 | if (p.state_count <= 1) { | |
379 | dprintk("No P-States\n"); | |
380 | result = -ENODEV; | |
381 | goto err_unreg; | |
382 | } | |
383 | ||
384 | if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) || | |
385 | (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { | |
386 | dprintk("Invalid control/status registers (%x - %x)\n", | |
387 | p.control_register.space_id, p.status_register.space_id); | |
388 | result = -EIO; | |
389 | goto err_unreg; | |
390 | } | |
391 | ||
392 | for (i=0; i<p.state_count; i++) { | |
393 | if (p.states[i].control != p.states[i].status) { | |
123411f2 | 394 | dprintk("Different control (%llu) and status values (%llu)\n", |
1da177e4 LT |
395 | p.states[i].control, p.states[i].status); |
396 | result = -EINVAL; | |
397 | goto err_unreg; | |
398 | } | |
399 | ||
400 | if (!p.states[i].core_frequency) { | |
401 | dprintk("Zero core frequency for state %u\n", i); | |
402 | result = -EINVAL; | |
403 | goto err_unreg; | |
404 | } | |
405 | ||
406 | if (p.states[i].core_frequency > p.states[0].core_frequency) { | |
123411f2 | 407 | dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i, |
1da177e4 LT |
408 | p.states[i].core_frequency, p.states[0].core_frequency); |
409 | p.states[i].core_frequency = 0; | |
410 | continue; | |
411 | } | |
412 | } | |
413 | ||
bfdc708d | 414 | centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL); |
1da177e4 LT |
415 | if (!centrino_model[cpu]) { |
416 | result = -ENOMEM; | |
417 | goto err_unreg; | |
418 | } | |
1da177e4 LT |
419 | |
420 | centrino_model[cpu]->model_name=NULL; | |
421 | centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000; | |
422 | centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) * | |
423 | (p.state_count + 1), GFP_KERNEL); | |
424 | if (!centrino_model[cpu]->op_points) { | |
425 | result = -ENOMEM; | |
426 | goto err_kfree; | |
427 | } | |
428 | ||
429 | for (i=0; i<p.state_count; i++) { | |
430 | centrino_model[cpu]->op_points[i].index = p.states[i].control; | |
431 | centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000; | |
432 | dprintk("adding state %i with frequency %u and control value %04x\n", | |
433 | i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index); | |
434 | } | |
435 | centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END; | |
436 | ||
437 | cur_freq = get_cur_freq(cpu); | |
438 | ||
439 | for (i=0; i<p.state_count; i++) { | |
440 | if (!p.states[i].core_frequency) { | |
441 | dprintk("skipping state %u\n", i); | |
442 | centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID; | |
443 | continue; | |
444 | } | |
445 | ||
446 | if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) != | |
447 | (centrino_model[cpu]->op_points[i].frequency)) { | |
448 | dprintk("Invalid encoded frequency (%u vs. %u)\n", | |
449 | extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0), | |
450 | centrino_model[cpu]->op_points[i].frequency); | |
451 | result = -EINVAL; | |
452 | goto err_kfree_all; | |
453 | } | |
454 | ||
455 | if (cur_freq == centrino_model[cpu]->op_points[i].frequency) | |
456 | p.state = i; | |
457 | } | |
458 | ||
459 | /* notify BIOS that we exist */ | |
460 | acpi_processor_notify_smm(THIS_MODULE); | |
461 | ||
462 | return 0; | |
463 | ||
464 | err_kfree_all: | |
465 | kfree(centrino_model[cpu]->op_points); | |
466 | err_kfree: | |
467 | kfree(centrino_model[cpu]); | |
468 | err_unreg: | |
469 | acpi_processor_unregister_performance(&p, cpu); | |
470 | dprintk(KERN_INFO PFX "invalid ACPI data\n"); | |
471 | return (result); | |
472 | } | |
473 | #else | |
474 | static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; } | |
475 | #endif | |
476 | ||
477 | static int centrino_cpu_init(struct cpufreq_policy *policy) | |
478 | { | |
479 | struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu]; | |
480 | unsigned freq; | |
481 | unsigned l, h; | |
482 | int ret; | |
483 | int i; | |
484 | ||
485 | /* Only Intel makes Enhanced Speedstep-capable CPUs */ | |
486 | if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST)) | |
487 | return -ENODEV; | |
488 | ||
1da177e4 LT |
489 | if (is_const_loops_cpu(policy->cpu)) { |
490 | centrino_driver.flags |= CPUFREQ_CONST_LOOPS; | |
491 | } | |
492 | ||
493 | if (centrino_cpu_init_acpi(policy)) { | |
494 | if (policy->cpu != 0) | |
495 | return -ENODEV; | |
496 | ||
f914be79 VP |
497 | for (i = 0; i < N_IDS; i++) |
498 | if (centrino_verify_cpu_id(cpu, &cpu_ids[i])) | |
499 | break; | |
500 | ||
501 | if (i != N_IDS) | |
502 | centrino_cpu[policy->cpu] = &cpu_ids[i]; | |
503 | ||
1da177e4 LT |
504 | if (!centrino_cpu[policy->cpu]) { |
505 | dprintk(KERN_INFO PFX "found unsupported CPU with " | |
506 | "Enhanced SpeedStep: send /proc/cpuinfo to " | |
507 | MAINTAINER "\n"); | |
508 | return -ENODEV; | |
509 | } | |
510 | ||
511 | if (centrino_cpu_init_table(policy)) { | |
512 | return -ENODEV; | |
513 | } | |
514 | } | |
515 | ||
516 | /* Check to see if Enhanced SpeedStep is enabled, and try to | |
517 | enable it if not. */ | |
518 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
519 | ||
520 | if (!(l & (1<<16))) { | |
521 | l |= (1<<16); | |
522 | dprintk("trying to enable Enhanced SpeedStep (%x)\n", l); | |
523 | wrmsr(MSR_IA32_MISC_ENABLE, l, h); | |
524 | ||
525 | /* check to see if it stuck */ | |
526 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
527 | if (!(l & (1<<16))) { | |
528 | printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n"); | |
529 | return -ENODEV; | |
530 | } | |
531 | } | |
532 | ||
533 | freq = get_cur_freq(policy->cpu); | |
534 | ||
535 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | |
536 | policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */ | |
537 | policy->cur = freq; | |
538 | ||
539 | dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur); | |
540 | ||
541 | ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points); | |
542 | if (ret) | |
543 | return (ret); | |
544 | ||
545 | cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu); | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
550 | static int centrino_cpu_exit(struct cpufreq_policy *policy) | |
551 | { | |
552 | unsigned int cpu = policy->cpu; | |
553 | ||
554 | if (!centrino_model[cpu]) | |
555 | return -ENODEV; | |
556 | ||
557 | cpufreq_frequency_table_put_attr(cpu); | |
558 | ||
559 | #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI | |
560 | if (!centrino_model[cpu]->model_name) { | |
561 | dprintk("unregistering and freeing ACPI data\n"); | |
562 | acpi_processor_unregister_performance(&p, cpu); | |
563 | kfree(centrino_model[cpu]->op_points); | |
564 | kfree(centrino_model[cpu]); | |
565 | } | |
566 | #endif | |
567 | ||
568 | centrino_model[cpu] = NULL; | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | /** | |
574 | * centrino_verify - verifies a new CPUFreq policy | |
575 | * @policy: new policy | |
576 | * | |
577 | * Limit must be within this model's frequency range at least one | |
578 | * border included. | |
579 | */ | |
580 | static int centrino_verify (struct cpufreq_policy *policy) | |
581 | { | |
582 | return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points); | |
583 | } | |
584 | ||
585 | /** | |
586 | * centrino_setpolicy - set a new CPUFreq policy | |
587 | * @policy: new policy | |
588 | * @target_freq: the target frequency | |
589 | * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H) | |
590 | * | |
591 | * Sets a new CPUFreq policy. | |
592 | */ | |
593 | static int centrino_target (struct cpufreq_policy *policy, | |
594 | unsigned int target_freq, | |
595 | unsigned int relation) | |
596 | { | |
597 | unsigned int newstate = 0; | |
598 | unsigned int msr, oldmsr, h, cpu = policy->cpu; | |
599 | struct cpufreq_freqs freqs; | |
600 | cpumask_t saved_mask; | |
601 | int retval; | |
602 | ||
603 | if (centrino_model[cpu] == NULL) | |
604 | return -ENODEV; | |
605 | ||
606 | /* | |
607 | * Support for SMP systems. | |
608 | * Make sure we are running on the CPU that wants to change frequency | |
609 | */ | |
610 | saved_mask = current->cpus_allowed; | |
611 | set_cpus_allowed(current, policy->cpus); | |
612 | if (!cpu_isset(smp_processor_id(), policy->cpus)) { | |
613 | dprintk("couldn't limit to CPUs in this domain\n"); | |
614 | return(-EAGAIN); | |
615 | } | |
616 | ||
617 | if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq, | |
618 | relation, &newstate)) { | |
619 | retval = -EINVAL; | |
620 | goto migrate_end; | |
621 | } | |
622 | ||
623 | msr = centrino_model[cpu]->op_points[newstate].index; | |
624 | rdmsr(MSR_IA32_PERF_CTL, oldmsr, h); | |
625 | ||
626 | if (msr == (oldmsr & 0xffff)) { | |
627 | retval = 0; | |
628 | dprintk("no change needed - msr was and needs to be %x\n", oldmsr); | |
629 | goto migrate_end; | |
630 | } | |
631 | ||
632 | freqs.cpu = cpu; | |
633 | freqs.old = extract_clock(oldmsr, cpu, 0); | |
634 | freqs.new = extract_clock(msr, cpu, 0); | |
635 | ||
636 | dprintk("target=%dkHz old=%d new=%d msr=%04x\n", | |
637 | target_freq, freqs.old, freqs.new, msr); | |
638 | ||
639 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
640 | ||
641 | /* all but 16 LSB are "reserved", so treat them with | |
642 | care */ | |
643 | oldmsr &= ~0xffff; | |
644 | msr &= 0xffff; | |
645 | oldmsr |= msr; | |
646 | ||
647 | wrmsr(MSR_IA32_PERF_CTL, oldmsr, h); | |
648 | ||
649 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
650 | ||
651 | retval = 0; | |
652 | migrate_end: | |
653 | set_cpus_allowed(current, saved_mask); | |
654 | return (retval); | |
655 | } | |
656 | ||
657 | static struct freq_attr* centrino_attr[] = { | |
658 | &cpufreq_freq_attr_scaling_available_freqs, | |
659 | NULL, | |
660 | }; | |
661 | ||
662 | static struct cpufreq_driver centrino_driver = { | |
663 | .name = "centrino", /* should be speedstep-centrino, | |
664 | but there's a 16 char limit */ | |
665 | .init = centrino_cpu_init, | |
666 | .exit = centrino_cpu_exit, | |
667 | .verify = centrino_verify, | |
668 | .target = centrino_target, | |
669 | .get = get_cur_freq, | |
670 | .attr = centrino_attr, | |
671 | .owner = THIS_MODULE, | |
672 | }; | |
673 | ||
674 | ||
675 | /** | |
676 | * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver | |
677 | * | |
678 | * Initializes the Enhanced SpeedStep support. Returns -ENODEV on | |
679 | * unsupported devices, -ENOENT if there's no voltage table for this | |
680 | * particular CPU model, -EINVAL on problems during initiatization, | |
681 | * and zero on success. | |
682 | * | |
683 | * This is quite picky. Not only does the CPU have to advertise the | |
684 | * "est" flag in the cpuid capability flags, we look for a specific | |
685 | * CPU model and stepping, and we need to have the exact model name in | |
686 | * our voltage tables. That is, be paranoid about not releasing | |
687 | * someone's valuable magic smoke. | |
688 | */ | |
689 | static int __init centrino_init(void) | |
690 | { | |
691 | struct cpuinfo_x86 *cpu = cpu_data; | |
692 | ||
693 | if (!cpu_has(cpu, X86_FEATURE_EST)) | |
694 | return -ENODEV; | |
695 | ||
696 | return cpufreq_register_driver(¢rino_driver); | |
697 | } | |
698 | ||
699 | static void __exit centrino_exit(void) | |
700 | { | |
701 | cpufreq_unregister_driver(¢rino_driver); | |
702 | } | |
703 | ||
704 | MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>"); | |
705 | MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors."); | |
706 | MODULE_LICENSE ("GPL"); | |
707 | ||
708 | late_initcall(centrino_init); | |
709 | module_exit(centrino_exit); |