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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/kernel.h> | |
3 | ||
4 | #include <linux/string.h> | |
5 | #include <linux/bitops.h> | |
6 | #include <linux/smp.h> | |
7 | #include <linux/thread_info.h> | |
53e86b91 | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | |
10 | #include <asm/processor.h> | |
11 | #include <asm/msr.h> | |
12 | #include <asm/uaccess.h> | |
13 | ||
14 | #include "cpu.h" | |
15 | ||
16 | #ifdef CONFIG_X86_LOCAL_APIC | |
17 | #include <asm/mpspec.h> | |
18 | #include <asm/apic.h> | |
19 | #include <mach_apic.h> | |
20 | #endif | |
21 | ||
22 | extern int trap_init_f00f_bug(void); | |
23 | ||
24 | #ifdef CONFIG_X86_INTEL_USERCOPY | |
25 | /* | |
26 | * Alignment at which movsl is preferred for bulk memory copies. | |
27 | */ | |
6c036527 | 28 | struct movsl_mask movsl_mask __read_mostly; |
1da177e4 LT |
29 | #endif |
30 | ||
3bc9b76b | 31 | void __cpuinit early_intel_workaround(struct cpuinfo_x86 *c) |
1da177e4 LT |
32 | { |
33 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
34 | return; | |
35 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
36 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
37 | c->x86_cache_alignment = 128; | |
38 | } | |
39 | ||
40 | /* | |
41 | * Early probe support logic for ppro memory erratum #50 | |
42 | * | |
43 | * This is called before we do cpu ident work | |
44 | */ | |
45 | ||
3bc9b76b | 46 | int __cpuinit ppro_with_ram_bug(void) |
1da177e4 LT |
47 | { |
48 | /* Uses data from early_cpu_detect now */ | |
49 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
50 | boot_cpu_data.x86 == 6 && | |
51 | boot_cpu_data.x86_model == 1 && | |
52 | boot_cpu_data.x86_mask < 8) { | |
53 | printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); | |
54 | return 1; | |
55 | } | |
56 | return 0; | |
57 | } | |
58 | ||
59 | ||
60 | /* | |
61 | * P4 Xeon errata 037 workaround. | |
62 | * Hardware prefetcher may cause stale data to be loaded into the cache. | |
63 | */ | |
3bc9b76b | 64 | static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c) |
1da177e4 LT |
65 | { |
66 | unsigned long lo, hi; | |
67 | ||
68 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { | |
69 | rdmsr (MSR_IA32_MISC_ENABLE, lo, hi); | |
70 | if ((lo & (1<<9)) == 0) { | |
71 | printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); | |
72 | printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); | |
73 | lo |= (1<<9); /* Disable hw prefetching */ | |
74 | wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); | |
75 | } | |
76 | } | |
77 | } | |
78 | ||
79 | ||
3dd9d514 AK |
80 | /* |
81 | * find out the number of processor cores on the die | |
82 | */ | |
3bc9b76b | 83 | static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 84 | { |
f2ab4461 | 85 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 AK |
86 | |
87 | if (c->cpuid_level < 4) | |
88 | return 1; | |
89 | ||
f2ab4461 ZA |
90 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
91 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 AK |
92 | if (eax & 0x1f) |
93 | return ((eax >> 26) + 1); | |
94 | else | |
95 | return 1; | |
96 | } | |
97 | ||
3bc9b76b | 98 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
99 | { |
100 | unsigned int l2 = 0; | |
101 | char *p = NULL; | |
102 | ||
103 | #ifdef CONFIG_X86_F00F_BUG | |
104 | /* | |
105 | * All current models of Pentium and Pentium with MMX technology CPUs | |
106 | * have the F0 0F bug, which lets nonprivileged users lock up the system. | |
107 | * Note that the workaround only should be initialized once... | |
108 | */ | |
109 | c->f00f_bug = 0; | |
4f205fd4 | 110 | if (!paravirt_enabled() && c->x86 == 5) { |
1da177e4 LT |
111 | static int f00f_workaround_enabled = 0; |
112 | ||
113 | c->f00f_bug = 1; | |
114 | if ( !f00f_workaround_enabled ) { | |
115 | trap_init_f00f_bug(); | |
116 | printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); | |
117 | f00f_workaround_enabled = 1; | |
118 | } | |
119 | } | |
120 | #endif | |
121 | ||
122 | select_idle_routine(c); | |
123 | l2 = init_intel_cacheinfo(c); | |
0080e667 VP |
124 | if (c->cpuid_level > 9 ) { |
125 | unsigned eax = cpuid_eax(10); | |
126 | /* Check for version and the number of counters */ | |
127 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
128 | set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability); | |
129 | } | |
1da177e4 LT |
130 | |
131 | /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */ | |
132 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | |
133 | clear_bit(X86_FEATURE_SEP, c->x86_capability); | |
134 | ||
135 | /* Names for the Pentium II/Celeron processors | |
136 | detectable only by also checking the cache size. | |
137 | Dixon is NOT a Celeron. */ | |
138 | if (c->x86 == 6) { | |
139 | switch (c->x86_model) { | |
140 | case 5: | |
141 | if (c->x86_mask == 0) { | |
142 | if (l2 == 0) | |
143 | p = "Celeron (Covington)"; | |
144 | else if (l2 == 256) | |
145 | p = "Mobile Pentium II (Dixon)"; | |
146 | } | |
147 | break; | |
148 | ||
149 | case 6: | |
150 | if (l2 == 128) | |
151 | p = "Celeron (Mendocino)"; | |
152 | else if (c->x86_mask == 0 || c->x86_mask == 5) | |
153 | p = "Celeron-A"; | |
154 | break; | |
155 | ||
156 | case 8: | |
157 | if (l2 == 128) | |
158 | p = "Celeron (Coppermine)"; | |
159 | break; | |
160 | } | |
161 | } | |
162 | ||
163 | if ( p ) | |
164 | strcpy(c->x86_model_id, p); | |
165 | ||
94605eff | 166 | c->x86_max_cores = num_cpu_cores(c); |
3dd9d514 | 167 | |
1da177e4 LT |
168 | detect_ht(c); |
169 | ||
170 | /* Work around errata */ | |
171 | Intel_errata_workarounds(c); | |
172 | ||
173 | #ifdef CONFIG_X86_INTEL_USERCOPY | |
174 | /* | |
175 | * Set up the preferred alignment for movsl bulk memory moves | |
176 | */ | |
177 | switch (c->x86) { | |
178 | case 4: /* 486: untested */ | |
179 | break; | |
180 | case 5: /* Old Pentia: untested */ | |
181 | break; | |
182 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
183 | movsl_mask.mask = 7; | |
184 | break; | |
185 | case 15: /* P4 is OK down to 8-byte alignment */ | |
186 | movsl_mask.mask = 7; | |
187 | break; | |
188 | } | |
189 | #endif | |
190 | ||
39b3a791 | 191 | if (c->x86 == 15) |
1da177e4 LT |
192 | set_bit(X86_FEATURE_P4, c->x86_capability); |
193 | if (c->x86 == 6) | |
194 | set_bit(X86_FEATURE_P3, c->x86_capability); | |
39b3a791 AK |
195 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
196 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
197 | set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); | |
1da177e4 | 198 | |
42ed458a SE |
199 | if (cpu_has_ds) { |
200 | unsigned int l1; | |
201 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
202 | if (!(l1 & (1<<12))) | |
203 | set_bit(X86_FEATURE_PEBS, c->x86_capability); | |
204 | } | |
205 | } | |
1da177e4 | 206 | |
e9dff0ee | 207 | static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size) |
1da177e4 LT |
208 | { |
209 | /* Intel PIII Tualatin. This comes in two flavours. | |
210 | * One has 256kb of cache, the other 512. We have no way | |
211 | * to determine which, so we use a boottime override | |
212 | * for the 512kb model, and assume 256 otherwise. | |
213 | */ | |
214 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
215 | size = 256; | |
216 | return size; | |
217 | } | |
218 | ||
3bc9b76b | 219 | static struct cpu_dev intel_cpu_dev __cpuinitdata = { |
1da177e4 LT |
220 | .c_vendor = "Intel", |
221 | .c_ident = { "GenuineIntel" }, | |
222 | .c_models = { | |
223 | { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = | |
224 | { | |
225 | [0] = "486 DX-25/33", | |
226 | [1] = "486 DX-50", | |
227 | [2] = "486 SX", | |
228 | [3] = "486 DX/2", | |
229 | [4] = "486 SL", | |
230 | [5] = "486 SX/2", | |
231 | [7] = "486 DX/2-WB", | |
232 | [8] = "486 DX/4", | |
233 | [9] = "486 DX/4-WB" | |
234 | } | |
235 | }, | |
236 | { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = | |
237 | { | |
238 | [0] = "Pentium 60/66 A-step", | |
239 | [1] = "Pentium 60/66", | |
240 | [2] = "Pentium 75 - 200", | |
241 | [3] = "OverDrive PODP5V83", | |
242 | [4] = "Pentium MMX", | |
243 | [7] = "Mobile Pentium 75 - 200", | |
244 | [8] = "Mobile Pentium MMX" | |
245 | } | |
246 | }, | |
247 | { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = | |
248 | { | |
249 | [0] = "Pentium Pro A-step", | |
250 | [1] = "Pentium Pro", | |
251 | [3] = "Pentium II (Klamath)", | |
252 | [4] = "Pentium II (Deschutes)", | |
253 | [5] = "Pentium II (Deschutes)", | |
254 | [6] = "Mobile Pentium II", | |
255 | [7] = "Pentium III (Katmai)", | |
256 | [8] = "Pentium III (Coppermine)", | |
257 | [10] = "Pentium III (Cascades)", | |
258 | [11] = "Pentium III (Tualatin)", | |
259 | } | |
260 | }, | |
261 | { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = | |
262 | { | |
263 | [0] = "Pentium 4 (Unknown)", | |
264 | [1] = "Pentium 4 (Willamette)", | |
265 | [2] = "Pentium 4 (Northwood)", | |
266 | [4] = "Pentium 4 (Foster)", | |
267 | [5] = "Pentium 4 (Foster)", | |
268 | } | |
269 | }, | |
270 | }, | |
271 | .c_init = init_intel, | |
1da177e4 LT |
272 | .c_size_cache = intel_size_cache, |
273 | }; | |
274 | ||
275 | __init int intel_cpu_init(void) | |
276 | { | |
277 | cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev; | |
278 | return 0; | |
279 | } | |
280 | ||
53e86b91 NP |
281 | #ifndef CONFIG_X86_CMPXCHG |
282 | unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new) | |
283 | { | |
284 | u8 prev; | |
285 | unsigned long flags; | |
286 | ||
287 | /* Poor man's cmpxchg for 386. Unsuitable for SMP */ | |
288 | local_irq_save(flags); | |
289 | prev = *(u8 *)ptr; | |
290 | if (prev == old) | |
291 | *(u8 *)ptr = new; | |
292 | local_irq_restore(flags); | |
293 | return prev; | |
294 | } | |
295 | EXPORT_SYMBOL(cmpxchg_386_u8); | |
296 | ||
297 | unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new) | |
298 | { | |
299 | u16 prev; | |
300 | unsigned long flags; | |
301 | ||
302 | /* Poor man's cmpxchg for 386. Unsuitable for SMP */ | |
303 | local_irq_save(flags); | |
304 | prev = *(u16 *)ptr; | |
305 | if (prev == old) | |
306 | *(u16 *)ptr = new; | |
307 | local_irq_restore(flags); | |
308 | return prev; | |
309 | } | |
310 | EXPORT_SYMBOL(cmpxchg_386_u16); | |
311 | ||
312 | unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new) | |
313 | { | |
314 | u32 prev; | |
315 | unsigned long flags; | |
316 | ||
317 | /* Poor man's cmpxchg for 386. Unsuitable for SMP */ | |
318 | local_irq_save(flags); | |
319 | prev = *(u32 *)ptr; | |
320 | if (prev == old) | |
321 | *(u32 *)ptr = new; | |
322 | local_irq_restore(flags); | |
323 | return prev; | |
324 | } | |
325 | EXPORT_SYMBOL(cmpxchg_386_u32); | |
326 | #endif | |
327 | ||
1da177e4 LT |
328 | // arch_initcall(intel_cpu_init); |
329 |