[mirror_ubuntu-artful-kernel.git] / arch / i386 / kernel / hpet.c

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/errno.h>
#include <linux/hpet.h>
#include <linux/init.h>

#include <asm/hpet.h>
#include <asm/io.h>

extern struct clock_event_device *global_clock_event;

#define HPET_MASK	CLOCKSOURCE_MASK(32)
#define HPET_SHIFT	22

/* FSEC = 10^-15 NSEC = 10^-9 */
#define FSEC_PER_NSEC	1000000

/*
 * HPET address is set in acpi/boot.c, when an ACPI entry exists
 */
unsigned long hpet_address;
static void __iomem * hpet_virt_address;

static inline unsigned long hpet_readl(unsigned long a)
{
	return readl(hpet_virt_address + a);
}

static inline void hpet_writel(unsigned long d, unsigned long a)
{
	writel(d, hpet_virt_address + a);
}

/*
 * HPET command line enable / disable
 */
static int boot_hpet_disable;

static int __init hpet_setup(char* str)
{
	if (str) {
		if (!strncmp("disable", str, 7))
			boot_hpet_disable = 1;
	}
	return 1;
}
__setup("hpet=", hpet_setup);

static inline int is_hpet_capable(void)
{
	return (!boot_hpet_disable && hpet_address);
}

/*
 * HPET timer interrupt enable / disable
 */
static int hpet_legacy_int_enabled;

/**
 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 */
int is_hpet_enabled(void)
{
	return is_hpet_capable() && hpet_legacy_int_enabled;
}

/*
 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 * timer 0 and timer 1 in case of RTC emulation.
 */
#ifdef CONFIG_HPET
static void hpet_reserve_platform_timers(unsigned long id)
{
	struct hpet __iomem *hpet = hpet_virt_address;
	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	unsigned int nrtimers, i;
	struct hpet_data hd;

	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;

	memset(&hd, 0, sizeof (hd));
	hd.hd_phys_address = hpet_address;
	hd.hd_address = hpet_virt_address;
	hd.hd_nirqs = nrtimers;
	hd.hd_flags = HPET_DATA_PLATFORM;
	hpet_reserve_timer(&hd, 0);

#ifdef CONFIG_HPET_EMULATE_RTC
	hpet_reserve_timer(&hd, 1);
#endif

	hd.hd_irq[0] = HPET_LEGACY_8254;
	hd.hd_irq[1] = HPET_LEGACY_RTC;

	for (i = 2; i < nrtimers; timer++, i++)
		hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
			Tn_INT_ROUTE_CNF_SHIFT;

	hpet_alloc(&hd);

}
#else
static void hpet_reserve_platform_timers(unsigned long id) { }
#endif

/*
 * Common hpet info
 */
static unsigned long hpet_period;

static void hpet_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt);
static int hpet_next_event(unsigned long delta,
			   struct clock_event_device *evt);

/*
 * The hpet clock event device
 */
static struct clock_event_device hpet_clockevent = {
	.name		= "hpet",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= hpet_set_mode,
	.set_next_event = hpet_next_event,
	.shift		= 32,
	.irq		= 0,
};

static void hpet_start_counter(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg &= ~HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
	hpet_writel(0, HPET_COUNTER);
	hpet_writel(0, HPET_COUNTER + 4);
	cfg |= HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
}

static void hpet_enable_int(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg |= HPET_CFG_LEGACY;
	hpet_writel(cfg, HPET_CFG);
	hpet_legacy_int_enabled = 1;
}

static void hpet_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	unsigned long cfg, cmp, now;
	uint64_t delta;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
		delta >>= hpet_clockevent.shift;
		now = hpet_readl(HPET_COUNTER);
		cmp = now + (unsigned long) delta;
		cfg = hpet_readl(HPET_T0_CFG);
		cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
		       HPET_TN_SETVAL | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		/*
		 * The first write after writing TN_SETVAL to the
		 * config register sets the counter value, the second
		 * write sets the period.
		 */
		hpet_writel(cmp, HPET_T0_CMP);
		udelay(1);
		hpet_writel((unsigned long) delta, HPET_T0_CMP);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_PERIODIC;
		cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T0_CFG);
		break;
	}
}

static int hpet_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	unsigned long cnt;

	cnt = hpet_readl(HPET_COUNTER);
	cnt += delta;
	hpet_writel(cnt, HPET_T0_CMP);

	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0);
}

/*
 * Try to setup the HPET timer
 */
int __init hpet_enable(void)
{
	unsigned long id;
	uint64_t hpet_freq;

	if (!is_hpet_capable())
		return 0;

	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);

	/*
	 * Read the period and check for a sane value:
	 */
	hpet_period = hpet_readl(HPET_PERIOD);
	if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
		goto out_nohpet;

	/*
	 * The period is a femto seconds value. We need to calculate the
	 * scaled math multiplication factor for nanosecond to hpet tick
	 * conversion.
	 */
	hpet_freq = 1000000000000000ULL;
	do_div(hpet_freq, hpet_period);
	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
				      NSEC_PER_SEC, 32);
	/* Calculate the min / max delta */
	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
							   &hpet_clockevent);
	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
							   &hpet_clockevent);

	/*
	 * Read the HPET ID register to retrieve the IRQ routing
	 * information and the number of channels
	 */
	id = hpet_readl(HPET_ID);

#ifdef CONFIG_HPET_EMULATE_RTC
	/*
	 * The legacy routing mode needs at least two channels, tick timer
	 * and the rtc emulation channel.
	 */
	if (!(id & HPET_ID_NUMBER))
		goto out_nohpet;
#endif

	/* Start the counter */
	hpet_start_counter();

	if (id & HPET_ID_LEGSUP) {
		hpet_enable_int();
		hpet_reserve_platform_timers(id);
		/*
		 * Start hpet with the boot cpu mask and make it
		 * global after the IO_APIC has been initialized.
		 */
		hpet_clockevent.cpumask =cpumask_of_cpu(0);
		clockevents_register_device(&hpet_clockevent);
		global_clock_event = &hpet_clockevent;
		return 1;
	}
	return 0;

out_nohpet:
	iounmap(hpet_virt_address);
	hpet_virt_address = NULL;
	return 0;
}

/*
 * Clock source related code
 */
static cycle_t read_hpet(void)
{
	return (cycle_t)hpet_readl(HPET_COUNTER);
}

static struct clocksource clocksource_hpet = {
	.name		= "hpet",
	.rating		= 250,
	.read		= read_hpet,
	.mask		= HPET_MASK,
	.shift		= HPET_SHIFT,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init init_hpet_clocksource(void)
{
	u64 tmp;

	if (!hpet_virt_address)
		return -ENODEV;

	/*
	 * hpet period is in femto seconds per cycle
	 * so we need to convert this to ns/cyc units
	 * aproximated by mult/2^shift
	 *
	 *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	 *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	 *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	 *  (fsec/cyc << shift)/1000000 = mult
	 *  (hpet_period << shift)/FSEC_PER_NSEC = mult
	 */
	tmp = (u64)hpet_period << HPET_SHIFT;
	do_div(tmp, FSEC_PER_NSEC);
	clocksource_hpet.mult = (u32)tmp;

	return clocksource_register(&clocksource_hpet);
}

module_init(init_hpet_clocksource);

#ifdef CONFIG_HPET_EMULATE_RTC

/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 * is enabled, we support RTC interrupt functionality in software.
 * RTC has 3 kinds of interrupts:
 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 *    is updated
 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 * (1) and (2) above are implemented using polling at a frequency of
 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 * overhead. (DEFAULT_RTC_INT_FREQ)
 * For (3), we use interrupts at 64Hz or user specified periodic
 * frequency, whichever is higher.
 */
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>

#define DEFAULT_RTC_INT_FREQ	64
#define DEFAULT_RTC_SHIFT	6
#define RTC_NUM_INTS		1

static unsigned long hpet_rtc_flags;
static unsigned long hpet_prev_update_sec;
static struct rtc_time hpet_alarm_time;
static unsigned long hpet_pie_count;
static unsigned long hpet_t1_cmp;
static unsigned long hpet_default_delta;
static unsigned long hpet_pie_delta;
static unsigned long hpet_pie_limit;

/*
 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 * is not supported by all HPET implementations for timer 1.
 *
 * hpet_rtc_timer_init() is called when the rtc is initialized.
 */
int hpet_rtc_timer_init(void)
{
	unsigned long cfg, cnt, delta, flags;

	if (!is_hpet_enabled())
		return 0;

	if (!hpet_default_delta) {
		uint64_t clc;

		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
		hpet_default_delta = (unsigned long) clc;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	local_irq_save(flags);

	cnt = delta + hpet_readl(HPET_COUNTER);
	hpet_writel(cnt, HPET_T1_CMP);
	hpet_t1_cmp = cnt;

	cfg = hpet_readl(HPET_T1_CFG);
	cfg &= ~HPET_TN_PERIODIC;
	cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
	hpet_writel(cfg, HPET_T1_CFG);

	local_irq_restore(flags);

	return 1;
}

/*
 * The functions below are called from rtc driver.
 * Return 0 if HPET is not being used.
 * Otherwise do the necessary changes and return 1.
 */
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags &= ~bit_mask;
	return 1;
}

int hpet_set_rtc_irq_bit(unsigned long bit_mask)
{
	unsigned long oldbits = hpet_rtc_flags;

	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags |= bit_mask;

	if (!oldbits)
		hpet_rtc_timer_init();

	return 1;
}

int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
			unsigned char sec)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_alarm_time.tm_hour = hrs;
	hpet_alarm_time.tm_min = min;
	hpet_alarm_time.tm_sec = sec;

	return 1;
}

int hpet_set_periodic_freq(unsigned long freq)
{
	uint64_t clc;

	if (!is_hpet_enabled())
		return 0;

	if (freq <= DEFAULT_RTC_INT_FREQ)
		hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
	else {
		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		do_div(clc, freq);
		clc >>= hpet_clockevent.shift;
		hpet_pie_delta = (unsigned long) clc;
	}
	return 1;
}

int hpet_rtc_dropped_irq(void)
{
	return is_hpet_enabled();
}

static void hpet_rtc_timer_reinit(void)
{
	unsigned long cfg, delta;
	int lost_ints = -1;

	if (unlikely(!hpet_rtc_flags)) {
		cfg = hpet_readl(HPET_T1_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T1_CFG);
		return;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	/*
	 * Increment the comparator value until we are ahead of the
	 * current count.
	 */
	do {
		hpet_t1_cmp += delta;
		hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
		lost_ints++;
	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);

	if (lost_ints) {
		if (hpet_rtc_flags & RTC_PIE)
			hpet_pie_count += lost_ints;
		if (printk_ratelimit())
			printk(KERN_WARNING "rtc: lost %d interrupts\n",
				lost_ints);
	}
}

irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
{
	struct rtc_time curr_time;
	unsigned long rtc_int_flag = 0;

	hpet_rtc_timer_reinit();

	if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
		rtc_get_rtc_time(&curr_time);

	if (hpet_rtc_flags & RTC_UIE &&
	    curr_time.tm_sec != hpet_prev_update_sec) {
		rtc_int_flag = RTC_UF;
		hpet_prev_update_sec = curr_time.tm_sec;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    ++hpet_pie_count >= hpet_pie_limit) {
		rtc_int_flag |= RTC_PF;
		hpet_pie_count = 0;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	    (curr_time.tm_min == hpet_alarm_time.tm_min) &&
	    (curr_time.tm_hour == hpet_alarm_time.tm_hour))
			rtc_int_flag |= RTC_AF;

	if (rtc_int_flag) {
		rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
		rtc_interrupt(rtc_int_flag, dev_id);
	}
	return IRQ_HANDLED;
}
#endif
Commit	Line	Data
5d0cf410	1	#include <linux/clocksource.h>
e9e2cdb4	2	#include <linux/clockchips.h>
5d0cf410 JS	3	#include <linux/errno.h>
	4	#include <linux/hpet.h>
	5	#include <linux/init.h>
	6
	7	#include <asm/hpet.h>
	8	#include <asm/io.h>
	9
e9e2cdb4 TG	10	extern struct clock_event_device *global_clock_event;
e9e2cdb4 TG	11
7f9f303a	12	#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410 JS	13	#define HPET_SHIFT 22
	14
	15	/* FSEC = 10^-15 NSEC = 10^-9 */
	16	#define FSEC_PER_NSEC 1000000
	17
e9e2cdb4 TG	18	/*
	19	* HPET address is set in acpi/boot.c, when an ACPI entry exists
	20	*/
	21	unsigned long hpet_address;
	22	static void __iomem * hpet_virt_address;
	23
	24	static inline unsigned long hpet_readl(unsigned long a)
	25	{
	26	return readl(hpet_virt_address + a);
	27	}
	28
	29	static inline void hpet_writel(unsigned long d, unsigned long a)
	30	{
	31	writel(d, hpet_virt_address + a);
	32	}
	33
	34	/*
	35	* HPET command line enable / disable
	36	*/
	37	static int boot_hpet_disable;
	38
	39	static int __init hpet_setup(char* str)
	40	{
	41	if (str) {
	42	if (!strncmp("disable", str, 7))
	43	boot_hpet_disable = 1;
	44	}
	45	return 1;
	46	}
	47	__setup("hpet=", hpet_setup);
	48
	49	static inline int is_hpet_capable(void)
	50	{
	51	return (!boot_hpet_disable && hpet_address);
	52	}
	53
	54	/*
	55	* HPET timer interrupt enable / disable
	56	*/
	57	static int hpet_legacy_int_enabled;
	58
	59	/**
	60	* is_hpet_enabled - check whether the hpet timer interrupt is enabled
	61	*/
	62	int is_hpet_enabled(void)
	63	{
	64	return is_hpet_capable() && hpet_legacy_int_enabled;
	65	}
	66
	67	/*
	68	* When the hpet driver (/dev/hpet) is enabled, we need to reserve
	69	* timer 0 and timer 1 in case of RTC emulation.
	70	*/
	71	#ifdef CONFIG_HPET
	72	static void hpet_reserve_platform_timers(unsigned long id)
	73	{
	74	struct hpet __iomem *hpet = hpet_virt_address;
	75	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	76	unsigned int nrtimers, i;
	77	struct hpet_data hd;
	78
	79	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
	80
	81	memset(&hd, 0, sizeof (hd));
82	hd.hd_phys_address = hpet_address;
83	hd.hd_address = hpet_virt_address;
84	hd.hd_nirqs = nrtimers;
85	hd.hd_flags = HPET_DATA_PLATFORM;
86	hpet_reserve_timer(&hd, 0);
87
88	#ifdef CONFIG_HPET_EMULATE_RTC
89	hpet_reserve_timer(&hd, 1);
90	#endif
91
92	hd.hd_irq[0] = HPET_LEGACY_8254;
93	hd.hd_irq[1] = HPET_LEGACY_RTC;
94
95	for (i = 2; i < nrtimers; timer++, i++)
96	hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
97	Tn_INT_ROUTE_CNF_SHIFT;
98
99	hpet_alloc(&hd);
100
101	}
102	#else
103	static void hpet_reserve_platform_timers(unsigned long id) { }
104	#endif
105
106	/*
107	* Common hpet info
108	*/
109	static unsigned long hpet_period;
110
111	static void hpet_set_mode(enum clock_event_mode mode,
112	struct clock_event_device *evt);
113	static int hpet_next_event(unsigned long delta,
114	struct clock_event_device *evt);
115
116	/*
117	* The hpet clock event device
118	*/
119	static struct clock_event_device hpet_clockevent = {
120	.name = "hpet",
121	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
122	.set_mode = hpet_set_mode,
123	.set_next_event = hpet_next_event,
124	.shift = 32,
125	.irq = 0,
126	};
127
128	static void hpet_start_counter(void)
129	{
130	unsigned long cfg = hpet_readl(HPET_CFG);
131
132	cfg &= ~HPET_CFG_ENABLE;
133	hpet_writel(cfg, HPET_CFG);
134	hpet_writel(0, HPET_COUNTER);
135	hpet_writel(0, HPET_COUNTER + 4);
136	cfg \|= HPET_CFG_ENABLE;
137	hpet_writel(cfg, HPET_CFG);
138	}
139
140	static void hpet_enable_int(void)
141	{
142	unsigned long cfg = hpet_readl(HPET_CFG);
143
144	cfg \|= HPET_CFG_LEGACY;
145	hpet_writel(cfg, HPET_CFG);
146	hpet_legacy_int_enabled = 1;
147	}
148
149	static void hpet_set_mode(enum clock_event_mode mode,
150	struct clock_event_device *evt)
151	{
152	unsigned long cfg, cmp, now;
153	uint64_t delta;
154
155	switch(mode) {
156	case CLOCK_EVT_MODE_PERIODIC:
157	delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
158	delta >>= hpet_clockevent.shift;
159	now = hpet_readl(HPET_COUNTER);
160	cmp = now + (unsigned long) delta;
161	cfg = hpet_readl(HPET_T0_CFG);
162	cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
163	HPET_TN_SETVAL \| HPET_TN_32BIT;
164	hpet_writel(cfg, HPET_T0_CFG);
165	/*
166	* The first write after writing TN_SETVAL to the
167	* config register sets the counter value, the second
168	* write sets the period.
169	*/
170	hpet_writel(cmp, HPET_T0_CMP);
171	udelay(1);
172	hpet_writel((unsigned long) delta, HPET_T0_CMP);
173	break;
174
175	case CLOCK_EVT_MODE_ONESHOT:
176	cfg = hpet_readl(HPET_T0_CFG);
177	cfg &= ~HPET_TN_PERIODIC;
178	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
179	hpet_writel(cfg, HPET_T0_CFG);
180	break;
181
182	case CLOCK_EVT_MODE_UNUSED:
183	case CLOCK_EVT_MODE_SHUTDOWN:
184	cfg = hpet_readl(HPET_T0_CFG);
185	cfg &= ~HPET_TN_ENABLE;
186	hpet_writel(cfg, HPET_T0_CFG);
187	break;
188	}
189	}
190
191	static int hpet_next_event(unsigned long delta,
192	struct clock_event_device *evt)
193	{
194	unsigned long cnt;
195
196	cnt = hpet_readl(HPET_COUNTER);
197	cnt += delta;
198	hpet_writel(cnt, HPET_T0_CMP);
199
200	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0);
201	}
202
203	/*
204	* Try to setup the HPET timer
205	*/
206	int __init hpet_enable(void)
207	{
208	unsigned long id;
209	uint64_t hpet_freq;
210
211	if (!is_hpet_capable())
212	return 0;
213
214	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
215
216	/*
217	* Read the period and check for a sane value:
218	*/
219	hpet_period = hpet_readl(HPET_PERIOD);
220	if (hpet_period < HPET_MIN_PERIOD \|\| hpet_period > HPET_MAX_PERIOD)
221	goto out_nohpet;
222
223	/*
224	* The period is a femto seconds value. We need to calculate the
225	* scaled math multiplication factor for nanosecond to hpet tick
226	* conversion.
227	*/
228	hpet_freq = 1000000000000000ULL;
229	do_div(hpet_freq, hpet_period);
230	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
231	NSEC_PER_SEC, 32);
232	/* Calculate the min / max delta */
233	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
234	&hpet_clockevent);
235	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
236	&hpet_clockevent);
237
238	/*
239	* Read the HPET ID register to retrieve the IRQ routing
240	* information and the number of channels
241	*/
242	id = hpet_readl(HPET_ID);
243
244	#ifdef CONFIG_HPET_EMULATE_RTC
245	/*
246	* The legacy routing mode needs at least two channels, tick timer
247	* and the rtc emulation channel.
248	*/
249	if (!(id & HPET_ID_NUMBER))
250	goto out_nohpet;
251	#endif
252
253	/* Start the counter */
254	hpet_start_counter();
255
256	if (id & HPET_ID_LEGSUP) {
257	hpet_enable_int();
258	hpet_reserve_platform_timers(id);
259	/*
260	* Start hpet with the boot cpu mask and make it
261	* global after the IO_APIC has been initialized.
262	*/
263	hpet_clockevent.cpumask =cpumask_of_cpu(0);
264	clockevents_register_device(&hpet_clockevent);
265	global_clock_event = &hpet_clockevent;
266	return 1;
267	}
268	return 0;
5d0cf410	269
e9e2cdb4 TG	270	out_nohpet:
	271	iounmap(hpet_virt_address);
	272	hpet_virt_address = NULL;
	273	return 0;
	274	}
	275
	276	/*
	277	* Clock source related code
	278	*/
5d0cf410 JS	279	static cycle_t read_hpet(void)
5d0cf410 JS	280	{
e9e2cdb4	281	return (cycle_t)hpet_readl(HPET_COUNTER);
5d0cf410 JS	282	}
	283
	284	static struct clocksource clocksource_hpet = {
	285	.name = "hpet",
	286	.rating = 250,
	287	.read = read_hpet,
7f9f303a	288	.mask = HPET_MASK,
5d0cf410	289	.shift = HPET_SHIFT,
73b08d2a	290	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
5d0cf410 JS	291	};
	292
	293	static int __init init_hpet_clocksource(void)
	294	{
5d0cf410 JS	295	u64 tmp;
5d0cf410 JS	296
e9e2cdb4	297	if (!hpet_virt_address)
5d0cf410 JS	298	return -ENODEV;
5d0cf410 JS	299
5d0cf410 JS	300	/*
	301	* hpet period is in femto seconds per cycle
	302	* so we need to convert this to ns/cyc units
	303	* aproximated by mult/2^shift
	304	*
	305	* fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	306	* fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	307	* fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	308	* (fsec/cyc << shift)/1000000 = mult
	309	* (hpet_period << shift)/FSEC_PER_NSEC = mult
	310	*/
	311	tmp = (u64)hpet_period << HPET_SHIFT;
	312	do_div(tmp, FSEC_PER_NSEC);
	313	clocksource_hpet.mult = (u32)tmp;
	314
e9e2cdb4	315	return clocksource_register(&clocksource_hpet);
5d0cf410 JS	316	}
	317
	318	module_init(init_hpet_clocksource);
e9e2cdb4 TG	319
	320	#ifdef CONFIG_HPET_EMULATE_RTC
	321
	322	/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
	323	* is enabled, we support RTC interrupt functionality in software.
	324	* RTC has 3 kinds of interrupts:
	325	* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
	326	* is updated
	327	* 2) Alarm Interrupt - generate an interrupt at a specific time of day
	328	* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
	329	* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
	330	* (1) and (2) above are implemented using polling at a frequency of
	331	* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
	332	* overhead. (DEFAULT_RTC_INT_FREQ)
	333	* For (3), we use interrupts at 64Hz or user specified periodic
	334	* frequency, whichever is higher.
	335	*/
	336	#include <linux/mc146818rtc.h>
	337	#include <linux/rtc.h>
	338
	339	#define DEFAULT_RTC_INT_FREQ 64
	340	#define DEFAULT_RTC_SHIFT 6
	341	#define RTC_NUM_INTS 1
	342
	343	static unsigned long hpet_rtc_flags;
	344	static unsigned long hpet_prev_update_sec;
	345	static struct rtc_time hpet_alarm_time;
	346	static unsigned long hpet_pie_count;
	347	static unsigned long hpet_t1_cmp;
	348	static unsigned long hpet_default_delta;
	349	static unsigned long hpet_pie_delta;
	350	static unsigned long hpet_pie_limit;
	351
	352	/*
	353	* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
	354	* is not supported by all HPET implementations for timer 1.
	355	*
	356	* hpet_rtc_timer_init() is called when the rtc is initialized.
	357	*/
	358	int hpet_rtc_timer_init(void)
	359	{
	360	unsigned long cfg, cnt, delta, flags;
	361
	362	if (!is_hpet_enabled())
	363	return 0;
	364
	365	if (!hpet_default_delta) {
	366	uint64_t clc;
	367
	368	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
	369	clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
	370	hpet_default_delta = (unsigned long) clc;
	371	}
	372
	373	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
	374	delta = hpet_default_delta;
	375	else
	376	delta = hpet_pie_delta;
	377
	378	local_irq_save(flags);
	379
	380	cnt = delta + hpet_readl(HPET_COUNTER);
	381	hpet_writel(cnt, HPET_T1_CMP);
	382	hpet_t1_cmp = cnt;
383
384	cfg = hpet_readl(HPET_T1_CFG);
385	cfg &= ~HPET_TN_PERIODIC;
386	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
387	hpet_writel(cfg, HPET_T1_CFG);
388
389	local_irq_restore(flags);
390
391	return 1;
392	}
393
394	/*
395	* The functions below are called from rtc driver.
396	* Return 0 if HPET is not being used.
397	* Otherwise do the necessary changes and return 1.
398	*/
399	int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
400	{
401	if (!is_hpet_enabled())
402	return 0;
403
404	hpet_rtc_flags &= ~bit_mask;
405	return 1;
406	}
407
408	int hpet_set_rtc_irq_bit(unsigned long bit_mask)
409	{
410	unsigned long oldbits = hpet_rtc_flags;
411
412	if (!is_hpet_enabled())
413	return 0;
414
415	hpet_rtc_flags \|= bit_mask;
416
417	if (!oldbits)
418	hpet_rtc_timer_init();
419
420	return 1;
421	}
422
423	int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
424	unsigned char sec)
425	{
426	if (!is_hpet_enabled())
427	return 0;
428
429	hpet_alarm_time.tm_hour = hrs;
430	hpet_alarm_time.tm_min = min;
431	hpet_alarm_time.tm_sec = sec;
432
433	return 1;
434	}
435
436	int hpet_set_periodic_freq(unsigned long freq)
437	{
438	uint64_t clc;
439
440	if (!is_hpet_enabled())
441	return 0;
442
443	if (freq <= DEFAULT_RTC_INT_FREQ)
444	hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
445	else {
446	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
447	do_div(clc, freq);
448	clc >>= hpet_clockevent.shift;
449	hpet_pie_delta = (unsigned long) clc;
450	}
451	return 1;
452	}
453
454	int hpet_rtc_dropped_irq(void)
455	{
456	return is_hpet_enabled();
457	}
458
459	static void hpet_rtc_timer_reinit(void)
460	{
461	unsigned long cfg, delta;
462	int lost_ints = -1;
463
464	if (unlikely(!hpet_rtc_flags)) {
465	cfg = hpet_readl(HPET_T1_CFG);
466	cfg &= ~HPET_TN_ENABLE;
467	hpet_writel(cfg, HPET_T1_CFG);
468	return;
469	}
470
471	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
472	delta = hpet_default_delta;
473	else
474	delta = hpet_pie_delta;
475
476	/*
477	* Increment the comparator value until we are ahead of the
478	* current count.
479	*/
480	do {
481	hpet_t1_cmp += delta;
482	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
483	lost_ints++;
484	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
485
486	if (lost_ints) {
487	if (hpet_rtc_flags & RTC_PIE)
488	hpet_pie_count += lost_ints;
489	if (printk_ratelimit())
490	printk(KERN_WARNING "rtc: lost %d interrupts\n",
491	lost_ints);
492	}
493	}
494
495	irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
496	{
497	struct rtc_time curr_time;
498	unsigned long rtc_int_flag = 0;
499
500	hpet_rtc_timer_reinit();
501
502	if (hpet_rtc_flags & (RTC_UIE \| RTC_AIE))
503	rtc_get_rtc_time(&curr_time);
504
505	if (hpet_rtc_flags & RTC_UIE &&
506	curr_time.tm_sec != hpet_prev_update_sec) {
507	rtc_int_flag = RTC_UF;
508	hpet_prev_update_sec = curr_time.tm_sec;
509	}
510
511	if (hpet_rtc_flags & RTC_PIE &&
512	++hpet_pie_count >= hpet_pie_limit) {
513	rtc_int_flag \|= RTC_PF;
514	hpet_pie_count = 0;
515	}
516
517	if (hpet_rtc_flags & RTC_PIE &&
518	(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
519	(curr_time.tm_min == hpet_alarm_time.tm_min) &&
520	(curr_time.tm_hour == hpet_alarm_time.tm_hour))
521	rtc_int_flag \|= RTC_AF;
522
523	if (rtc_int_flag) {
524	rtc_int_flag \|= (RTC_IRQF \| (RTC_NUM_INTS << 8));
525	rtc_interrupt(rtc_int_flag, dev_id);
526	}
527	return IRQ_HANDLED;
528	}
529	#endif