[mirror_ubuntu-bionic-kernel.git] / arch / i386 / kernel / i8253.c

/*
 * i8253.c  8253/PIT functions
 *
 */
#include <linux/clockchips.h>
#include <linux/spinlock.h>
#include <linux/jiffies.h>
#include <linux/sysdev.h>
#include <linux/module.h>
#include <linux/init.h>

#include <asm/smp.h>
#include <asm/delay.h>
#include <asm/i8253.h>
#include <asm/io.h>

#include "io_ports.h"

DEFINE_SPINLOCK(i8253_lock);
EXPORT_SYMBOL(i8253_lock);

/*
 * HPET replaces the PIT, when enabled. So we need to know, which of
 * the two timers is used
 */
struct clock_event_device *global_clock_event;

/*
 * Initialize the PIT timer.
 *
 * This is also called after resume to bring the PIT into operation again.
 */
static void init_pit_timer(enum clock_event_mode mode,
			   struct clock_event_device *evt)
{
	unsigned long flags;

	spin_lock_irqsave(&i8253_lock, flags);

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* binary, mode 2, LSB/MSB, ch 0 */
		outb_p(0x34, PIT_MODE);
		udelay(10);
		outb_p(LATCH & 0xff , PIT_CH0);	/* LSB */
		udelay(10);
		outb(LATCH >> 8 , PIT_CH0);	/* MSB */
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		/* One shot setup */
		outb_p(0x38, PIT_MODE);
		udelay(10);
		break;
	}
	spin_unlock_irqrestore(&i8253_lock, flags);
}

/*
 * Program the next event in oneshot mode
 *
 * Delta is given in PIT ticks
 */
static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
{
	unsigned long flags;

	spin_lock_irqsave(&i8253_lock, flags);
	outb_p(delta & 0xff , PIT_CH0);	/* LSB */
	outb(delta >> 8 , PIT_CH0);	/* MSB */
	spin_unlock_irqrestore(&i8253_lock, flags);

	return 0;
}

/*
 * On UP the PIT can serve all of the possible timer functions. On SMP systems
 * it can be solely used for the global tick.
 *
 * The profiling and update capabilites are switched off once the local apic is
 * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
 * !using_apic_timer decisions in do_timer_interrupt_hook()
 */
struct clock_event_device pit_clockevent = {
	.name		= "pit",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= init_pit_timer,
	.set_next_event = pit_next_event,
	.shift		= 32,
	.irq		= 0,
};

/*
 * Initialize the conversion factor and the min/max deltas of the clock event
 * structure and register the clock event source with the framework.
 */
void __init setup_pit_timer(void)
{
	/*
	 * Start pit with the boot cpu mask and make it global after the
	 * IO_APIC has been initialized.
	 */
	pit_clockevent.cpumask = cpumask_of_cpu(0);
	pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
	pit_clockevent.max_delta_ns =
		clockevent_delta2ns(0x7FFF, &pit_clockevent);
	pit_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &pit_clockevent);
	clockevents_register_device(&pit_clockevent);
	global_clock_event = &pit_clockevent;
}

/*
 * Since the PIT overflows every tick, its not very useful
 * to just read by itself. So use jiffies to emulate a free
 * running counter:
 */
static cycle_t pit_read(void)
{
	unsigned long flags;
	int count;
	u32 jifs;
	static int old_count;
	static u32 old_jifs;

	spin_lock_irqsave(&i8253_lock, flags);
	/*
	 * Although our caller may have the read side of xtime_lock,
	 * this is now a seqlock, and we are cheating in this routine
	 * by having side effects on state that we cannot undo if
	 * there is a collision on the seqlock and our caller has to
	 * retry.  (Namely, old_jifs and old_count.)  So we must treat
	 * jiffies as volatile despite the lock.  We read jiffies
	 * before latching the timer count to guarantee that although
	 * the jiffies value might be older than the count (that is,
	 * the counter may underflow between the last point where
	 * jiffies was incremented and the point where we latch the
	 * count), it cannot be newer.
	 */
	jifs = jiffies;
	outb_p(0x00, PIT_MODE);	/* latch the count ASAP */
	count = inb_p(PIT_CH0);	/* read the latched count */
	count |= inb_p(PIT_CH0) << 8;

	/* VIA686a test code... reset the latch if count > max + 1 */
	if (count > LATCH) {
		outb_p(0x34, PIT_MODE);
		outb_p(LATCH & 0xff, PIT_CH0);
		outb(LATCH >> 8, PIT_CH0);
		count = LATCH - 1;
	}

	/*
	 * It's possible for count to appear to go the wrong way for a
	 * couple of reasons:
	 *
	 *  1. The timer counter underflows, but we haven't handled the
	 *     resulting interrupt and incremented jiffies yet.
	 *  2. Hardware problem with the timer, not giving us continuous time,
	 *     the counter does small "jumps" upwards on some Pentium systems,
	 *     (see c't 95/10 page 335 for Neptun bug.)
	 *
	 * Previous attempts to handle these cases intelligently were
	 * buggy, so we just do the simple thing now.
	 */
	if (count > old_count && jifs == old_jifs) {
		count = old_count;
	}
	old_count = count;
	old_jifs = jifs;

	spin_unlock_irqrestore(&i8253_lock, flags);

	count = (LATCH - 1) - count;

	return (cycle_t)(jifs * LATCH) + count;
}

static struct clocksource clocksource_pit = {
	.name	= "pit",
	.rating = 110,
	.read	= pit_read,
	.mask	= CLOCKSOURCE_MASK(32),
	.mult	= 0,
	.shift	= 20,
};

static int __init init_pit_clocksource(void)
{
	if (num_possible_cpus() > 1) /* PIT does not scale! */
		return 0;

	clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
	return clocksource_register(&clocksource_pit);
}
arch_initcall(init_pit_clocksource);
Commit	Line	Data
8d016ef1 JS	1	/*
	2	* i8253.c 8253/PIT functions
	3	*
	4	*/
e9e2cdb4	5	#include <linux/clockchips.h>
8d016ef1 JS	6	#include <linux/spinlock.h>
	7	#include <linux/jiffies.h>
	8	#include <linux/sysdev.h>
	9	#include <linux/module.h>
	10	#include <linux/init.h>
	11
	12	#include <asm/smp.h>
	13	#include <asm/delay.h>
	14	#include <asm/i8253.h>
	15	#include <asm/io.h>
	16
	17	#include "io_ports.h"
	18
	19	DEFINE_SPINLOCK(i8253_lock);
	20	EXPORT_SYMBOL(i8253_lock);
	21
e9e2cdb4 TG	22	/*
	23	* HPET replaces the PIT, when enabled. So we need to know, which of
	24	* the two timers is used
	25	*/
	26	struct clock_event_device *global_clock_event;
	27
	28	/*
	29	* Initialize the PIT timer.
	30	*
	31	* This is also called after resume to bring the PIT into operation again.
	32	*/
	33	static void init_pit_timer(enum clock_event_mode mode,
	34	struct clock_event_device *evt)
	35	{
	36	unsigned long flags;
	37
	38	spin_lock_irqsave(&i8253_lock, flags);
	39
	40	switch(mode) {
	41	case CLOCK_EVT_MODE_PERIODIC:
	42	/* binary, mode 2, LSB/MSB, ch 0 */
	43	outb_p(0x34, PIT_MODE);
	44	udelay(10);
	45	outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
	46	udelay(10);
	47	outb(LATCH >> 8 , PIT_CH0); /* MSB */
	48	break;
	49
	50	case CLOCK_EVT_MODE_ONESHOT:
	51	case CLOCK_EVT_MODE_SHUTDOWN:
	52	case CLOCK_EVT_MODE_UNUSED:
	53	/* One shot setup */
	54	outb_p(0x38, PIT_MODE);
	55	udelay(10);
	56	break;
	57	}
	58	spin_unlock_irqrestore(&i8253_lock, flags);
	59	}
	60
	61	/*
	62	* Program the next event in oneshot mode
	63	*
	64	* Delta is given in PIT ticks
	65	*/
	66	static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
8d016ef1 JS	67	{
	68	unsigned long flags;
	69
	70	spin_lock_irqsave(&i8253_lock, flags);
e9e2cdb4 TG	71	outb_p(delta & 0xff , PIT_CH0); /* LSB */
e9e2cdb4 TG	72	outb(delta >> 8 , PIT_CH0); /* MSB */
8d016ef1	73	spin_unlock_irqrestore(&i8253_lock, flags);
e9e2cdb4 TG	74
	75	return 0;
	76	}
	77
	78	/*
	79	* On UP the PIT can serve all of the possible timer functions. On SMP systems
	80	* it can be solely used for the global tick.
	81	*
	82	* The profiling and update capabilites are switched off once the local apic is
	83	* registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
	84	* !using_apic_timer decisions in do_timer_interrupt_hook()
	85	*/
	86	struct clock_event_device pit_clockevent = {
	87	.name = "pit",
	88	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	89	.set_mode = init_pit_timer,
	90	.set_next_event = pit_next_event,
	91	.shift = 32,
	92	.irq = 0,
	93	};
	94
	95	/*
	96	* Initialize the conversion factor and the min/max deltas of the clock event
	97	* structure and register the clock event source with the framework.
	98	*/
	99	void __init setup_pit_timer(void)
	100	{
	101	/*
	102	* Start pit with the boot cpu mask and make it global after the
	103	* IO_APIC has been initialized.
	104	*/
	105	pit_clockevent.cpumask = cpumask_of_cpu(0);
	106	pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
	107	pit_clockevent.max_delta_ns =
	108	clockevent_delta2ns(0x7FFF, &pit_clockevent);
	109	pit_clockevent.min_delta_ns =
	110	clockevent_delta2ns(0xF, &pit_clockevent);
	111	clockevents_register_device(&pit_clockevent);
	112	global_clock_event = &pit_clockevent;
8d016ef1	113	}
5d0cf410 JS	114
	115	/*
	116	* Since the PIT overflows every tick, its not very useful
	117	* to just read by itself. So use jiffies to emulate a free
	118	* running counter:
	119	*/
	120	static cycle_t pit_read(void)
	121	{
	122	unsigned long flags;
	123	int count;
6415ce9a JS	124	u32 jifs;
	125	static int old_count;
	126	static u32 old_jifs;
5d0cf410 JS	127
5d0cf410 JS	128	spin_lock_irqsave(&i8253_lock, flags);
e9e2cdb4	129	/*
6415ce9a JS	130	* Although our caller may have the read side of xtime_lock,
	131	* this is now a seqlock, and we are cheating in this routine
	132	* by having side effects on state that we cannot undo if
	133	* there is a collision on the seqlock and our caller has to
	134	* retry. (Namely, old_jifs and old_count.) So we must treat
	135	* jiffies as volatile despite the lock. We read jiffies
	136	* before latching the timer count to guarantee that although
	137	* the jiffies value might be older than the count (that is,
	138	* the counter may underflow between the last point where
	139	* jiffies was incremented and the point where we latch the
	140	* count), it cannot be newer.
	141	*/
	142	jifs = jiffies;
5d0cf410 JS	143	outb_p(0x00, PIT_MODE); /* latch the count ASAP */
	144	count = inb_p(PIT_CH0); /* read the latched count */
	145	count \|= inb_p(PIT_CH0) << 8;
	146
	147	/* VIA686a test code... reset the latch if count > max + 1 */
	148	if (count > LATCH) {
	149	outb_p(0x34, PIT_MODE);
	150	outb_p(LATCH & 0xff, PIT_CH0);
	151	outb(LATCH >> 8, PIT_CH0);
	152	count = LATCH - 1;
	153	}
5d0cf410	154
6415ce9a JS	155	/*
	156	* It's possible for count to appear to go the wrong way for a
	157	* couple of reasons:
	158	*
	159	* 1. The timer counter underflows, but we haven't handled the
	160	* resulting interrupt and incremented jiffies yet.
	161	* 2. Hardware problem with the timer, not giving us continuous time,
	162	* the counter does small "jumps" upwards on some Pentium systems,
	163	* (see c't 95/10 page 335 for Neptun bug.)
	164	*
	165	* Previous attempts to handle these cases intelligently were
	166	* buggy, so we just do the simple thing now.
	167	*/
	168	if (count > old_count && jifs == old_jifs) {
	169	count = old_count;
	170	}
	171	old_count = count;
	172	old_jifs = jifs;
	173
	174	spin_unlock_irqrestore(&i8253_lock, flags);
5d0cf410	175
6415ce9a	176	count = (LATCH - 1) - count;
5d0cf410 JS	177
	178	return (cycle_t)(jifs * LATCH) + count;
	179	}
	180
	181	static struct clocksource clocksource_pit = {
	182	.name = "pit",
	183	.rating = 110,
	184	.read = pit_read,
6415ce9a	185	.mask = CLOCKSOURCE_MASK(32),
5d0cf410 JS	186	.mult = 0,
	187	.shift = 20,
	188	};
	189
	190	static int __init init_pit_clocksource(void)
	191	{
3f4a0b91	192	if (num_possible_cpus() > 1) /* PIT does not scale! */
5d0cf410 JS	193	return 0;
	194
	195	clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
a2752549	196	return clocksource_register(&clocksource_pit);
5d0cf410	197	}
6bb74df4	198	arch_initcall(init_pit_clocksource);