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[PATCH] i386: Convert PDA into the percpu section
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CommitLineData
1da177e4
LT
1/*
2 * linux/arch/i386/kernel/irq.c
3 *
4 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
5 *
6 * This file contains the lowest level x86-specific interrupt
7 * entry, irq-stacks and irq statistics code. All the remaining
8 * irq logic is done by the generic kernel/irq/ code and
9 * by the x86-specific irq controller code. (e.g. i8259.c and
10 * io_apic.c.)
11 */
12
1da177e4
LT
13#include <linux/module.h>
14#include <linux/seq_file.h>
15#include <linux/interrupt.h>
16#include <linux/kernel_stat.h>
f3705136
ZM
17#include <linux/notifier.h>
18#include <linux/cpu.h>
19#include <linux/delay.h>
1da177e4 20
e05d723f
TG
21#include <asm/apic.h>
22#include <asm/uaccess.h>
23
22fc6ecc 24DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
1da177e4
LT
25EXPORT_PER_CPU_SYMBOL(irq_stat);
26
7c3576d2
JF
27DEFINE_PER_CPU(struct pt_regs *, irq_regs);
28EXPORT_PER_CPU_SYMBOL(irq_regs);
29
1da177e4
LT
30/*
31 * 'what should we do if we get a hw irq event on an illegal vector'.
32 * each architecture has to answer this themselves.
33 */
34void ack_bad_irq(unsigned int irq)
35{
e05d723f
TG
36 printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);
37
38#ifdef CONFIG_X86_LOCAL_APIC
39 /*
40 * Currently unexpected vectors happen only on SMP and APIC.
41 * We _must_ ack these because every local APIC has only N
42 * irq slots per priority level, and a 'hanging, unacked' IRQ
43 * holds up an irq slot - in excessive cases (when multiple
44 * unexpected vectors occur) that might lock up the APIC
45 * completely.
46 * But only ack when the APIC is enabled -AK
47 */
48 if (cpu_has_apic)
49 ack_APIC_irq();
1da177e4 50#endif
e05d723f 51}
1da177e4
LT
52
53#ifdef CONFIG_4KSTACKS
54/*
55 * per-CPU IRQ handling contexts (thread information and stack)
56 */
57union irq_ctx {
58 struct thread_info tinfo;
59 u32 stack[THREAD_SIZE/sizeof(u32)];
60};
61
22722051
AM
62static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
63static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
1da177e4
LT
64#endif
65
66/*
67 * do_IRQ handles all normal device IRQ's (the special
68 * SMP cross-CPU interrupts have their own specific
69 * handlers).
70 */
71fastcall unsigned int do_IRQ(struct pt_regs *regs)
72{
7d12e780 73 struct pt_regs *old_regs;
19eadf98
RR
74 /* high bit used in ret_from_ code */
75 int irq = ~regs->orig_eax;
f5b9ed7a 76 struct irq_desc *desc = irq_desc + irq;
1da177e4
LT
77#ifdef CONFIG_4KSTACKS
78 union irq_ctx *curctx, *irqctx;
79 u32 *isp;
80#endif
81
a052b68b
AM
82 if (unlikely((unsigned)irq >= NR_IRQS)) {
83 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
84 __FUNCTION__, irq);
85 BUG();
86 }
87
7d12e780 88 old_regs = set_irq_regs(regs);
1da177e4
LT
89 irq_enter();
90#ifdef CONFIG_DEBUG_STACKOVERFLOW
91 /* Debugging check for stack overflow: is there less than 1KB free? */
92 {
93 long esp;
94
95 __asm__ __volatile__("andl %%esp,%0" :
96 "=r" (esp) : "0" (THREAD_SIZE - 1));
97 if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
98 printk("do_IRQ: stack overflow: %ld\n",
99 esp - sizeof(struct thread_info));
100 dump_stack();
101 }
102 }
103#endif
104
105#ifdef CONFIG_4KSTACKS
106
107 curctx = (union irq_ctx *) current_thread_info();
108 irqctx = hardirq_ctx[smp_processor_id()];
109
110 /*
111 * this is where we switch to the IRQ stack. However, if we are
112 * already using the IRQ stack (because we interrupted a hardirq
113 * handler) we can't do that and just have to keep using the
114 * current stack (which is the irq stack already after all)
115 */
116 if (curctx != irqctx) {
7d12e780 117 int arg1, arg2, ebx;
1da177e4
LT
118
119 /* build the stack frame on the IRQ stack */
120 isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
121 irqctx->tinfo.task = curctx->tinfo.task;
122 irqctx->tinfo.previous_esp = current_stack_pointer;
123
a5d157e0
BS
124 /*
125 * Copy the softirq bits in preempt_count so that the
126 * softirq checks work in the hardirq context.
127 */
128 irqctx->tinfo.preempt_count =
91bf4602
AM
129 (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
130 (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
a5d157e0 131
1da177e4 132 asm volatile(
f5b9ed7a
IM
133 " xchgl %%ebx,%%esp \n"
134 " call *%%edi \n"
1da177e4 135 " movl %%ebx,%%esp \n"
7d12e780
DH
136 : "=a" (arg1), "=d" (arg2), "=b" (ebx)
137 : "0" (irq), "1" (desc), "2" (isp),
f5b9ed7a
IM
138 "D" (desc->handle_irq)
139 : "memory", "cc"
1da177e4
LT
140 );
141 } else
142#endif
7d12e780 143 desc->handle_irq(irq, desc);
1da177e4
LT
144
145 irq_exit();
7d12e780 146 set_irq_regs(old_regs);
1da177e4
LT
147 return 1;
148}
149
150#ifdef CONFIG_4KSTACKS
151
152/*
153 * These should really be __section__(".bss.page_aligned") as well, but
154 * gcc's 3.0 and earlier don't handle that correctly.
155 */
156static char softirq_stack[NR_CPUS * THREAD_SIZE]
157 __attribute__((__aligned__(THREAD_SIZE)));
158
159static char hardirq_stack[NR_CPUS * THREAD_SIZE]
160 __attribute__((__aligned__(THREAD_SIZE)));
161
162/*
163 * allocate per-cpu stacks for hardirq and for softirq processing
164 */
165void irq_ctx_init(int cpu)
166{
167 union irq_ctx *irqctx;
168
169 if (hardirq_ctx[cpu])
170 return;
171
172 irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
173 irqctx->tinfo.task = NULL;
174 irqctx->tinfo.exec_domain = NULL;
175 irqctx->tinfo.cpu = cpu;
176 irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
177 irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
178
179 hardirq_ctx[cpu] = irqctx;
180
181 irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
182 irqctx->tinfo.task = NULL;
183 irqctx->tinfo.exec_domain = NULL;
184 irqctx->tinfo.cpu = cpu;
55f327fa 185 irqctx->tinfo.preempt_count = 0;
1da177e4
LT
186 irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
187
188 softirq_ctx[cpu] = irqctx;
189
190 printk("CPU %u irqstacks, hard=%p soft=%p\n",
191 cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
192}
193
e1367daf
LS
194void irq_ctx_exit(int cpu)
195{
196 hardirq_ctx[cpu] = NULL;
197}
198
1da177e4
LT
199extern asmlinkage void __do_softirq(void);
200
201asmlinkage void do_softirq(void)
202{
203 unsigned long flags;
204 struct thread_info *curctx;
205 union irq_ctx *irqctx;
206 u32 *isp;
207
208 if (in_interrupt())
209 return;
210
211 local_irq_save(flags);
212
213 if (local_softirq_pending()) {
214 curctx = current_thread_info();
215 irqctx = softirq_ctx[smp_processor_id()];
216 irqctx->tinfo.task = curctx->task;
217 irqctx->tinfo.previous_esp = current_stack_pointer;
218
219 /* build the stack frame on the softirq stack */
220 isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
221
222 asm volatile(
223 " xchgl %%ebx,%%esp \n"
224 " call __do_softirq \n"
225 " movl %%ebx,%%esp \n"
226 : "=b"(isp)
227 : "0"(isp)
228 : "memory", "cc", "edx", "ecx", "eax"
229 );
55f327fa
IM
230 /*
231 * Shouldnt happen, we returned above if in_interrupt():
232 */
233 WARN_ON_ONCE(softirq_count());
1da177e4
LT
234 }
235
236 local_irq_restore(flags);
237}
238
239EXPORT_SYMBOL(do_softirq);
240#endif
241
242/*
243 * Interrupt statistics:
244 */
245
246atomic_t irq_err_count;
247
248/*
249 * /proc/interrupts printing:
250 */
251
252int show_interrupts(struct seq_file *p, void *v)
253{
254 int i = *(loff_t *) v, j;
255 struct irqaction * action;
256 unsigned long flags;
257
258 if (i == 0) {
259 seq_printf(p, " ");
9f40a72a 260 for_each_online_cpu(j)
bdbdaa79 261 seq_printf(p, "CPU%-8d",j);
1da177e4
LT
262 seq_putc(p, '\n');
263 }
264
265 if (i < NR_IRQS) {
266 spin_lock_irqsave(&irq_desc[i].lock, flags);
267 action = irq_desc[i].action;
268 if (!action)
269 goto skip;
270 seq_printf(p, "%3d: ",i);
271#ifndef CONFIG_SMP
272 seq_printf(p, "%10u ", kstat_irqs(i));
273#else
9f40a72a 274 for_each_online_cpu(j)
f3705136 275 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
1da177e4 276#endif
f5b9ed7a 277 seq_printf(p, " %8s", irq_desc[i].chip->name);
a460e745 278 seq_printf(p, "-%-8s", irq_desc[i].name);
1da177e4
LT
279 seq_printf(p, " %s", action->name);
280
281 for (action=action->next; action; action = action->next)
282 seq_printf(p, ", %s", action->name);
283
284 seq_putc(p, '\n');
285skip:
286 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
287 } else if (i == NR_IRQS) {
288 seq_printf(p, "NMI: ");
9f40a72a 289 for_each_online_cpu(j)
f3705136 290 seq_printf(p, "%10u ", nmi_count(j));
1da177e4
LT
291 seq_putc(p, '\n');
292#ifdef CONFIG_X86_LOCAL_APIC
293 seq_printf(p, "LOC: ");
9f40a72a 294 for_each_online_cpu(j)
f3705136
ZM
295 seq_printf(p, "%10u ",
296 per_cpu(irq_stat,j).apic_timer_irqs);
1da177e4
LT
297 seq_putc(p, '\n');
298#endif
299 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
300#if defined(CONFIG_X86_IO_APIC)
301 seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
302#endif
303 }
304 return 0;
305}
f3705136
ZM
306
307#ifdef CONFIG_HOTPLUG_CPU
308#include <mach_apic.h>
309
310void fixup_irqs(cpumask_t map)
311{
312 unsigned int irq;
313 static int warned;
314
315 for (irq = 0; irq < NR_IRQS; irq++) {
316 cpumask_t mask;
317 if (irq == 2)
318 continue;
319
a53da52f 320 cpus_and(mask, irq_desc[irq].affinity, map);
f3705136
ZM
321 if (any_online_cpu(mask) == NR_CPUS) {
322 printk("Breaking affinity for irq %i\n", irq);
323 mask = map;
324 }
d1bef4ed
IM
325 if (irq_desc[irq].chip->set_affinity)
326 irq_desc[irq].chip->set_affinity(irq, mask);
f3705136
ZM
327 else if (irq_desc[irq].action && !(warned++))
328 printk("Cannot set affinity for irq %i\n", irq);
329 }
330
331#if 0
332 barrier();
333 /* Ingo Molnar says: "after the IO-APIC masks have been redirected
334 [note the nop - the interrupt-enable boundary on x86 is two
335 instructions from sti] - to flush out pending hardirqs and
336 IPIs. After this point nothing is supposed to reach this CPU." */
337 __asm__ __volatile__("sti; nop; cli");
338 barrier();
339#else
340 /* That doesn't seem sufficient. Give it 1ms. */
341 local_irq_enable();
342 mdelay(1);
343 local_irq_disable();
344#endif
345}
346#endif
347