[mirror_ubuntu-artful-kernel.git] / arch / i386 / kernel / irq.c

/*
 *	linux/arch/i386/kernel/irq.c
 *
 *	Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
 *
 * This file contains the lowest level x86-specific interrupt
 * entry, irq-stacks and irq statistics code. All the remaining
 * irq logic is done by the generic kernel/irq/ code and
 * by the x86-specific irq controller code. (e.g. i8259.c and
 * io_apic.c.)
 */

#include <asm/uaccess.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/delay.h>

DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
EXPORT_PER_CPU_SYMBOL(irq_stat);

#ifndef CONFIG_X86_LOCAL_APIC
/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
}
#endif

#ifdef CONFIG_4KSTACKS
/*
 * per-CPU IRQ handling contexts (thread information and stack)
 */
union irq_ctx {
	struct thread_info      tinfo;
	u32                     stack[THREAD_SIZE/sizeof(u32)];
};

static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
#endif

/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
fastcall unsigned int do_IRQ(struct pt_regs *regs)
{	
	/* high bit used in ret_from_ code */
	int irq = ~regs->orig_eax;
#ifdef CONFIG_4KSTACKS
	union irq_ctx *curctx, *irqctx;
	u32 *isp;
#endif

	if (unlikely((unsigned)irq >= NR_IRQS)) {
		printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
					__FUNCTION__, irq);
		BUG();
	}

	irq_enter();
#ifdef CONFIG_DEBUG_STACKOVERFLOW
	/* Debugging check for stack overflow: is there less than 1KB free? */
	{
		long esp;

		__asm__ __volatile__("andl %%esp,%0" :
					"=r" (esp) : "0" (THREAD_SIZE - 1));
		if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
			printk("do_IRQ: stack overflow: %ld\n",
				esp - sizeof(struct thread_info));
			dump_stack();
		}
	}
#endif

#ifdef CONFIG_4KSTACKS

	curctx = (union irq_ctx *) current_thread_info();
	irqctx = hardirq_ctx[smp_processor_id()];

	/*
	 * this is where we switch to the IRQ stack. However, if we are
	 * already using the IRQ stack (because we interrupted a hardirq
	 * handler) we can't do that and just have to keep using the
	 * current stack (which is the irq stack already after all)
	 */
	if (curctx != irqctx) {
		int arg1, arg2, ebx;

		/* build the stack frame on the IRQ stack */
		isp = (u32*) ((char*)irqctx + sizeof(*irqctx));
		irqctx->tinfo.task = curctx->tinfo.task;
		irqctx->tinfo.previous_esp = current_stack_pointer;

		/*
		 * Copy the softirq bits in preempt_count so that the
		 * softirq checks work in the hardirq context.
		 */
		irqctx->tinfo.preempt_count =
			(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
			(curctx->tinfo.preempt_count & SOFTIRQ_MASK);

		asm volatile(
			"       xchgl   %%ebx,%%esp      \n"
			"       call    __do_IRQ         \n"
			"       movl   %%ebx,%%esp      \n"
			: "=a" (arg1), "=d" (arg2), "=b" (ebx)
			:  "0" (irq),   "1" (regs),  "2" (isp)
			: "memory", "cc", "ecx"
		);
	} else
#endif
		__do_IRQ(irq, regs);

	irq_exit();

	return 1;
}

#ifdef CONFIG_4KSTACKS

/*
 * These should really be __section__(".bss.page_aligned") as well, but
 * gcc's 3.0 and earlier don't handle that correctly.
 */
static char softirq_stack[NR_CPUS * THREAD_SIZE]
		__attribute__((__aligned__(THREAD_SIZE)));

static char hardirq_stack[NR_CPUS * THREAD_SIZE]
		__attribute__((__aligned__(THREAD_SIZE)));

/*
 * allocate per-cpu stacks for hardirq and for softirq processing
 */
void irq_ctx_init(int cpu)
{
	union irq_ctx *irqctx;

	if (hardirq_ctx[cpu])
		return;

	irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
	irqctx->tinfo.task              = NULL;
	irqctx->tinfo.exec_domain       = NULL;
	irqctx->tinfo.cpu               = cpu;
	irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
	irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);

	hardirq_ctx[cpu] = irqctx;

	irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
	irqctx->tinfo.task              = NULL;
	irqctx->tinfo.exec_domain       = NULL;
	irqctx->tinfo.cpu               = cpu;
	irqctx->tinfo.preempt_count     = 0;
	irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);

	softirq_ctx[cpu] = irqctx;

	printk("CPU %u irqstacks, hard=%p soft=%p\n",
		cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
}

void irq_ctx_exit(int cpu)
{
	hardirq_ctx[cpu] = NULL;
}

extern asmlinkage void __do_softirq(void);

asmlinkage void do_softirq(void)
{
	unsigned long flags;
	struct thread_info *curctx;
	union irq_ctx *irqctx;
	u32 *isp;

	if (in_interrupt())
		return;

	local_irq_save(flags);

	if (local_softirq_pending()) {
		curctx = current_thread_info();
		irqctx = softirq_ctx[smp_processor_id()];
		irqctx->tinfo.task = curctx->task;
		irqctx->tinfo.previous_esp = current_stack_pointer;

		/* build the stack frame on the softirq stack */
		isp = (u32*) ((char*)irqctx + sizeof(*irqctx));

		asm volatile(
			"       xchgl   %%ebx,%%esp     \n"
			"       call    __do_softirq    \n"
			"       movl    %%ebx,%%esp     \n"
			: "=b"(isp)
			: "0"(isp)
			: "memory", "cc", "edx", "ecx", "eax"
		);
		/*
		 * Shouldnt happen, we returned above if in_interrupt():
	 	 */
		WARN_ON_ONCE(softirq_count());
	}

	local_irq_restore(flags);
}

EXPORT_SYMBOL(do_softirq);
#endif

/*
 * Interrupt statistics:
 */

atomic_t irq_err_count;

/*
 * /proc/interrupts printing:
 */

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	struct irqaction * action;
	unsigned long flags;

	if (i == 0) {
		seq_printf(p, "           ");
		for_each_online_cpu(j)
			seq_printf(p, "CPU%-8d",j);
		seq_putc(p, '\n');
	}

	if (i < NR_IRQS) {
		spin_lock_irqsave(&irq_desc[i].lock, flags);
		action = irq_desc[i].action;
		if (!action)
			goto skip;
		seq_printf(p, "%3d: ",i);
#ifndef CONFIG_SMP
		seq_printf(p, "%10u ", kstat_irqs(i));
#else
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
#endif
		seq_printf(p, " %14s", irq_desc[i].chip->typename);
		seq_printf(p, "  %s", action->name);

		for (action=action->next; action; action = action->next)
			seq_printf(p, ", %s", action->name);

		seq_putc(p, '\n');
skip:
		spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	} else if (i == NR_IRQS) {
		seq_printf(p, "NMI: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", nmi_count(j));
		seq_putc(p, '\n');
#ifdef CONFIG_X86_LOCAL_APIC
		seq_printf(p, "LOC: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).apic_timer_irqs);
		seq_putc(p, '\n');
#endif
		seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
#if defined(CONFIG_X86_IO_APIC)
		seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
#endif
	}
	return 0;
}

#ifdef CONFIG_HOTPLUG_CPU
#include <mach_apic.h>

void fixup_irqs(cpumask_t map)
{
	unsigned int irq;
	static int warned;

	for (irq = 0; irq < NR_IRQS; irq++) {
		cpumask_t mask;
		if (irq == 2)
			continue;

		cpus_and(mask, irq_desc[irq].affinity, map);
		if (any_online_cpu(mask) == NR_CPUS) {
			printk("Breaking affinity for irq %i\n", irq);
			mask = map;
		}
		if (irq_desc[irq].chip->set_affinity)
			irq_desc[irq].chip->set_affinity(irq, mask);
		else if (irq_desc[irq].action && !(warned++))
			printk("Cannot set affinity for irq %i\n", irq);
	}

#if 0
	barrier();
	/* Ingo Molnar says: "after the IO-APIC masks have been redirected
	   [note the nop - the interrupt-enable boundary on x86 is two
	   instructions from sti] - to flush out pending hardirqs and
	   IPIs. After this point nothing is supposed to reach this CPU." */
	__asm__ __volatile__("sti; nop; cli");
	barrier();
#else
	/* That doesn't seem sufficient.  Give it 1ms. */
	local_irq_enable();
	mdelay(1);
	local_irq_disable();
#endif
}
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/i386/kernel/irq.c
	3	*
	4	* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
	5	*
	6	* This file contains the lowest level x86-specific interrupt
	7	* entry, irq-stacks and irq statistics code. All the remaining
	8	* irq logic is done by the generic kernel/irq/ code and
	9	* by the x86-specific irq controller code. (e.g. i8259.c and
	10	* io_apic.c.)
	11	*/
	12
	13	#include <asm/uaccess.h>
	14	#include <linux/module.h>
	15	#include <linux/seq_file.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/kernel_stat.h>
f3705136 ZM	18	#include <linux/notifier.h>
	19	#include <linux/cpu.h>
	20	#include <linux/delay.h>
1da177e4	21
22fc6ecc	22	DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
1da177e4 LT	23	EXPORT_PER_CPU_SYMBOL(irq_stat);
	24
	25	#ifndef CONFIG_X86_LOCAL_APIC
	26	/*
	27	* 'what should we do if we get a hw irq event on an illegal vector'.
	28	* each architecture has to answer this themselves.
	29	*/
	30	void ack_bad_irq(unsigned int irq)
	31	{
	32	printk("unexpected IRQ trap at vector %02x\n", irq);
	33	}
	34	#endif
	35
	36	#ifdef CONFIG_4KSTACKS
	37	/*
	38	* per-CPU IRQ handling contexts (thread information and stack)
	39	*/
	40	union irq_ctx {
	41	struct thread_info tinfo;
	42	u32 stack[THREAD_SIZE/sizeof(u32)];
	43	};
	44
22722051 AM	45	static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
22722051 AM	46	static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
1da177e4 LT	47	#endif
	48
	49	/*
	50	* do_IRQ handles all normal device IRQ's (the special
	51	* SMP cross-CPU interrupts have their own specific
	52	* handlers).
	53	*/
	54	fastcall unsigned int do_IRQ(struct pt_regs *regs)
	55	{
19eadf98 RR	56	/* high bit used in ret_from_ code */
19eadf98 RR	57	int irq = ~regs->orig_eax;
1da177e4 LT	58	#ifdef CONFIG_4KSTACKS
	59	union irq_ctx curctx, irqctx;
	60	u32 *isp;
	61	#endif
	62
a052b68b AM	63	if (unlikely((unsigned)irq >= NR_IRQS)) {
	64	printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
	65	__FUNCTION__, irq);
	66	BUG();
	67	}
	68
1da177e4 LT	69	irq_enter();
	70	#ifdef CONFIG_DEBUG_STACKOVERFLOW
	71	/* Debugging check for stack overflow: is there less than 1KB free? */
	72	{
	73	long esp;
	74
	75	__asm__ __volatile__("andl %%esp,%0" :
	76	"=r" (esp) : "0" (THREAD_SIZE - 1));
	77	if (unlikely(esp < (sizeof(struct thread_info) + STACK_WARN))) {
	78	printk("do_IRQ: stack overflow: %ld\n",
	79	esp - sizeof(struct thread_info));
	80	dump_stack();
	81	}
	82	}
	83	#endif
	84
	85	#ifdef CONFIG_4KSTACKS
	86
	87	curctx = (union irq_ctx *) current_thread_info();
	88	irqctx = hardirq_ctx[smp_processor_id()];
	89
	90	/*
	91	* this is where we switch to the IRQ stack. However, if we are
	92	* already using the IRQ stack (because we interrupted a hardirq
	93	* handler) we can't do that and just have to keep using the
	94	* current stack (which is the irq stack already after all)
	95	*/
	96	if (curctx != irqctx) {
	97	int arg1, arg2, ebx;
	98
	99	/* build the stack frame on the IRQ stack */
	100	isp = (u32) ((char)irqctx + sizeof(*irqctx));
	101	irqctx->tinfo.task = curctx->tinfo.task;
	102	irqctx->tinfo.previous_esp = current_stack_pointer;
	103
a5d157e0 BS	104	/*
	105	* Copy the softirq bits in preempt_count so that the
	106	* softirq checks work in the hardirq context.
	107	*/
	108	irqctx->tinfo.preempt_count =
91bf4602 AM	109	(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) \|
91bf4602 AM	110	(curctx->tinfo.preempt_count & SOFTIRQ_MASK);
a5d157e0	111
1da177e4 LT	112	asm volatile(
	113	" xchgl %%ebx,%%esp \n"
	114	" call __do_IRQ \n"
	115	" movl %%ebx,%%esp \n"
	116	: "=a" (arg1), "=d" (arg2), "=b" (ebx)
	117	: "0" (irq), "1" (regs), "2" (isp)
	118	: "memory", "cc", "ecx"
	119	);
	120	} else
	121	#endif
	122	__do_IRQ(irq, regs);
	123
	124	irq_exit();
	125
	126	return 1;
	127	}
	128
	129	#ifdef CONFIG_4KSTACKS
	130
	131	/*
	132	* These should really be __section__(".bss.page_aligned") as well, but
	133	* gcc's 3.0 and earlier don't handle that correctly.
	134	*/
	135	static char softirq_stack[NR_CPUS * THREAD_SIZE]
	136	__attribute__((__aligned__(THREAD_SIZE)));
	137
	138	static char hardirq_stack[NR_CPUS * THREAD_SIZE]
	139	__attribute__((__aligned__(THREAD_SIZE)));
	140
	141	/*
	142	* allocate per-cpu stacks for hardirq and for softirq processing
	143	*/
	144	void irq_ctx_init(int cpu)
	145	{
	146	union irq_ctx *irqctx;
	147
	148	if (hardirq_ctx[cpu])
	149	return;
	150
	151	irqctx = (union irq_ctx) &hardirq_stack[cpuTHREAD_SIZE];
	152	irqctx->tinfo.task = NULL;
	153	irqctx->tinfo.exec_domain = NULL;
	154	irqctx->tinfo.cpu = cpu;
	155	irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
	156	irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
	157
	158	hardirq_ctx[cpu] = irqctx;
	159
	160	irqctx = (union irq_ctx) &softirq_stack[cpuTHREAD_SIZE];
	161	irqctx->tinfo.task = NULL;
	162	irqctx->tinfo.exec_domain = NULL;
	163	irqctx->tinfo.cpu = cpu;
55f327fa	164	irqctx->tinfo.preempt_count = 0;
1da177e4 LT	165	irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
	166
	167	softirq_ctx[cpu] = irqctx;
	168
	169	printk("CPU %u irqstacks, hard=%p soft=%p\n",
	170	cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
	171	}
	172
e1367daf LS	173	void irq_ctx_exit(int cpu)
	174	{
	175	hardirq_ctx[cpu] = NULL;
	176	}
	177
1da177e4 LT	178	extern asmlinkage void __do_softirq(void);
	179
	180	asmlinkage void do_softirq(void)
	181	{
	182	unsigned long flags;
	183	struct thread_info *curctx;
	184	union irq_ctx *irqctx;
	185	u32 *isp;
	186
	187	if (in_interrupt())
	188	return;
	189
	190	local_irq_save(flags);
	191
	192	if (local_softirq_pending()) {
	193	curctx = current_thread_info();
	194	irqctx = softirq_ctx[smp_processor_id()];
	195	irqctx->tinfo.task = curctx->task;
	196	irqctx->tinfo.previous_esp = current_stack_pointer;
	197
	198	/* build the stack frame on the softirq stack */
	199	isp = (u32) ((char)irqctx + sizeof(*irqctx));
	200
	201	asm volatile(
	202	" xchgl %%ebx,%%esp \n"
	203	" call __do_softirq \n"
	204	" movl %%ebx,%%esp \n"
	205	: "=b"(isp)
	206	: "0"(isp)
	207	: "memory", "cc", "edx", "ecx", "eax"
	208	);
55f327fa IM	209	/*
	210	* Shouldnt happen, we returned above if in_interrupt():
	211	*/
	212	WARN_ON_ONCE(softirq_count());
1da177e4 LT	213	}
	214
	215	local_irq_restore(flags);
	216	}
	217
	218	EXPORT_SYMBOL(do_softirq);
	219	#endif
	220
	221	/*
	222	* Interrupt statistics:
	223	*/
	224
	225	atomic_t irq_err_count;
	226
	227	/*
	228	* /proc/interrupts printing:
	229	*/
	230
	231	int show_interrupts(struct seq_file p, void v)
	232	{
	233	int i = (loff_t ) v, j;
	234	struct irqaction * action;
	235	unsigned long flags;
	236
	237	if (i == 0) {
	238	seq_printf(p, " ");
9f40a72a	239	for_each_online_cpu(j)
bdbdaa79	240	seq_printf(p, "CPU%-8d",j);
1da177e4 LT	241	seq_putc(p, '\n');
	242	}
	243
	244	if (i < NR_IRQS) {
	245	spin_lock_irqsave(&irq_desc[i].lock, flags);
	246	action = irq_desc[i].action;
	247	if (!action)
	248	goto skip;
	249	seq_printf(p, "%3d: ",i);
	250	#ifndef CONFIG_SMP
	251	seq_printf(p, "%10u ", kstat_irqs(i));
	252	#else
9f40a72a	253	for_each_online_cpu(j)
f3705136	254	seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
1da177e4	255	#endif
d1bef4ed	256	seq_printf(p, " %14s", irq_desc[i].chip->typename);
1da177e4 LT	257	seq_printf(p, " %s", action->name);
	258
	259	for (action=action->next; action; action = action->next)
	260	seq_printf(p, ", %s", action->name);
	261
	262	seq_putc(p, '\n');
	263	skip:
	264	spin_unlock_irqrestore(&irq_desc[i].lock, flags);
	265	} else if (i == NR_IRQS) {
	266	seq_printf(p, "NMI: ");
9f40a72a	267	for_each_online_cpu(j)
f3705136	268	seq_printf(p, "%10u ", nmi_count(j));
1da177e4 LT	269	seq_putc(p, '\n');
	270	#ifdef CONFIG_X86_LOCAL_APIC
	271	seq_printf(p, "LOC: ");
9f40a72a	272	for_each_online_cpu(j)
f3705136 ZM	273	seq_printf(p, "%10u ",
f3705136 ZM	274	per_cpu(irq_stat,j).apic_timer_irqs);
1da177e4 LT	275	seq_putc(p, '\n');
	276	#endif
	277	seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
	278	#if defined(CONFIG_X86_IO_APIC)
	279	seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
	280	#endif
	281	}
	282	return 0;
	283	}
f3705136 ZM	284
	285	#ifdef CONFIG_HOTPLUG_CPU
	286	#include <mach_apic.h>
	287
	288	void fixup_irqs(cpumask_t map)
	289	{
	290	unsigned int irq;
	291	static int warned;
	292
	293	for (irq = 0; irq < NR_IRQS; irq++) {
	294	cpumask_t mask;
	295	if (irq == 2)
	296	continue;
	297
a53da52f	298	cpus_and(mask, irq_desc[irq].affinity, map);
f3705136 ZM	299	if (any_online_cpu(mask) == NR_CPUS) {
	300	printk("Breaking affinity for irq %i\n", irq);
	301	mask = map;
	302	}
d1bef4ed IM	303	if (irq_desc[irq].chip->set_affinity)
d1bef4ed IM	304	irq_desc[irq].chip->set_affinity(irq, mask);
f3705136 ZM	305	else if (irq_desc[irq].action && !(warned++))
	306	printk("Cannot set affinity for irq %i\n", irq);
	307	}
	308
	309	#if 0
	310	barrier();
	311	/* Ingo Molnar says: "after the IO-APIC masks have been redirected
	312	[note the nop - the interrupt-enable boundary on x86 is two
	313	instructions from sti] - to flush out pending hardirqs and
	314	IPIs. After this point nothing is supposed to reach this CPU." */
	315	__asm__ __volatile__("sti; nop; cli");
	316	barrier();
	317	#else
	318	/* That doesn't seem sufficient. Give it 1ms. */
	319	local_irq_enable();
	320	mdelay(1);
	321	local_irq_disable();
	322	#endif
	323	}
	324	#endif
	325