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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
d3561b7f RR |
36 | |
37 | /* SMP boot always wants to use real time delay to allow sufficient time for | |
38 | * the APs to come online */ | |
39 | #define USE_REAL_TIME_DELAY | |
40 | ||
1da177e4 | 41 | #include <linux/module.h> |
1da177e4 LT |
42 | #include <linux/init.h> |
43 | #include <linux/kernel.h> | |
44 | ||
45 | #include <linux/mm.h> | |
46 | #include <linux/sched.h> | |
47 | #include <linux/kernel_stat.h> | |
48 | #include <linux/smp_lock.h> | |
1da177e4 | 49 | #include <linux/bootmem.h> |
f3705136 ZM |
50 | #include <linux/notifier.h> |
51 | #include <linux/cpu.h> | |
52 | #include <linux/percpu.h> | |
1da177e4 LT |
53 | |
54 | #include <linux/delay.h> | |
55 | #include <linux/mc146818rtc.h> | |
56 | #include <asm/tlbflush.h> | |
57 | #include <asm/desc.h> | |
58 | #include <asm/arch_hooks.h> | |
3e4ff115 | 59 | #include <asm/nmi.h> |
62111195 | 60 | #include <asm/pda.h> |
1da177e4 LT |
61 | |
62 | #include <mach_apic.h> | |
63 | #include <mach_wakecpu.h> | |
64 | #include <smpboot_hooks.h> | |
65 | ||
66 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 67 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
68 | |
69 | /* Number of siblings per CPU package */ | |
70 | int smp_num_siblings = 1; | |
129f6946 AD |
71 | #ifdef CONFIG_X86_HT |
72 | EXPORT_SYMBOL(smp_num_siblings); | |
73 | #endif | |
d720803a | 74 | |
1e9f28fa SS |
75 | /* Last level cache ID of each logical CPU */ |
76 | int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
77 | ||
94605eff | 78 | /* representing HT siblings of each logical CPU */ |
6c036527 | 79 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
80 | EXPORT_SYMBOL(cpu_sibling_map); |
81 | ||
94605eff | 82 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 83 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
84 | EXPORT_SYMBOL(cpu_core_map); |
85 | ||
1da177e4 | 86 | /* bitmap of online cpus */ |
6c036527 | 87 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 88 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
89 | |
90 | cpumask_t cpu_callin_map; | |
91 | cpumask_t cpu_callout_map; | |
129f6946 | 92 | EXPORT_SYMBOL(cpu_callout_map); |
4ad8d383 ZM |
93 | cpumask_t cpu_possible_map; |
94 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
95 | static cpumask_t smp_commenced_mask; |
96 | ||
e1367daf LS |
97 | /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there |
98 | * is no way to resync one AP against BP. TBD: for prescott and above, we | |
99 | * should use IA64's algorithm | |
100 | */ | |
101 | static int __devinitdata tsc_sync_disabled; | |
102 | ||
1da177e4 LT |
103 | /* Per CPU bogomips and other parameters */ |
104 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 105 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 106 | |
6c036527 | 107 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
108 | { [0 ... NR_CPUS-1] = 0xff }; |
109 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
110 | ||
3b08606d | 111 | u8 apicid_2_node[MAX_APICID]; |
112 | ||
1da177e4 LT |
113 | /* |
114 | * Trampoline 80x86 program as an array. | |
115 | */ | |
116 | ||
117 | extern unsigned char trampoline_data []; | |
118 | extern unsigned char trampoline_end []; | |
119 | static unsigned char *trampoline_base; | |
120 | static int trampoline_exec; | |
121 | ||
122 | static void map_cpu_to_logical_apicid(void); | |
123 | ||
f3705136 ZM |
124 | /* State of each CPU. */ |
125 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
126 | ||
1da177e4 LT |
127 | /* |
128 | * Currently trivial. Write the real->protected mode | |
129 | * bootstrap into the page concerned. The caller | |
130 | * has made sure it's suitably aligned. | |
131 | */ | |
132 | ||
0bb3184d | 133 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
134 | { |
135 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
136 | return virt_to_phys(trampoline_base); | |
137 | } | |
138 | ||
139 | /* | |
140 | * We are called very early to get the low memory for the | |
141 | * SMP bootup trampoline page. | |
142 | */ | |
143 | void __init smp_alloc_memory(void) | |
144 | { | |
145 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
146 | /* | |
147 | * Has to be in very low memory so we can execute | |
148 | * real-mode AP code. | |
149 | */ | |
150 | if (__pa(trampoline_base) >= 0x9F000) | |
151 | BUG(); | |
152 | /* | |
153 | * Make the SMP trampoline executable: | |
154 | */ | |
155 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
156 | } | |
157 | ||
158 | /* | |
159 | * The bootstrap kernel entry code has set these up. Save them for | |
160 | * a given CPU | |
161 | */ | |
162 | ||
0bb3184d | 163 | static void __devinit smp_store_cpu_info(int id) |
1da177e4 LT |
164 | { |
165 | struct cpuinfo_x86 *c = cpu_data + id; | |
166 | ||
167 | *c = boot_cpu_data; | |
168 | if (id!=0) | |
169 | identify_cpu(c); | |
170 | /* | |
171 | * Mask B, Pentium, but not Pentium MMX | |
172 | */ | |
173 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
174 | c->x86 == 5 && | |
175 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
176 | c->x86_model <= 3) | |
177 | /* | |
178 | * Remember we have B step Pentia with bugs | |
179 | */ | |
180 | smp_b_stepping = 1; | |
181 | ||
182 | /* | |
183 | * Certain Athlons might work (for various values of 'work') in SMP | |
184 | * but they are not certified as MP capable. | |
185 | */ | |
186 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
187 | ||
3ca113ea DJ |
188 | if (num_possible_cpus() == 1) |
189 | goto valid_k7; | |
190 | ||
1da177e4 LT |
191 | /* Athlon 660/661 is valid. */ |
192 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
193 | goto valid_k7; | |
194 | ||
195 | /* Duron 670 is valid */ | |
196 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
197 | goto valid_k7; | |
198 | ||
199 | /* | |
200 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
201 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
202 | * have the MP bit set. | |
203 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
204 | */ | |
205 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
206 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
207 | (c->x86_model> 7)) | |
208 | if (cpu_has_mp) | |
209 | goto valid_k7; | |
210 | ||
211 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 212 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
213 | } |
214 | ||
215 | valid_k7: | |
216 | ; | |
217 | } | |
218 | ||
219 | /* | |
220 | * TSC synchronization. | |
221 | * | |
222 | * We first check whether all CPUs have their TSC's synchronized, | |
223 | * then we print a warning if not, and always resync. | |
224 | */ | |
225 | ||
c35a7261 AM |
226 | static struct { |
227 | atomic_t start_flag; | |
228 | atomic_t count_start; | |
229 | atomic_t count_stop; | |
230 | unsigned long long values[NR_CPUS]; | |
231 | } tsc __initdata = { | |
232 | .start_flag = ATOMIC_INIT(0), | |
233 | .count_start = ATOMIC_INIT(0), | |
234 | .count_stop = ATOMIC_INIT(0), | |
235 | }; | |
1da177e4 LT |
236 | |
237 | #define NR_LOOPS 5 | |
238 | ||
c35a7261 | 239 | static void __init synchronize_tsc_bp(void) |
1da177e4 LT |
240 | { |
241 | int i; | |
242 | unsigned long long t0; | |
243 | unsigned long long sum, avg; | |
244 | long long delta; | |
a3a255e7 | 245 | unsigned int one_usec; |
1da177e4 LT |
246 | int buggy = 0; |
247 | ||
248 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
249 | ||
250 | /* convert from kcyc/sec to cyc/usec */ | |
251 | one_usec = cpu_khz / 1000; | |
252 | ||
c35a7261 | 253 | atomic_set(&tsc.start_flag, 1); |
1da177e4 LT |
254 | wmb(); |
255 | ||
256 | /* | |
257 | * We loop a few times to get a primed instruction cache, | |
258 | * then the last pass is more or less synchronized and | |
259 | * the BP and APs set their cycle counters to zero all at | |
260 | * once. This reduces the chance of having random offsets | |
261 | * between the processors, and guarantees that the maximum | |
262 | * delay between the cycle counters is never bigger than | |
263 | * the latency of information-passing (cachelines) between | |
264 | * two CPUs. | |
265 | */ | |
266 | for (i = 0; i < NR_LOOPS; i++) { | |
267 | /* | |
268 | * all APs synchronize but they loop on '== num_cpus' | |
269 | */ | |
c35a7261 | 270 | while (atomic_read(&tsc.count_start) != num_booting_cpus()-1) |
18698917 | 271 | cpu_relax(); |
c35a7261 | 272 | atomic_set(&tsc.count_stop, 0); |
1da177e4 LT |
273 | wmb(); |
274 | /* | |
275 | * this lets the APs save their current TSC: | |
276 | */ | |
c35a7261 | 277 | atomic_inc(&tsc.count_start); |
1da177e4 | 278 | |
c35a7261 | 279 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
280 | /* |
281 | * We clear the TSC in the last loop: | |
282 | */ | |
283 | if (i == NR_LOOPS-1) | |
284 | write_tsc(0, 0); | |
285 | ||
286 | /* | |
287 | * Wait for all APs to leave the synchronization point: | |
288 | */ | |
c35a7261 | 289 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1) |
18698917 | 290 | cpu_relax(); |
c35a7261 | 291 | atomic_set(&tsc.count_start, 0); |
1da177e4 | 292 | wmb(); |
c35a7261 | 293 | atomic_inc(&tsc.count_stop); |
1da177e4 LT |
294 | } |
295 | ||
296 | sum = 0; | |
297 | for (i = 0; i < NR_CPUS; i++) { | |
298 | if (cpu_isset(i, cpu_callout_map)) { | |
c35a7261 | 299 | t0 = tsc.values[i]; |
1da177e4 LT |
300 | sum += t0; |
301 | } | |
302 | } | |
303 | avg = sum; | |
304 | do_div(avg, num_booting_cpus()); | |
305 | ||
1da177e4 LT |
306 | for (i = 0; i < NR_CPUS; i++) { |
307 | if (!cpu_isset(i, cpu_callout_map)) | |
308 | continue; | |
c35a7261 | 309 | delta = tsc.values[i] - avg; |
1da177e4 LT |
310 | if (delta < 0) |
311 | delta = -delta; | |
312 | /* | |
313 | * We report bigger than 2 microseconds clock differences. | |
314 | */ | |
315 | if (delta > 2*one_usec) { | |
c35a7261 AM |
316 | long long realdelta; |
317 | ||
1da177e4 LT |
318 | if (!buggy) { |
319 | buggy = 1; | |
320 | printk("\n"); | |
321 | } | |
322 | realdelta = delta; | |
323 | do_div(realdelta, one_usec); | |
c35a7261 | 324 | if (tsc.values[i] < avg) |
1da177e4 LT |
325 | realdelta = -realdelta; |
326 | ||
c35a7261 AM |
327 | if (realdelta) |
328 | printk(KERN_INFO "CPU#%d had %Ld usecs TSC " | |
7f5910ec | 329 | "skew, fixed it up.\n", i, realdelta); |
1da177e4 | 330 | } |
1da177e4 LT |
331 | } |
332 | if (!buggy) | |
333 | printk("passed.\n"); | |
334 | } | |
335 | ||
c35a7261 | 336 | static void __init synchronize_tsc_ap(void) |
1da177e4 LT |
337 | { |
338 | int i; | |
339 | ||
340 | /* | |
341 | * Not every cpu is online at the time | |
342 | * this gets called, so we first wait for the BP to | |
343 | * finish SMP initialization: | |
344 | */ | |
c35a7261 | 345 | while (!atomic_read(&tsc.start_flag)) |
18698917 | 346 | cpu_relax(); |
1da177e4 LT |
347 | |
348 | for (i = 0; i < NR_LOOPS; i++) { | |
c35a7261 AM |
349 | atomic_inc(&tsc.count_start); |
350 | while (atomic_read(&tsc.count_start) != num_booting_cpus()) | |
18698917 | 351 | cpu_relax(); |
1da177e4 | 352 | |
c35a7261 | 353 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
354 | if (i == NR_LOOPS-1) |
355 | write_tsc(0, 0); | |
356 | ||
c35a7261 AM |
357 | atomic_inc(&tsc.count_stop); |
358 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()) | |
18698917 | 359 | cpu_relax(); |
1da177e4 LT |
360 | } |
361 | } | |
362 | #undef NR_LOOPS | |
363 | ||
364 | extern void calibrate_delay(void); | |
365 | ||
366 | static atomic_t init_deasserted; | |
367 | ||
0bb3184d | 368 | static void __devinit smp_callin(void) |
1da177e4 LT |
369 | { |
370 | int cpuid, phys_id; | |
371 | unsigned long timeout; | |
372 | ||
373 | /* | |
374 | * If waken up by an INIT in an 82489DX configuration | |
375 | * we may get here before an INIT-deassert IPI reaches | |
376 | * our local APIC. We have to wait for the IPI or we'll | |
377 | * lock up on an APIC access. | |
378 | */ | |
379 | wait_for_init_deassert(&init_deasserted); | |
380 | ||
381 | /* | |
382 | * (This works even if the APIC is not enabled.) | |
383 | */ | |
384 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
385 | cpuid = smp_processor_id(); | |
386 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
387 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
388 | phys_id, cpuid); | |
389 | BUG(); | |
390 | } | |
391 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
392 | ||
393 | /* | |
394 | * STARTUP IPIs are fragile beasts as they might sometimes | |
395 | * trigger some glue motherboard logic. Complete APIC bus | |
396 | * silence for 1 second, this overestimates the time the | |
397 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
398 | * by a factor of two. This should be enough. | |
399 | */ | |
400 | ||
401 | /* | |
402 | * Waiting 2s total for startup (udelay is not yet working) | |
403 | */ | |
404 | timeout = jiffies + 2*HZ; | |
405 | while (time_before(jiffies, timeout)) { | |
406 | /* | |
407 | * Has the boot CPU finished it's STARTUP sequence? | |
408 | */ | |
409 | if (cpu_isset(cpuid, cpu_callout_map)) | |
410 | break; | |
411 | rep_nop(); | |
412 | } | |
413 | ||
414 | if (!time_before(jiffies, timeout)) { | |
415 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
416 | cpuid); | |
417 | BUG(); | |
418 | } | |
419 | ||
420 | /* | |
421 | * the boot CPU has finished the init stage and is spinning | |
422 | * on callin_map until we finish. We are free to set up this | |
423 | * CPU, first the APIC. (this is probably redundant on most | |
424 | * boards) | |
425 | */ | |
426 | ||
427 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
428 | smp_callin_clear_local_apic(); | |
429 | setup_local_APIC(); | |
430 | map_cpu_to_logical_apicid(); | |
431 | ||
432 | /* | |
433 | * Get our bogomips. | |
434 | */ | |
435 | calibrate_delay(); | |
436 | Dprintk("Stack at about %p\n",&cpuid); | |
437 | ||
438 | /* | |
439 | * Save our processor parameters | |
440 | */ | |
441 | smp_store_cpu_info(cpuid); | |
442 | ||
443 | disable_APIC_timer(); | |
444 | ||
445 | /* | |
446 | * Allow the master to continue. | |
447 | */ | |
448 | cpu_set(cpuid, cpu_callin_map); | |
449 | ||
450 | /* | |
451 | * Synchronize the TSC with the BP | |
452 | */ | |
e1367daf | 453 | if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) |
1da177e4 LT |
454 | synchronize_tsc_ap(); |
455 | } | |
456 | ||
457 | static int cpucount; | |
458 | ||
1e9f28fa SS |
459 | /* maps the cpu to the sched domain representing multi-core */ |
460 | cpumask_t cpu_coregroup_map(int cpu) | |
461 | { | |
462 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
463 | /* | |
464 | * For perf, we return last level cache shared map. | |
5c45bf27 | 465 | * And for power savings, we return cpu_core_map |
1e9f28fa | 466 | */ |
5c45bf27 SS |
467 | if (sched_mc_power_savings || sched_smt_power_savings) |
468 | return cpu_core_map[cpu]; | |
469 | else | |
470 | return c->llc_shared_map; | |
1e9f28fa SS |
471 | } |
472 | ||
94605eff SS |
473 | /* representing cpus for which sibling maps can be computed */ |
474 | static cpumask_t cpu_sibling_setup_map; | |
475 | ||
d720803a LS |
476 | static inline void |
477 | set_cpu_sibling_map(int cpu) | |
478 | { | |
479 | int i; | |
94605eff SS |
480 | struct cpuinfo_x86 *c = cpu_data; |
481 | ||
482 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
483 | |
484 | if (smp_num_siblings > 1) { | |
94605eff | 485 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
4b89aff9 RS |
486 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
487 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
d720803a LS |
488 | cpu_set(i, cpu_sibling_map[cpu]); |
489 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
490 | cpu_set(i, cpu_core_map[cpu]); |
491 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
492 | cpu_set(i, c[cpu].llc_shared_map); |
493 | cpu_set(cpu, c[i].llc_shared_map); | |
d720803a LS |
494 | } |
495 | } | |
496 | } else { | |
497 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
498 | } | |
499 | ||
1e9f28fa SS |
500 | cpu_set(cpu, c[cpu].llc_shared_map); |
501 | ||
94605eff | 502 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 503 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
504 | c[cpu].booted_cores = 1; |
505 | return; | |
506 | } | |
507 | ||
508 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
509 | if (cpu_llc_id[cpu] != BAD_APICID && |
510 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
511 | cpu_set(i, c[cpu].llc_shared_map); | |
512 | cpu_set(cpu, c[i].llc_shared_map); | |
513 | } | |
4b89aff9 | 514 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
515 | cpu_set(i, cpu_core_map[cpu]); |
516 | cpu_set(cpu, cpu_core_map[i]); | |
517 | /* | |
518 | * Does this new cpu bringup a new core? | |
519 | */ | |
520 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
521 | /* | |
522 | * for each core in package, increment | |
523 | * the booted_cores for this new cpu | |
524 | */ | |
525 | if (first_cpu(cpu_sibling_map[i]) == i) | |
526 | c[cpu].booted_cores++; | |
527 | /* | |
528 | * increment the core count for all | |
529 | * the other cpus in this package | |
530 | */ | |
531 | if (i != cpu) | |
532 | c[i].booted_cores++; | |
533 | } else if (i != cpu && !c[cpu].booted_cores) | |
534 | c[cpu].booted_cores = c[i].booted_cores; | |
535 | } | |
d720803a LS |
536 | } |
537 | } | |
538 | ||
1da177e4 LT |
539 | /* |
540 | * Activate a secondary processor. | |
541 | */ | |
0bb3184d | 542 | static void __devinit start_secondary(void *unused) |
1da177e4 LT |
543 | { |
544 | /* | |
62111195 | 545 | * Don't put *anything* before secondary_cpu_init(), SMP |
1da177e4 LT |
546 | * booting is too fragile that we want to limit the |
547 | * things done here to the most necessary things. | |
548 | */ | |
62111195 | 549 | secondary_cpu_init(); |
5bfb5d69 | 550 | preempt_disable(); |
1da177e4 LT |
551 | smp_callin(); |
552 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
553 | rep_nop(); | |
554 | setup_secondary_APIC_clock(); | |
555 | if (nmi_watchdog == NMI_IO_APIC) { | |
556 | disable_8259A_irq(0); | |
557 | enable_NMI_through_LVT0(NULL); | |
558 | enable_8259A_irq(0); | |
559 | } | |
560 | enable_APIC_timer(); | |
561 | /* | |
562 | * low-memory mappings have been cleared, flush them from | |
563 | * the local TLBs too. | |
564 | */ | |
565 | local_flush_tlb(); | |
6fe940d6 | 566 | |
d720803a LS |
567 | /* This must be done before setting cpu_online_map */ |
568 | set_cpu_sibling_map(raw_smp_processor_id()); | |
569 | wmb(); | |
570 | ||
6fe940d6 LS |
571 | /* |
572 | * We need to hold call_lock, so there is no inconsistency | |
573 | * between the time smp_call_function() determines number of | |
574 | * IPI receipients, and the time when the determination is made | |
575 | * for which cpus receive the IPI. Holding this | |
576 | * lock helps us to not include this cpu in a currently in progress | |
577 | * smp_call_function(). | |
578 | */ | |
579 | lock_ipi_call_lock(); | |
1da177e4 | 580 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 581 | unlock_ipi_call_lock(); |
e1367daf | 582 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
583 | |
584 | /* We can take interrupts now: we're officially "up". */ | |
585 | local_irq_enable(); | |
586 | ||
587 | wmb(); | |
588 | cpu_idle(); | |
589 | } | |
590 | ||
591 | /* | |
592 | * Everything has been set up for the secondary | |
593 | * CPUs - they just need to reload everything | |
594 | * from the task structure | |
595 | * This function must not return. | |
596 | */ | |
0bb3184d | 597 | void __devinit initialize_secondary(void) |
1da177e4 LT |
598 | { |
599 | /* | |
600 | * We don't actually need to load the full TSS, | |
601 | * basically just the stack pointer and the eip. | |
602 | */ | |
603 | ||
604 | asm volatile( | |
605 | "movl %0,%%esp\n\t" | |
606 | "jmp *%1" | |
607 | : | |
62111195 | 608 | :"m" (current->thread.esp),"m" (current->thread.eip)); |
1da177e4 LT |
609 | } |
610 | ||
62111195 | 611 | /* Static state in head.S used to set up a CPU */ |
1da177e4 LT |
612 | extern struct { |
613 | void * esp; | |
614 | unsigned short ss; | |
615 | } stack_start; | |
62111195 JF |
616 | extern struct i386_pda *start_pda; |
617 | extern struct Xgt_desc_struct cpu_gdt_descr; | |
1da177e4 LT |
618 | |
619 | #ifdef CONFIG_NUMA | |
620 | ||
621 | /* which logical CPUs are on which nodes */ | |
6c036527 | 622 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 | 623 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
a406c366 | 624 | EXPORT_SYMBOL(node_2_cpu_mask); |
1da177e4 | 625 | /* which node each logical CPU is on */ |
6c036527 | 626 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
627 | EXPORT_SYMBOL(cpu_2_node); |
628 | ||
629 | /* set up a mapping between cpu and node. */ | |
630 | static inline void map_cpu_to_node(int cpu, int node) | |
631 | { | |
632 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
633 | cpu_set(cpu, node_2_cpu_mask[node]); | |
634 | cpu_2_node[cpu] = node; | |
635 | } | |
636 | ||
637 | /* undo a mapping between cpu and node. */ | |
638 | static inline void unmap_cpu_to_node(int cpu) | |
639 | { | |
640 | int node; | |
641 | ||
642 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
643 | for (node = 0; node < MAX_NUMNODES; node ++) | |
644 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
645 | cpu_2_node[cpu] = 0; | |
646 | } | |
647 | #else /* !CONFIG_NUMA */ | |
648 | ||
649 | #define map_cpu_to_node(cpu, node) ({}) | |
650 | #define unmap_cpu_to_node(cpu) ({}) | |
651 | ||
652 | #endif /* CONFIG_NUMA */ | |
653 | ||
6c036527 | 654 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
655 | |
656 | static void map_cpu_to_logical_apicid(void) | |
657 | { | |
658 | int cpu = smp_processor_id(); | |
659 | int apicid = logical_smp_processor_id(); | |
78b656b8 | 660 | int node = apicid_to_node(apicid); |
bfa0e9a0 | 661 | |
662 | if (!node_online(node)) | |
663 | node = first_online_node; | |
1da177e4 LT |
664 | |
665 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 666 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
667 | } |
668 | ||
669 | static void unmap_cpu_to_logical_apicid(int cpu) | |
670 | { | |
671 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
672 | unmap_cpu_to_node(cpu); | |
673 | } | |
674 | ||
675 | #if APIC_DEBUG | |
676 | static inline void __inquire_remote_apic(int apicid) | |
677 | { | |
678 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
679 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
680 | int timeout, status; | |
681 | ||
682 | printk("Inquiring remote APIC #%d...\n", apicid); | |
683 | ||
38e548ee | 684 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
685 | printk("... APIC #%d %s: ", apicid, names[i]); |
686 | ||
687 | /* | |
688 | * Wait for idle. | |
689 | */ | |
690 | apic_wait_icr_idle(); | |
691 | ||
692 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
693 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
694 | ||
695 | timeout = 0; | |
696 | do { | |
697 | udelay(100); | |
698 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
699 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
700 | ||
701 | switch (status) { | |
702 | case APIC_ICR_RR_VALID: | |
703 | status = apic_read(APIC_RRR); | |
704 | printk("%08x\n", status); | |
705 | break; | |
706 | default: | |
707 | printk("failed\n"); | |
708 | } | |
709 | } | |
710 | } | |
711 | #endif | |
712 | ||
713 | #ifdef WAKE_SECONDARY_VIA_NMI | |
714 | /* | |
715 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
716 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
717 | * won't ... remember to clear down the APIC, etc later. | |
718 | */ | |
0bb3184d | 719 | static int __devinit |
1da177e4 LT |
720 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
721 | { | |
722 | unsigned long send_status = 0, accept_status = 0; | |
723 | int timeout, maxlvt; | |
724 | ||
725 | /* Target chip */ | |
726 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
727 | ||
728 | /* Boot on the stack */ | |
729 | /* Kick the second */ | |
730 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
731 | ||
732 | Dprintk("Waiting for send to finish...\n"); | |
733 | timeout = 0; | |
734 | do { | |
735 | Dprintk("+"); | |
736 | udelay(100); | |
737 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
738 | } while (send_status && (timeout++ < 1000)); | |
739 | ||
740 | /* | |
741 | * Give the other CPU some time to accept the IPI. | |
742 | */ | |
743 | udelay(200); | |
744 | /* | |
745 | * Due to the Pentium erratum 3AP. | |
746 | */ | |
747 | maxlvt = get_maxlvt(); | |
748 | if (maxlvt > 3) { | |
749 | apic_read_around(APIC_SPIV); | |
750 | apic_write(APIC_ESR, 0); | |
751 | } | |
752 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
753 | Dprintk("NMI sent.\n"); | |
754 | ||
755 | if (send_status) | |
756 | printk("APIC never delivered???\n"); | |
757 | if (accept_status) | |
758 | printk("APIC delivery error (%lx).\n", accept_status); | |
759 | ||
760 | return (send_status | accept_status); | |
761 | } | |
762 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
763 | ||
764 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 765 | static int __devinit |
1da177e4 LT |
766 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
767 | { | |
768 | unsigned long send_status = 0, accept_status = 0; | |
769 | int maxlvt, timeout, num_starts, j; | |
770 | ||
771 | /* | |
772 | * Be paranoid about clearing APIC errors. | |
773 | */ | |
774 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
775 | apic_read_around(APIC_SPIV); | |
776 | apic_write(APIC_ESR, 0); | |
777 | apic_read(APIC_ESR); | |
778 | } | |
779 | ||
780 | Dprintk("Asserting INIT.\n"); | |
781 | ||
782 | /* | |
783 | * Turn INIT on target chip | |
784 | */ | |
785 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
786 | ||
787 | /* | |
788 | * Send IPI | |
789 | */ | |
790 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
791 | | APIC_DM_INIT); | |
792 | ||
793 | Dprintk("Waiting for send to finish...\n"); | |
794 | timeout = 0; | |
795 | do { | |
796 | Dprintk("+"); | |
797 | udelay(100); | |
798 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
799 | } while (send_status && (timeout++ < 1000)); | |
800 | ||
801 | mdelay(10); | |
802 | ||
803 | Dprintk("Deasserting INIT.\n"); | |
804 | ||
805 | /* Target chip */ | |
806 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
807 | ||
808 | /* Send IPI */ | |
809 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
810 | ||
811 | Dprintk("Waiting for send to finish...\n"); | |
812 | timeout = 0; | |
813 | do { | |
814 | Dprintk("+"); | |
815 | udelay(100); | |
816 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
817 | } while (send_status && (timeout++ < 1000)); | |
818 | ||
819 | atomic_set(&init_deasserted, 1); | |
820 | ||
821 | /* | |
822 | * Should we send STARTUP IPIs ? | |
823 | * | |
824 | * Determine this based on the APIC version. | |
825 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
826 | */ | |
827 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
828 | num_starts = 2; | |
829 | else | |
830 | num_starts = 0; | |
831 | ||
832 | /* | |
833 | * Run STARTUP IPI loop. | |
834 | */ | |
835 | Dprintk("#startup loops: %d.\n", num_starts); | |
836 | ||
837 | maxlvt = get_maxlvt(); | |
838 | ||
839 | for (j = 1; j <= num_starts; j++) { | |
840 | Dprintk("Sending STARTUP #%d.\n",j); | |
841 | apic_read_around(APIC_SPIV); | |
842 | apic_write(APIC_ESR, 0); | |
843 | apic_read(APIC_ESR); | |
844 | Dprintk("After apic_write.\n"); | |
845 | ||
846 | /* | |
847 | * STARTUP IPI | |
848 | */ | |
849 | ||
850 | /* Target chip */ | |
851 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
852 | ||
853 | /* Boot on the stack */ | |
854 | /* Kick the second */ | |
855 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
856 | | (start_eip >> 12)); | |
857 | ||
858 | /* | |
859 | * Give the other CPU some time to accept the IPI. | |
860 | */ | |
861 | udelay(300); | |
862 | ||
863 | Dprintk("Startup point 1.\n"); | |
864 | ||
865 | Dprintk("Waiting for send to finish...\n"); | |
866 | timeout = 0; | |
867 | do { | |
868 | Dprintk("+"); | |
869 | udelay(100); | |
870 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
871 | } while (send_status && (timeout++ < 1000)); | |
872 | ||
873 | /* | |
874 | * Give the other CPU some time to accept the IPI. | |
875 | */ | |
876 | udelay(200); | |
877 | /* | |
878 | * Due to the Pentium erratum 3AP. | |
879 | */ | |
880 | if (maxlvt > 3) { | |
881 | apic_read_around(APIC_SPIV); | |
882 | apic_write(APIC_ESR, 0); | |
883 | } | |
884 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
885 | if (send_status || accept_status) | |
886 | break; | |
887 | } | |
888 | Dprintk("After Startup.\n"); | |
889 | ||
890 | if (send_status) | |
891 | printk("APIC never delivered???\n"); | |
892 | if (accept_status) | |
893 | printk("APIC delivery error (%lx).\n", accept_status); | |
894 | ||
895 | return (send_status | accept_status); | |
896 | } | |
897 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
898 | ||
899 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
900 | static inline int alloc_cpu_id(void) |
901 | { | |
902 | cpumask_t tmp_map; | |
903 | int cpu; | |
904 | cpus_complement(tmp_map, cpu_present_map); | |
905 | cpu = first_cpu(tmp_map); | |
906 | if (cpu >= NR_CPUS) | |
907 | return -ENODEV; | |
908 | return cpu; | |
909 | } | |
910 | ||
911 | #ifdef CONFIG_HOTPLUG_CPU | |
912 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
913 | static inline struct task_struct * alloc_idle_task(int cpu) | |
914 | { | |
915 | struct task_struct *idle; | |
916 | ||
917 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
918 | /* initialize thread_struct. we really want to avoid destroy | |
919 | * idle tread | |
920 | */ | |
07b047fc | 921 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
922 | init_idle(idle, cpu); |
923 | return idle; | |
924 | } | |
925 | idle = fork_idle(cpu); | |
926 | ||
927 | if (!IS_ERR(idle)) | |
928 | cpu_idle_tasks[cpu] = idle; | |
929 | return idle; | |
930 | } | |
931 | #else | |
932 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
933 | #endif | |
1da177e4 | 934 | |
e1367daf | 935 | static int __devinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
936 | /* |
937 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
938 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
939 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
940 | */ | |
941 | { | |
942 | struct task_struct *idle; | |
943 | unsigned long boot_error; | |
e1367daf | 944 | int timeout; |
1da177e4 LT |
945 | unsigned long start_eip; |
946 | unsigned short nmi_high = 0, nmi_low = 0; | |
947 | ||
1da177e4 LT |
948 | /* |
949 | * We can't use kernel_thread since we must avoid to | |
950 | * reschedule the child. | |
951 | */ | |
e1367daf | 952 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
953 | if (IS_ERR(idle)) |
954 | panic("failed fork for CPU %d", cpu); | |
62111195 JF |
955 | |
956 | /* Pre-allocate and initialize the CPU's GDT and PDA so it | |
957 | doesn't have to do any memory allocation during the | |
958 | delicate CPU-bringup phase. */ | |
959 | if (!init_gdt(cpu, idle)) { | |
960 | printk(KERN_INFO "Couldn't allocate GDT/PDA for CPU %d\n", cpu); | |
961 | return -1; /* ? */ | |
962 | } | |
963 | ||
1da177e4 LT |
964 | idle->thread.eip = (unsigned long) start_secondary; |
965 | /* start_eip had better be page-aligned! */ | |
966 | start_eip = setup_trampoline(); | |
967 | ||
62111195 JF |
968 | ++cpucount; |
969 | alternatives_smp_switch(1); | |
970 | ||
1da177e4 LT |
971 | /* So we see what's up */ |
972 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
973 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
974 | stack_start.esp = (void *) idle->thread.esp; | |
975 | ||
62111195 JF |
976 | start_pda = cpu_pda(cpu); |
977 | cpu_gdt_descr = per_cpu(cpu_gdt_descr, cpu); | |
978 | ||
1da177e4 LT |
979 | irq_ctx_init(cpu); |
980 | ||
3b08606d | 981 | x86_cpu_to_apicid[cpu] = apicid; |
1da177e4 LT |
982 | /* |
983 | * This grunge runs the startup process for | |
984 | * the targeted processor. | |
985 | */ | |
986 | ||
987 | atomic_set(&init_deasserted, 0); | |
988 | ||
989 | Dprintk("Setting warm reset code and vector.\n"); | |
990 | ||
991 | store_NMI_vector(&nmi_high, &nmi_low); | |
992 | ||
993 | smpboot_setup_warm_reset_vector(start_eip); | |
994 | ||
995 | /* | |
996 | * Starting actual IPI sequence... | |
997 | */ | |
998 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
999 | ||
1000 | if (!boot_error) { | |
1001 | /* | |
1002 | * allow APs to start initializing. | |
1003 | */ | |
1004 | Dprintk("Before Callout %d.\n", cpu); | |
1005 | cpu_set(cpu, cpu_callout_map); | |
1006 | Dprintk("After Callout %d.\n", cpu); | |
1007 | ||
1008 | /* | |
1009 | * Wait 5s total for a response | |
1010 | */ | |
1011 | for (timeout = 0; timeout < 50000; timeout++) { | |
1012 | if (cpu_isset(cpu, cpu_callin_map)) | |
1013 | break; /* It has booted */ | |
1014 | udelay(100); | |
1015 | } | |
1016 | ||
1017 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1018 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1019 | Dprintk("OK.\n"); | |
1020 | printk("CPU%d: ", cpu); | |
1021 | print_cpu_info(&cpu_data[cpu]); | |
1022 | Dprintk("CPU has booted.\n"); | |
1023 | } else { | |
1024 | boot_error= 1; | |
1025 | if (*((volatile unsigned char *)trampoline_base) | |
1026 | == 0xA5) | |
1027 | /* trampoline started but...? */ | |
1028 | printk("Stuck ??\n"); | |
1029 | else | |
1030 | /* trampoline code not run */ | |
1031 | printk("Not responding.\n"); | |
1032 | inquire_remote_apic(apicid); | |
1033 | } | |
1034 | } | |
e1367daf | 1035 | |
1da177e4 LT |
1036 | if (boot_error) { |
1037 | /* Try to put things back the way they were before ... */ | |
1038 | unmap_cpu_to_logical_apicid(cpu); | |
1039 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
1040 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
1041 | cpucount--; | |
e1367daf LS |
1042 | } else { |
1043 | x86_cpu_to_apicid[cpu] = apicid; | |
1044 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
1045 | } |
1046 | ||
1047 | /* mark "stuck" area as not stuck */ | |
1048 | *((volatile unsigned long *)trampoline_base) = 0; | |
1049 | ||
1050 | return boot_error; | |
1051 | } | |
1052 | ||
e1367daf LS |
1053 | #ifdef CONFIG_HOTPLUG_CPU |
1054 | void cpu_exit_clear(void) | |
1055 | { | |
1056 | int cpu = raw_smp_processor_id(); | |
1057 | ||
1058 | idle_task_exit(); | |
1059 | ||
1060 | cpucount --; | |
1061 | cpu_uninit(); | |
1062 | irq_ctx_exit(cpu); | |
1063 | ||
1064 | cpu_clear(cpu, cpu_callout_map); | |
1065 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
1066 | |
1067 | cpu_clear(cpu, smp_commenced_mask); | |
1068 | unmap_cpu_to_logical_apicid(cpu); | |
1069 | } | |
1070 | ||
1071 | struct warm_boot_cpu_info { | |
1072 | struct completion *complete; | |
1073 | int apicid; | |
1074 | int cpu; | |
1075 | }; | |
1076 | ||
34f361ad | 1077 | static void __cpuinit do_warm_boot_cpu(void *p) |
e1367daf LS |
1078 | { |
1079 | struct warm_boot_cpu_info *info = p; | |
1080 | do_boot_cpu(info->apicid, info->cpu); | |
1081 | complete(info->complete); | |
1082 | } | |
1083 | ||
34f361ad | 1084 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf | 1085 | { |
6e9a4738 | 1086 | DECLARE_COMPLETION_ONSTACK(done); |
e1367daf LS |
1087 | struct warm_boot_cpu_info info; |
1088 | struct work_struct task; | |
1089 | int apicid, ret; | |
bd9e0b74 | 1090 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
e1367daf | 1091 | |
e1367daf LS |
1092 | apicid = x86_cpu_to_apicid[cpu]; |
1093 | if (apicid == BAD_APICID) { | |
1094 | ret = -ENODEV; | |
1095 | goto exit; | |
1096 | } | |
1097 | ||
bd9e0b74 SL |
1098 | /* |
1099 | * the CPU isn't initialized at boot time, allocate gdt table here. | |
1100 | * cpu_init will initialize it | |
1101 | */ | |
1102 | if (!cpu_gdt_descr->address) { | |
1103 | cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL); | |
1104 | if (!cpu_gdt_descr->address) | |
1105 | printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu); | |
1106 | ret = -ENOMEM; | |
1107 | goto exit; | |
1108 | } | |
1109 | ||
e1367daf LS |
1110 | info.complete = &done; |
1111 | info.apicid = apicid; | |
1112 | info.cpu = cpu; | |
1113 | INIT_WORK(&task, do_warm_boot_cpu, &info); | |
1114 | ||
1115 | tsc_sync_disabled = 1; | |
1116 | ||
1117 | /* init low mem mapping */ | |
d7271b14 ZA |
1118 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
1119 | KERNEL_PGD_PTRS); | |
e1367daf LS |
1120 | flush_tlb_all(); |
1121 | schedule_work(&task); | |
1122 | wait_for_completion(&done); | |
1123 | ||
1124 | tsc_sync_disabled = 0; | |
1125 | zap_low_mappings(); | |
1126 | ret = 0; | |
1127 | exit: | |
e1367daf LS |
1128 | return ret; |
1129 | } | |
1130 | #endif | |
1131 | ||
1da177e4 LT |
1132 | static void smp_tune_scheduling (void) |
1133 | { | |
1134 | unsigned long cachesize; /* kB */ | |
1135 | unsigned long bandwidth = 350; /* MB/s */ | |
1136 | /* | |
1137 | * Rough estimation for SMP scheduling, this is the number of | |
1138 | * cycles it takes for a fully memory-limited process to flush | |
1139 | * the SMP-local cache. | |
1140 | * | |
1141 | * (For a P5 this pretty much means we will choose another idle | |
1142 | * CPU almost always at wakeup time (this is due to the small | |
1143 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
1144 | * the cache size) | |
1145 | */ | |
1146 | ||
1147 | if (!cpu_khz) { | |
1148 | /* | |
1149 | * this basically disables processor-affinity | |
1150 | * scheduling on SMP without a TSC. | |
1151 | */ | |
1152 | return; | |
1153 | } else { | |
1154 | cachesize = boot_cpu_data.x86_cache_size; | |
1155 | if (cachesize == -1) { | |
1156 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
1157 | bandwidth = 100; | |
1158 | } | |
198e2f18 | 1159 | max_cache_size = cachesize * 1024; |
1da177e4 LT |
1160 | } |
1161 | } | |
1162 | ||
1163 | /* | |
1164 | * Cycle through the processors sending APIC IPIs to boot each. | |
1165 | */ | |
1166 | ||
1167 | static int boot_cpu_logical_apicid; | |
1168 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1169 | void *xquad_portio; | |
129f6946 AD |
1170 | #ifdef CONFIG_X86_NUMAQ |
1171 | EXPORT_SYMBOL(xquad_portio); | |
1172 | #endif | |
1da177e4 | 1173 | |
1da177e4 LT |
1174 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1175 | { | |
1176 | int apicid, cpu, bit, kicked; | |
1177 | unsigned long bogosum = 0; | |
1178 | ||
1179 | /* | |
1180 | * Setup boot CPU information | |
1181 | */ | |
1182 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1183 | printk("CPU%d: ", 0); | |
1184 | print_cpu_info(&cpu_data[0]); | |
1185 | ||
1e4c85f9 | 1186 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1187 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1188 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1189 | ||
1190 | current_thread_info()->cpu = 0; | |
1191 | smp_tune_scheduling(); | |
1da177e4 | 1192 | |
94605eff | 1193 | set_cpu_sibling_map(0); |
3dd9d514 | 1194 | |
1da177e4 LT |
1195 | /* |
1196 | * If we couldn't find an SMP configuration at boot time, | |
1197 | * get out of here now! | |
1198 | */ | |
1199 | if (!smp_found_config && !acpi_lapic) { | |
1200 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1201 | smpboot_clear_io_apic_irqs(); |
1202 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1203 | if (APIC_init_uniprocessor()) | |
1204 | printk(KERN_NOTICE "Local APIC not detected." | |
1205 | " Using dummy APIC emulation.\n"); | |
1206 | map_cpu_to_logical_apicid(); | |
1207 | cpu_set(0, cpu_sibling_map[0]); | |
1208 | cpu_set(0, cpu_core_map[0]); | |
1209 | return; | |
1210 | } | |
1211 | ||
1212 | /* | |
1213 | * Should not be necessary because the MP table should list the boot | |
1214 | * CPU too, but we do it for the sake of robustness anyway. | |
1215 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1216 | */ | |
1217 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1218 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1219 | boot_cpu_physical_apicid); | |
1220 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1221 | } | |
1222 | ||
1223 | /* | |
1224 | * If we couldn't find a local APIC, then get out of here now! | |
1225 | */ | |
1226 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1227 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1228 | boot_cpu_physical_apicid); | |
1229 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1230 | smpboot_clear_io_apic_irqs(); | |
1231 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1232 | cpu_set(0, cpu_sibling_map[0]); | |
1233 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1234 | return; |
1235 | } | |
1236 | ||
1e4c85f9 LT |
1237 | verify_local_APIC(); |
1238 | ||
1da177e4 LT |
1239 | /* |
1240 | * If SMP should be disabled, then really disable it! | |
1241 | */ | |
1e4c85f9 LT |
1242 | if (!max_cpus) { |
1243 | smp_found_config = 0; | |
1244 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1245 | smpboot_clear_io_apic_irqs(); | |
1246 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1247 | cpu_set(0, cpu_sibling_map[0]); | |
1248 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1249 | return; |
1250 | } | |
1251 | ||
1e4c85f9 LT |
1252 | connect_bsp_APIC(); |
1253 | setup_local_APIC(); | |
1254 | map_cpu_to_logical_apicid(); | |
1255 | ||
1256 | ||
1da177e4 LT |
1257 | setup_portio_remap(); |
1258 | ||
1259 | /* | |
1260 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1261 | * | |
1262 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1263 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1264 | * clustered apic ID. | |
1265 | */ | |
1266 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1267 | ||
1268 | kicked = 1; | |
1269 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1270 | apicid = cpu_present_to_apicid(bit); | |
1271 | /* | |
1272 | * Don't even attempt to start the boot CPU! | |
1273 | */ | |
1274 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1275 | continue; | |
1276 | ||
1277 | if (!check_apicid_present(bit)) | |
1278 | continue; | |
1279 | if (max_cpus <= cpucount+1) | |
1280 | continue; | |
1281 | ||
e1367daf | 1282 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1283 | printk("CPU #%d not responding - cannot use it.\n", |
1284 | apicid); | |
1285 | else | |
1286 | ++kicked; | |
1287 | } | |
1288 | ||
1289 | /* | |
1290 | * Cleanup possible dangling ends... | |
1291 | */ | |
1292 | smpboot_restore_warm_reset_vector(); | |
1293 | ||
1294 | /* | |
1295 | * Allow the user to impress friends. | |
1296 | */ | |
1297 | Dprintk("Before bogomips.\n"); | |
1298 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1299 | if (cpu_isset(cpu, cpu_callout_map)) | |
1300 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1301 | printk(KERN_INFO | |
1302 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1303 | cpucount+1, | |
1304 | bogosum/(500000/HZ), | |
1305 | (bogosum/(5000/HZ))%100); | |
1306 | ||
1307 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1308 | ||
1309 | if (smp_b_stepping) | |
1310 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1311 | ||
1312 | /* | |
1313 | * Don't taint if we are running SMP kernel on a single non-MP | |
1314 | * approved Athlon | |
1315 | */ | |
1316 | if (tainted & TAINT_UNSAFE_SMP) { | |
1317 | if (cpucount) | |
1318 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1319 | else | |
1320 | tainted &= ~TAINT_UNSAFE_SMP; | |
1321 | } | |
1322 | ||
1323 | Dprintk("Boot done.\n"); | |
1324 | ||
1325 | /* | |
1326 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1327 | * efficiently. | |
1328 | */ | |
3dd9d514 | 1329 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1330 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1331 | cpus_clear(cpu_core_map[cpu]); |
1332 | } | |
1da177e4 | 1333 | |
d720803a LS |
1334 | cpu_set(0, cpu_sibling_map[0]); |
1335 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1336 | |
1e4c85f9 LT |
1337 | smpboot_setup_io_apic(); |
1338 | ||
1339 | setup_boot_APIC_clock(); | |
1340 | ||
1da177e4 LT |
1341 | /* |
1342 | * Synchronize the TSC with the AP | |
1343 | */ | |
1344 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1345 | synchronize_tsc_bp(); | |
1346 | } | |
1347 | ||
1348 | /* These are wrappers to interface to the new boot process. Someone | |
1349 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1350 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1351 | { | |
f3705136 ZM |
1352 | smp_commenced_mask = cpumask_of_cpu(0); |
1353 | cpu_callin_map = cpumask_of_cpu(0); | |
1354 | mb(); | |
1da177e4 LT |
1355 | smp_boot_cpus(max_cpus); |
1356 | } | |
1357 | ||
1358 | void __devinit smp_prepare_boot_cpu(void) | |
1359 | { | |
1360 | cpu_set(smp_processor_id(), cpu_online_map); | |
1361 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1362 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1363 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1364 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1365 | } |
1366 | ||
f3705136 | 1367 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1368 | static void |
1369 | remove_siblinginfo(int cpu) | |
1da177e4 | 1370 | { |
e1367daf | 1371 | int sibling; |
94605eff | 1372 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1373 | |
94605eff SS |
1374 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1375 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1376 | /* | |
1377 | * last thread sibling in this cpu core going down | |
1378 | */ | |
1379 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1380 | c[sibling].booted_cores--; | |
1381 | } | |
1382 | ||
e1367daf LS |
1383 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1384 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1385 | cpus_clear(cpu_sibling_map[cpu]); |
1386 | cpus_clear(cpu_core_map[cpu]); | |
4b89aff9 RS |
1387 | c[cpu].phys_proc_id = 0; |
1388 | c[cpu].cpu_core_id = 0; | |
94605eff | 1389 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1390 | } |
1391 | ||
1392 | int __cpu_disable(void) | |
1393 | { | |
1394 | cpumask_t map = cpu_online_map; | |
1395 | int cpu = smp_processor_id(); | |
1396 | ||
1397 | /* | |
1398 | * Perhaps use cpufreq to drop frequency, but that could go | |
1399 | * into generic code. | |
1400 | * | |
1401 | * We won't take down the boot processor on i386 due to some | |
1402 | * interrupts only being able to be serviced by the BSP. | |
1403 | * Especially so if we're not using an IOAPIC -zwane | |
1404 | */ | |
1405 | if (cpu == 0) | |
1406 | return -EBUSY; | |
4038f901 SL |
1407 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1408 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1409 | clear_local_APIC(); |
f3705136 ZM |
1410 | /* Allow any queued timer interrupts to get serviced */ |
1411 | local_irq_enable(); | |
1412 | mdelay(1); | |
1413 | local_irq_disable(); | |
1414 | ||
e1367daf LS |
1415 | remove_siblinginfo(cpu); |
1416 | ||
f3705136 ZM |
1417 | cpu_clear(cpu, map); |
1418 | fixup_irqs(map); | |
1419 | /* It's now safe to remove this processor from the online map */ | |
1420 | cpu_clear(cpu, cpu_online_map); | |
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | void __cpu_die(unsigned int cpu) | |
1425 | { | |
1426 | /* We don't do anything here: idle task is faking death itself. */ | |
1427 | unsigned int i; | |
1428 | ||
1429 | for (i = 0; i < 10; i++) { | |
1430 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1431 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1432 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1433 | if (1 == num_online_cpus()) |
1434 | alternatives_smp_switch(0); | |
f3705136 | 1435 | return; |
e1367daf | 1436 | } |
aeb8397b | 1437 | msleep(100); |
1da177e4 | 1438 | } |
f3705136 ZM |
1439 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1440 | } | |
1441 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1442 | int __cpu_disable(void) | |
1443 | { | |
1444 | return -ENOSYS; | |
1445 | } | |
1da177e4 | 1446 | |
f3705136 ZM |
1447 | void __cpu_die(unsigned int cpu) |
1448 | { | |
1449 | /* We said "no" in __cpu_disable */ | |
1450 | BUG(); | |
1451 | } | |
1452 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1453 | ||
1454 | int __devinit __cpu_up(unsigned int cpu) | |
1455 | { | |
34f361ad AR |
1456 | #ifdef CONFIG_HOTPLUG_CPU |
1457 | int ret=0; | |
1458 | ||
1459 | /* | |
1460 | * We do warm boot only on cpus that had booted earlier | |
1461 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1462 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1463 | * when a cpu is taken offline from cpu_exit_clear(). | |
1464 | */ | |
1465 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1466 | ret = __smp_prepare_cpu(cpu); | |
1467 | ||
1468 | if (ret) | |
1469 | return -EIO; | |
1470 | #endif | |
1471 | ||
1da177e4 LT |
1472 | /* In case one didn't come up */ |
1473 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1474 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1475 | local_irq_enable(); |
1476 | return -EIO; | |
1477 | } | |
1478 | ||
1479 | local_irq_enable(); | |
e1367daf | 1480 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1481 | /* Unleash the CPU! */ |
1482 | cpu_set(cpu, smp_commenced_mask); | |
1483 | while (!cpu_isset(cpu, cpu_online_map)) | |
18698917 | 1484 | cpu_relax(); |
1da177e4 LT |
1485 | return 0; |
1486 | } | |
1487 | ||
1488 | void __init smp_cpus_done(unsigned int max_cpus) | |
1489 | { | |
1490 | #ifdef CONFIG_X86_IO_APIC | |
1491 | setup_ioapic_dest(); | |
1492 | #endif | |
1493 | zap_low_mappings(); | |
e1367daf | 1494 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1495 | /* |
1496 | * Disable executability of the SMP trampoline: | |
1497 | */ | |
1498 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1499 | #endif |
1da177e4 LT |
1500 | } |
1501 | ||
1502 | void __init smp_intr_init(void) | |
1503 | { | |
1504 | /* | |
1505 | * IRQ0 must be given a fixed assignment and initialized, | |
1506 | * because it's used before the IO-APIC is set up. | |
1507 | */ | |
1508 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1509 | ||
1510 | /* | |
1511 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1512 | * IPI, driven by wakeup. | |
1513 | */ | |
1514 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1515 | ||
1516 | /* IPI for invalidation */ | |
1517 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1518 | ||
1519 | /* IPI for generic function call */ | |
1520 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1521 | } | |
1a3f239d RR |
1522 | |
1523 | /* | |
1524 | * If the BIOS enumerates physical processors before logical, | |
1525 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1526 | */ | |
1527 | static int __init parse_maxcpus(char *arg) | |
1528 | { | |
1529 | extern unsigned int maxcpus; | |
1530 | ||
1531 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1532 | return 0; | |
1533 | } | |
1534 | early_param("maxcpus", parse_maxcpus); |