]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
43 | #include <linux/smp_lock.h> | |
1da177e4 | 44 | #include <linux/bootmem.h> |
f3705136 ZM |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpu.h> | |
47 | #include <linux/percpu.h> | |
d04f41e3 | 48 | #include <linux/nmi.h> |
1da177e4 LT |
49 | |
50 | #include <linux/delay.h> | |
51 | #include <linux/mc146818rtc.h> | |
52 | #include <asm/tlbflush.h> | |
53 | #include <asm/desc.h> | |
54 | #include <asm/arch_hooks.h> | |
3e4ff115 | 55 | #include <asm/nmi.h> |
1da177e4 LT |
56 | |
57 | #include <mach_apic.h> | |
58 | #include <mach_wakecpu.h> | |
59 | #include <smpboot_hooks.h> | |
7ce0bcfd | 60 | #include <asm/vmi.h> |
2b1f6278 | 61 | #include <asm/mtrr.h> |
1da177e4 LT |
62 | |
63 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 64 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
65 | |
66 | /* Number of siblings per CPU package */ | |
67 | int smp_num_siblings = 1; | |
129f6946 | 68 | EXPORT_SYMBOL(smp_num_siblings); |
d720803a | 69 | |
1e9f28fa SS |
70 | /* Last level cache ID of each logical CPU */ |
71 | int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
72 | ||
94605eff | 73 | /* representing HT siblings of each logical CPU */ |
6c036527 | 74 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
75 | EXPORT_SYMBOL(cpu_sibling_map); |
76 | ||
94605eff | 77 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 78 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
79 | EXPORT_SYMBOL(cpu_core_map); |
80 | ||
1da177e4 | 81 | /* bitmap of online cpus */ |
6c036527 | 82 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 83 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
84 | |
85 | cpumask_t cpu_callin_map; | |
86 | cpumask_t cpu_callout_map; | |
129f6946 | 87 | EXPORT_SYMBOL(cpu_callout_map); |
4ad8d383 ZM |
88 | cpumask_t cpu_possible_map; |
89 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
90 | static cpumask_t smp_commenced_mask; |
91 | ||
92 | /* Per CPU bogomips and other parameters */ | |
93 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 94 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 95 | |
6c036527 | 96 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
97 | { [0 ... NR_CPUS-1] = 0xff }; |
98 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
99 | ||
3b08606d | 100 | u8 apicid_2_node[MAX_APICID]; |
101 | ||
7c3576d2 JF |
102 | DEFINE_PER_CPU(unsigned long, this_cpu_off); |
103 | EXPORT_PER_CPU_SYMBOL(this_cpu_off); | |
104 | ||
1da177e4 LT |
105 | /* |
106 | * Trampoline 80x86 program as an array. | |
107 | */ | |
108 | ||
109 | extern unsigned char trampoline_data []; | |
110 | extern unsigned char trampoline_end []; | |
111 | static unsigned char *trampoline_base; | |
112 | static int trampoline_exec; | |
113 | ||
114 | static void map_cpu_to_logical_apicid(void); | |
115 | ||
f3705136 ZM |
116 | /* State of each CPU. */ |
117 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
118 | ||
1da177e4 LT |
119 | /* |
120 | * Currently trivial. Write the real->protected mode | |
121 | * bootstrap into the page concerned. The caller | |
122 | * has made sure it's suitably aligned. | |
123 | */ | |
124 | ||
0bb3184d | 125 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
126 | { |
127 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
128 | return virt_to_phys(trampoline_base); | |
129 | } | |
130 | ||
131 | /* | |
132 | * We are called very early to get the low memory for the | |
133 | * SMP bootup trampoline page. | |
134 | */ | |
135 | void __init smp_alloc_memory(void) | |
136 | { | |
137 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
138 | /* | |
139 | * Has to be in very low memory so we can execute | |
140 | * real-mode AP code. | |
141 | */ | |
142 | if (__pa(trampoline_base) >= 0x9F000) | |
143 | BUG(); | |
144 | /* | |
145 | * Make the SMP trampoline executable: | |
146 | */ | |
147 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
148 | } | |
149 | ||
150 | /* | |
151 | * The bootstrap kernel entry code has set these up. Save them for | |
152 | * a given CPU | |
153 | */ | |
154 | ||
4a5d107a | 155 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
156 | { |
157 | struct cpuinfo_x86 *c = cpu_data + id; | |
158 | ||
159 | *c = boot_cpu_data; | |
160 | if (id!=0) | |
a6c4e076 | 161 | identify_secondary_cpu(c); |
1da177e4 LT |
162 | /* |
163 | * Mask B, Pentium, but not Pentium MMX | |
164 | */ | |
165 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
166 | c->x86 == 5 && | |
167 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
168 | c->x86_model <= 3) | |
169 | /* | |
170 | * Remember we have B step Pentia with bugs | |
171 | */ | |
172 | smp_b_stepping = 1; | |
173 | ||
174 | /* | |
175 | * Certain Athlons might work (for various values of 'work') in SMP | |
176 | * but they are not certified as MP capable. | |
177 | */ | |
178 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
179 | ||
3ca113ea DJ |
180 | if (num_possible_cpus() == 1) |
181 | goto valid_k7; | |
182 | ||
1da177e4 LT |
183 | /* Athlon 660/661 is valid. */ |
184 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
185 | goto valid_k7; | |
186 | ||
187 | /* Duron 670 is valid */ | |
188 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
189 | goto valid_k7; | |
190 | ||
191 | /* | |
192 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
193 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
194 | * have the MP bit set. | |
195 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
196 | */ | |
197 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
198 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
199 | (c->x86_model> 7)) | |
200 | if (cpu_has_mp) | |
201 | goto valid_k7; | |
202 | ||
203 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 204 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
205 | } |
206 | ||
207 | valid_k7: | |
208 | ; | |
209 | } | |
210 | ||
1da177e4 LT |
211 | extern void calibrate_delay(void); |
212 | ||
213 | static atomic_t init_deasserted; | |
214 | ||
4a5d107a | 215 | static void __cpuinit smp_callin(void) |
1da177e4 LT |
216 | { |
217 | int cpuid, phys_id; | |
218 | unsigned long timeout; | |
219 | ||
220 | /* | |
221 | * If waken up by an INIT in an 82489DX configuration | |
222 | * we may get here before an INIT-deassert IPI reaches | |
223 | * our local APIC. We have to wait for the IPI or we'll | |
224 | * lock up on an APIC access. | |
225 | */ | |
226 | wait_for_init_deassert(&init_deasserted); | |
227 | ||
228 | /* | |
229 | * (This works even if the APIC is not enabled.) | |
230 | */ | |
231 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
232 | cpuid = smp_processor_id(); | |
233 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
234 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
235 | phys_id, cpuid); | |
236 | BUG(); | |
237 | } | |
238 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
239 | ||
240 | /* | |
241 | * STARTUP IPIs are fragile beasts as they might sometimes | |
242 | * trigger some glue motherboard logic. Complete APIC bus | |
243 | * silence for 1 second, this overestimates the time the | |
244 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
245 | * by a factor of two. This should be enough. | |
246 | */ | |
247 | ||
248 | /* | |
249 | * Waiting 2s total for startup (udelay is not yet working) | |
250 | */ | |
251 | timeout = jiffies + 2*HZ; | |
252 | while (time_before(jiffies, timeout)) { | |
253 | /* | |
254 | * Has the boot CPU finished it's STARTUP sequence? | |
255 | */ | |
256 | if (cpu_isset(cpuid, cpu_callout_map)) | |
257 | break; | |
258 | rep_nop(); | |
259 | } | |
260 | ||
261 | if (!time_before(jiffies, timeout)) { | |
262 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
263 | cpuid); | |
264 | BUG(); | |
265 | } | |
266 | ||
267 | /* | |
268 | * the boot CPU has finished the init stage and is spinning | |
269 | * on callin_map until we finish. We are free to set up this | |
270 | * CPU, first the APIC. (this is probably redundant on most | |
271 | * boards) | |
272 | */ | |
273 | ||
274 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
275 | smp_callin_clear_local_apic(); | |
276 | setup_local_APIC(); | |
277 | map_cpu_to_logical_apicid(); | |
278 | ||
279 | /* | |
280 | * Get our bogomips. | |
281 | */ | |
282 | calibrate_delay(); | |
283 | Dprintk("Stack at about %p\n",&cpuid); | |
284 | ||
285 | /* | |
286 | * Save our processor parameters | |
287 | */ | |
e9e2cdb4 | 288 | smp_store_cpu_info(cpuid); |
1da177e4 LT |
289 | |
290 | /* | |
291 | * Allow the master to continue. | |
292 | */ | |
293 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
294 | } |
295 | ||
296 | static int cpucount; | |
297 | ||
1e9f28fa SS |
298 | /* maps the cpu to the sched domain representing multi-core */ |
299 | cpumask_t cpu_coregroup_map(int cpu) | |
300 | { | |
301 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
302 | /* | |
303 | * For perf, we return last level cache shared map. | |
5c45bf27 | 304 | * And for power savings, we return cpu_core_map |
1e9f28fa | 305 | */ |
5c45bf27 SS |
306 | if (sched_mc_power_savings || sched_smt_power_savings) |
307 | return cpu_core_map[cpu]; | |
308 | else | |
309 | return c->llc_shared_map; | |
1e9f28fa SS |
310 | } |
311 | ||
94605eff SS |
312 | /* representing cpus for which sibling maps can be computed */ |
313 | static cpumask_t cpu_sibling_setup_map; | |
314 | ||
d720803a LS |
315 | static inline void |
316 | set_cpu_sibling_map(int cpu) | |
317 | { | |
318 | int i; | |
94605eff SS |
319 | struct cpuinfo_x86 *c = cpu_data; |
320 | ||
321 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
322 | |
323 | if (smp_num_siblings > 1) { | |
94605eff | 324 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
4b89aff9 RS |
325 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
326 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
d720803a LS |
327 | cpu_set(i, cpu_sibling_map[cpu]); |
328 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
329 | cpu_set(i, cpu_core_map[cpu]); |
330 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
331 | cpu_set(i, c[cpu].llc_shared_map); |
332 | cpu_set(cpu, c[i].llc_shared_map); | |
d720803a LS |
333 | } |
334 | } | |
335 | } else { | |
336 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
337 | } | |
338 | ||
1e9f28fa SS |
339 | cpu_set(cpu, c[cpu].llc_shared_map); |
340 | ||
94605eff | 341 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 342 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
343 | c[cpu].booted_cores = 1; |
344 | return; | |
345 | } | |
346 | ||
347 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
348 | if (cpu_llc_id[cpu] != BAD_APICID && |
349 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
350 | cpu_set(i, c[cpu].llc_shared_map); | |
351 | cpu_set(cpu, c[i].llc_shared_map); | |
352 | } | |
4b89aff9 | 353 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
354 | cpu_set(i, cpu_core_map[cpu]); |
355 | cpu_set(cpu, cpu_core_map[i]); | |
356 | /* | |
357 | * Does this new cpu bringup a new core? | |
358 | */ | |
359 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
360 | /* | |
361 | * for each core in package, increment | |
362 | * the booted_cores for this new cpu | |
363 | */ | |
364 | if (first_cpu(cpu_sibling_map[i]) == i) | |
365 | c[cpu].booted_cores++; | |
366 | /* | |
367 | * increment the core count for all | |
368 | * the other cpus in this package | |
369 | */ | |
370 | if (i != cpu) | |
371 | c[i].booted_cores++; | |
372 | } else if (i != cpu && !c[cpu].booted_cores) | |
373 | c[cpu].booted_cores = c[i].booted_cores; | |
374 | } | |
d720803a LS |
375 | } |
376 | } | |
377 | ||
1da177e4 LT |
378 | /* |
379 | * Activate a secondary processor. | |
380 | */ | |
4a5d107a | 381 | static void __cpuinit start_secondary(void *unused) |
1da177e4 LT |
382 | { |
383 | /* | |
d2cbcc49 RR |
384 | * Don't put *anything* before cpu_init(), SMP booting is too |
385 | * fragile that we want to limit the things done here to the | |
386 | * most necessary things. | |
1da177e4 | 387 | */ |
7ce0bcfd ZA |
388 | #ifdef CONFIG_VMI |
389 | vmi_bringup(); | |
390 | #endif | |
d2cbcc49 | 391 | cpu_init(); |
5bfb5d69 | 392 | preempt_disable(); |
1da177e4 LT |
393 | smp_callin(); |
394 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
395 | rep_nop(); | |
95492e46 IM |
396 | /* |
397 | * Check TSC synchronization with the BP: | |
398 | */ | |
399 | check_tsc_sync_target(); | |
400 | ||
bbab4f3b | 401 | setup_secondary_clock(); |
1da177e4 LT |
402 | if (nmi_watchdog == NMI_IO_APIC) { |
403 | disable_8259A_irq(0); | |
404 | enable_NMI_through_LVT0(NULL); | |
405 | enable_8259A_irq(0); | |
406 | } | |
1da177e4 LT |
407 | /* |
408 | * low-memory mappings have been cleared, flush them from | |
409 | * the local TLBs too. | |
410 | */ | |
411 | local_flush_tlb(); | |
6fe940d6 | 412 | |
d720803a LS |
413 | /* This must be done before setting cpu_online_map */ |
414 | set_cpu_sibling_map(raw_smp_processor_id()); | |
415 | wmb(); | |
416 | ||
6fe940d6 LS |
417 | /* |
418 | * We need to hold call_lock, so there is no inconsistency | |
419 | * between the time smp_call_function() determines number of | |
420 | * IPI receipients, and the time when the determination is made | |
421 | * for which cpus receive the IPI. Holding this | |
422 | * lock helps us to not include this cpu in a currently in progress | |
423 | * smp_call_function(). | |
424 | */ | |
425 | lock_ipi_call_lock(); | |
1da177e4 | 426 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 427 | unlock_ipi_call_lock(); |
e1367daf | 428 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
429 | |
430 | /* We can take interrupts now: we're officially "up". */ | |
431 | local_irq_enable(); | |
432 | ||
433 | wmb(); | |
434 | cpu_idle(); | |
435 | } | |
436 | ||
437 | /* | |
438 | * Everything has been set up for the secondary | |
439 | * CPUs - they just need to reload everything | |
440 | * from the task structure | |
441 | * This function must not return. | |
442 | */ | |
0bb3184d | 443 | void __devinit initialize_secondary(void) |
1da177e4 LT |
444 | { |
445 | /* | |
446 | * We don't actually need to load the full TSS, | |
447 | * basically just the stack pointer and the eip. | |
448 | */ | |
449 | ||
450 | asm volatile( | |
451 | "movl %0,%%esp\n\t" | |
452 | "jmp *%1" | |
453 | : | |
62111195 | 454 | :"m" (current->thread.esp),"m" (current->thread.eip)); |
1da177e4 LT |
455 | } |
456 | ||
62111195 | 457 | /* Static state in head.S used to set up a CPU */ |
1da177e4 LT |
458 | extern struct { |
459 | void * esp; | |
460 | unsigned short ss; | |
461 | } stack_start; | |
462 | ||
463 | #ifdef CONFIG_NUMA | |
464 | ||
465 | /* which logical CPUs are on which nodes */ | |
6c036527 | 466 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 | 467 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
a406c366 | 468 | EXPORT_SYMBOL(node_2_cpu_mask); |
1da177e4 | 469 | /* which node each logical CPU is on */ |
6c036527 | 470 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
471 | EXPORT_SYMBOL(cpu_2_node); |
472 | ||
473 | /* set up a mapping between cpu and node. */ | |
474 | static inline void map_cpu_to_node(int cpu, int node) | |
475 | { | |
476 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
477 | cpu_set(cpu, node_2_cpu_mask[node]); | |
478 | cpu_2_node[cpu] = node; | |
479 | } | |
480 | ||
481 | /* undo a mapping between cpu and node. */ | |
482 | static inline void unmap_cpu_to_node(int cpu) | |
483 | { | |
484 | int node; | |
485 | ||
486 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
487 | for (node = 0; node < MAX_NUMNODES; node ++) | |
488 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
489 | cpu_2_node[cpu] = 0; | |
490 | } | |
491 | #else /* !CONFIG_NUMA */ | |
492 | ||
493 | #define map_cpu_to_node(cpu, node) ({}) | |
494 | #define unmap_cpu_to_node(cpu) ({}) | |
495 | ||
496 | #endif /* CONFIG_NUMA */ | |
497 | ||
6c036527 | 498 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
499 | |
500 | static void map_cpu_to_logical_apicid(void) | |
501 | { | |
502 | int cpu = smp_processor_id(); | |
503 | int apicid = logical_smp_processor_id(); | |
78b656b8 | 504 | int node = apicid_to_node(apicid); |
bfa0e9a0 | 505 | |
506 | if (!node_online(node)) | |
507 | node = first_online_node; | |
1da177e4 LT |
508 | |
509 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 510 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
511 | } |
512 | ||
513 | static void unmap_cpu_to_logical_apicid(int cpu) | |
514 | { | |
515 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
516 | unmap_cpu_to_node(cpu); | |
517 | } | |
518 | ||
1da177e4 LT |
519 | static inline void __inquire_remote_apic(int apicid) |
520 | { | |
521 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
522 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
4312fa81 FLV |
523 | int timeout; |
524 | unsigned long status; | |
1da177e4 LT |
525 | |
526 | printk("Inquiring remote APIC #%d...\n", apicid); | |
527 | ||
38e548ee | 528 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
529 | printk("... APIC #%d %s: ", apicid, names[i]); |
530 | ||
531 | /* | |
532 | * Wait for idle. | |
533 | */ | |
4312fa81 FLV |
534 | status = safe_apic_wait_icr_idle(); |
535 | if (status) | |
536 | printk("a previous APIC delivery may have failed\n"); | |
1da177e4 LT |
537 | |
538 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
539 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
540 | ||
541 | timeout = 0; | |
542 | do { | |
543 | udelay(100); | |
544 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
545 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
546 | ||
547 | switch (status) { | |
548 | case APIC_ICR_RR_VALID: | |
549 | status = apic_read(APIC_RRR); | |
ec1180db | 550 | printk("%lx\n", status); |
1da177e4 LT |
551 | break; |
552 | default: | |
553 | printk("failed\n"); | |
554 | } | |
555 | } | |
556 | } | |
1da177e4 LT |
557 | |
558 | #ifdef WAKE_SECONDARY_VIA_NMI | |
559 | /* | |
560 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
561 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
562 | * won't ... remember to clear down the APIC, etc later. | |
563 | */ | |
0bb3184d | 564 | static int __devinit |
1da177e4 LT |
565 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
566 | { | |
ae08e43e FLV |
567 | unsigned long send_status, accept_status = 0; |
568 | int maxlvt; | |
1da177e4 LT |
569 | |
570 | /* Target chip */ | |
571 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
572 | ||
573 | /* Boot on the stack */ | |
574 | /* Kick the second */ | |
575 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
576 | ||
577 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 578 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
579 | |
580 | /* | |
581 | * Give the other CPU some time to accept the IPI. | |
582 | */ | |
583 | udelay(200); | |
584 | /* | |
585 | * Due to the Pentium erratum 3AP. | |
586 | */ | |
e05d723f | 587 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
588 | if (maxlvt > 3) { |
589 | apic_read_around(APIC_SPIV); | |
590 | apic_write(APIC_ESR, 0); | |
591 | } | |
592 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
593 | Dprintk("NMI sent.\n"); | |
594 | ||
595 | if (send_status) | |
596 | printk("APIC never delivered???\n"); | |
597 | if (accept_status) | |
598 | printk("APIC delivery error (%lx).\n", accept_status); | |
599 | ||
600 | return (send_status | accept_status); | |
601 | } | |
602 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
603 | ||
604 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 605 | static int __devinit |
1da177e4 LT |
606 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
607 | { | |
ae08e43e FLV |
608 | unsigned long send_status, accept_status = 0; |
609 | int maxlvt, num_starts, j; | |
1da177e4 LT |
610 | |
611 | /* | |
612 | * Be paranoid about clearing APIC errors. | |
613 | */ | |
614 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
615 | apic_read_around(APIC_SPIV); | |
616 | apic_write(APIC_ESR, 0); | |
617 | apic_read(APIC_ESR); | |
618 | } | |
619 | ||
620 | Dprintk("Asserting INIT.\n"); | |
621 | ||
622 | /* | |
623 | * Turn INIT on target chip | |
624 | */ | |
625 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
626 | ||
627 | /* | |
628 | * Send IPI | |
629 | */ | |
630 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
631 | | APIC_DM_INIT); | |
632 | ||
633 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 634 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
635 | |
636 | mdelay(10); | |
637 | ||
638 | Dprintk("Deasserting INIT.\n"); | |
639 | ||
640 | /* Target chip */ | |
641 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
642 | ||
643 | /* Send IPI */ | |
644 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
645 | ||
646 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 647 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
648 | |
649 | atomic_set(&init_deasserted, 1); | |
650 | ||
651 | /* | |
652 | * Should we send STARTUP IPIs ? | |
653 | * | |
654 | * Determine this based on the APIC version. | |
655 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
656 | */ | |
657 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
658 | num_starts = 2; | |
659 | else | |
660 | num_starts = 0; | |
661 | ||
ae5da273 ZA |
662 | /* |
663 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
664 | * target processor state. | |
665 | */ | |
666 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
667 | (unsigned long) stack_start.esp); | |
668 | ||
1da177e4 LT |
669 | /* |
670 | * Run STARTUP IPI loop. | |
671 | */ | |
672 | Dprintk("#startup loops: %d.\n", num_starts); | |
673 | ||
e05d723f | 674 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
675 | |
676 | for (j = 1; j <= num_starts; j++) { | |
677 | Dprintk("Sending STARTUP #%d.\n",j); | |
678 | apic_read_around(APIC_SPIV); | |
679 | apic_write(APIC_ESR, 0); | |
680 | apic_read(APIC_ESR); | |
681 | Dprintk("After apic_write.\n"); | |
682 | ||
683 | /* | |
684 | * STARTUP IPI | |
685 | */ | |
686 | ||
687 | /* Target chip */ | |
688 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
689 | ||
690 | /* Boot on the stack */ | |
691 | /* Kick the second */ | |
692 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
693 | | (start_eip >> 12)); | |
694 | ||
695 | /* | |
696 | * Give the other CPU some time to accept the IPI. | |
697 | */ | |
698 | udelay(300); | |
699 | ||
700 | Dprintk("Startup point 1.\n"); | |
701 | ||
702 | Dprintk("Waiting for send to finish...\n"); | |
ae08e43e | 703 | send_status = safe_apic_wait_icr_idle(); |
1da177e4 LT |
704 | |
705 | /* | |
706 | * Give the other CPU some time to accept the IPI. | |
707 | */ | |
708 | udelay(200); | |
709 | /* | |
710 | * Due to the Pentium erratum 3AP. | |
711 | */ | |
712 | if (maxlvt > 3) { | |
713 | apic_read_around(APIC_SPIV); | |
714 | apic_write(APIC_ESR, 0); | |
715 | } | |
716 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
717 | if (send_status || accept_status) | |
718 | break; | |
719 | } | |
720 | Dprintk("After Startup.\n"); | |
721 | ||
722 | if (send_status) | |
723 | printk("APIC never delivered???\n"); | |
724 | if (accept_status) | |
725 | printk("APIC delivery error (%lx).\n", accept_status); | |
726 | ||
727 | return (send_status | accept_status); | |
728 | } | |
729 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
730 | ||
731 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
732 | static inline int alloc_cpu_id(void) |
733 | { | |
734 | cpumask_t tmp_map; | |
735 | int cpu; | |
736 | cpus_complement(tmp_map, cpu_present_map); | |
737 | cpu = first_cpu(tmp_map); | |
738 | if (cpu >= NR_CPUS) | |
739 | return -ENODEV; | |
740 | return cpu; | |
741 | } | |
742 | ||
743 | #ifdef CONFIG_HOTPLUG_CPU | |
744 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
745 | static inline struct task_struct * alloc_idle_task(int cpu) | |
746 | { | |
747 | struct task_struct *idle; | |
748 | ||
749 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
750 | /* initialize thread_struct. we really want to avoid destroy | |
751 | * idle tread | |
752 | */ | |
07b047fc | 753 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
754 | init_idle(idle, cpu); |
755 | return idle; | |
756 | } | |
757 | idle = fork_idle(cpu); | |
758 | ||
759 | if (!IS_ERR(idle)) | |
760 | cpu_idle_tasks[cpu] = idle; | |
761 | return idle; | |
762 | } | |
763 | #else | |
764 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
765 | #endif | |
1da177e4 | 766 | |
bf504672 RR |
767 | /* Initialize the CPU's GDT. This is either the boot CPU doing itself |
768 | (still using the master per-cpu area), or a CPU doing it for a | |
769 | secondary which will soon come up. */ | |
7c3576d2 | 770 | static __cpuinit void init_gdt(int cpu) |
bf504672 | 771 | { |
4fbb5968 | 772 | struct desc_struct *gdt = get_cpu_gdt_table(cpu); |
bf504672 | 773 | |
7c3576d2 JF |
774 | pack_descriptor((u32 *)&gdt[GDT_ENTRY_PERCPU].a, |
775 | (u32 *)&gdt[GDT_ENTRY_PERCPU].b, | |
776 | __per_cpu_offset[cpu], 0xFFFFF, | |
777 | 0x80 | DESCTYPE_S | 0x2, 0x8); | |
bf504672 | 778 | |
7c3576d2 JF |
779 | per_cpu(this_cpu_off, cpu) = __per_cpu_offset[cpu]; |
780 | per_cpu(cpu_number, cpu) = cpu; | |
bf504672 RR |
781 | } |
782 | ||
783 | /* Defined in head.S */ | |
784 | extern struct Xgt_desc_struct early_gdt_descr; | |
785 | ||
4a5d107a | 786 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
787 | /* |
788 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
789 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
790 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
791 | */ | |
792 | { | |
793 | struct task_struct *idle; | |
794 | unsigned long boot_error; | |
e1367daf | 795 | int timeout; |
1da177e4 LT |
796 | unsigned long start_eip; |
797 | unsigned short nmi_high = 0, nmi_low = 0; | |
798 | ||
2b1f6278 BK |
799 | /* |
800 | * Save current MTRR state in case it was changed since early boot | |
801 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
802 | */ | |
803 | mtrr_save_state(); | |
804 | ||
1da177e4 LT |
805 | /* |
806 | * We can't use kernel_thread since we must avoid to | |
807 | * reschedule the child. | |
808 | */ | |
e1367daf | 809 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
810 | if (IS_ERR(idle)) |
811 | panic("failed fork for CPU %d", cpu); | |
62111195 | 812 | |
7c3576d2 JF |
813 | init_gdt(cpu); |
814 | per_cpu(current_task, cpu) = idle; | |
bf504672 | 815 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
62111195 | 816 | |
1da177e4 LT |
817 | idle->thread.eip = (unsigned long) start_secondary; |
818 | /* start_eip had better be page-aligned! */ | |
819 | start_eip = setup_trampoline(); | |
820 | ||
62111195 JF |
821 | ++cpucount; |
822 | alternatives_smp_switch(1); | |
823 | ||
1da177e4 LT |
824 | /* So we see what's up */ |
825 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
826 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
827 | stack_start.esp = (void *) idle->thread.esp; | |
828 | ||
829 | irq_ctx_init(cpu); | |
830 | ||
3b08606d | 831 | x86_cpu_to_apicid[cpu] = apicid; |
1da177e4 LT |
832 | /* |
833 | * This grunge runs the startup process for | |
834 | * the targeted processor. | |
835 | */ | |
836 | ||
837 | atomic_set(&init_deasserted, 0); | |
838 | ||
839 | Dprintk("Setting warm reset code and vector.\n"); | |
840 | ||
841 | store_NMI_vector(&nmi_high, &nmi_low); | |
842 | ||
843 | smpboot_setup_warm_reset_vector(start_eip); | |
844 | ||
845 | /* | |
846 | * Starting actual IPI sequence... | |
847 | */ | |
848 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
849 | ||
850 | if (!boot_error) { | |
851 | /* | |
852 | * allow APs to start initializing. | |
853 | */ | |
854 | Dprintk("Before Callout %d.\n", cpu); | |
855 | cpu_set(cpu, cpu_callout_map); | |
856 | Dprintk("After Callout %d.\n", cpu); | |
857 | ||
858 | /* | |
859 | * Wait 5s total for a response | |
860 | */ | |
861 | for (timeout = 0; timeout < 50000; timeout++) { | |
862 | if (cpu_isset(cpu, cpu_callin_map)) | |
863 | break; /* It has booted */ | |
864 | udelay(100); | |
865 | } | |
866 | ||
867 | if (cpu_isset(cpu, cpu_callin_map)) { | |
868 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
869 | Dprintk("OK.\n"); | |
870 | printk("CPU%d: ", cpu); | |
871 | print_cpu_info(&cpu_data[cpu]); | |
872 | Dprintk("CPU has booted.\n"); | |
873 | } else { | |
874 | boot_error= 1; | |
875 | if (*((volatile unsigned char *)trampoline_base) | |
876 | == 0xA5) | |
877 | /* trampoline started but...? */ | |
878 | printk("Stuck ??\n"); | |
879 | else | |
880 | /* trampoline code not run */ | |
881 | printk("Not responding.\n"); | |
882 | inquire_remote_apic(apicid); | |
883 | } | |
884 | } | |
e1367daf | 885 | |
1da177e4 LT |
886 | if (boot_error) { |
887 | /* Try to put things back the way they were before ... */ | |
888 | unmap_cpu_to_logical_apicid(cpu); | |
889 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
890 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
891 | cpucount--; | |
e1367daf LS |
892 | } else { |
893 | x86_cpu_to_apicid[cpu] = apicid; | |
894 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
895 | } |
896 | ||
897 | /* mark "stuck" area as not stuck */ | |
898 | *((volatile unsigned long *)trampoline_base) = 0; | |
899 | ||
900 | return boot_error; | |
901 | } | |
902 | ||
e1367daf LS |
903 | #ifdef CONFIG_HOTPLUG_CPU |
904 | void cpu_exit_clear(void) | |
905 | { | |
906 | int cpu = raw_smp_processor_id(); | |
907 | ||
908 | idle_task_exit(); | |
909 | ||
910 | cpucount --; | |
911 | cpu_uninit(); | |
912 | irq_ctx_exit(cpu); | |
913 | ||
914 | cpu_clear(cpu, cpu_callout_map); | |
915 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
916 | |
917 | cpu_clear(cpu, smp_commenced_mask); | |
918 | unmap_cpu_to_logical_apicid(cpu); | |
919 | } | |
920 | ||
921 | struct warm_boot_cpu_info { | |
922 | struct completion *complete; | |
c4028958 | 923 | struct work_struct task; |
e1367daf LS |
924 | int apicid; |
925 | int cpu; | |
926 | }; | |
927 | ||
c4028958 | 928 | static void __cpuinit do_warm_boot_cpu(struct work_struct *work) |
e1367daf | 929 | { |
c4028958 DH |
930 | struct warm_boot_cpu_info *info = |
931 | container_of(work, struct warm_boot_cpu_info, task); | |
e1367daf LS |
932 | do_boot_cpu(info->apicid, info->cpu); |
933 | complete(info->complete); | |
934 | } | |
935 | ||
34f361ad | 936 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf | 937 | { |
6e9a4738 | 938 | DECLARE_COMPLETION_ONSTACK(done); |
e1367daf | 939 | struct warm_boot_cpu_info info; |
e1367daf LS |
940 | int apicid, ret; |
941 | ||
e1367daf LS |
942 | apicid = x86_cpu_to_apicid[cpu]; |
943 | if (apicid == BAD_APICID) { | |
944 | ret = -ENODEV; | |
945 | goto exit; | |
946 | } | |
947 | ||
948 | info.complete = &done; | |
949 | info.apicid = apicid; | |
950 | info.cpu = cpu; | |
c4028958 | 951 | INIT_WORK(&info.task, do_warm_boot_cpu); |
e1367daf | 952 | |
e1367daf | 953 | /* init low mem mapping */ |
d7271b14 | 954 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
3b1bdf4e | 955 | min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS)); |
e1367daf | 956 | flush_tlb_all(); |
c4028958 | 957 | schedule_work(&info.task); |
e1367daf LS |
958 | wait_for_completion(&done); |
959 | ||
e1367daf LS |
960 | zap_low_mappings(); |
961 | ret = 0; | |
962 | exit: | |
e1367daf LS |
963 | return ret; |
964 | } | |
965 | #endif | |
966 | ||
d9408cef | 967 | static void smp_tune_scheduling(void) |
1da177e4 LT |
968 | { |
969 | unsigned long cachesize; /* kB */ | |
1da177e4 | 970 | |
d9408cef | 971 | if (cpu_khz) { |
1da177e4 | 972 | cachesize = boot_cpu_data.x86_cache_size; |
d9408cef AB |
973 | |
974 | if (cachesize > 0) | |
975 | max_cache_size = cachesize * 1024; | |
1da177e4 LT |
976 | } |
977 | } | |
978 | ||
979 | /* | |
980 | * Cycle through the processors sending APIC IPIs to boot each. | |
981 | */ | |
982 | ||
983 | static int boot_cpu_logical_apicid; | |
984 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
985 | void *xquad_portio; | |
129f6946 AD |
986 | #ifdef CONFIG_X86_NUMAQ |
987 | EXPORT_SYMBOL(xquad_portio); | |
988 | #endif | |
1da177e4 | 989 | |
1da177e4 LT |
990 | static void __init smp_boot_cpus(unsigned int max_cpus) |
991 | { | |
992 | int apicid, cpu, bit, kicked; | |
993 | unsigned long bogosum = 0; | |
994 | ||
995 | /* | |
996 | * Setup boot CPU information | |
997 | */ | |
998 | smp_store_cpu_info(0); /* Final full version of the data */ | |
999 | printk("CPU%d: ", 0); | |
1000 | print_cpu_info(&cpu_data[0]); | |
1001 | ||
1e4c85f9 | 1002 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1003 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1004 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1005 | ||
1006 | current_thread_info()->cpu = 0; | |
1007 | smp_tune_scheduling(); | |
1da177e4 | 1008 | |
94605eff | 1009 | set_cpu_sibling_map(0); |
3dd9d514 | 1010 | |
1da177e4 LT |
1011 | /* |
1012 | * If we couldn't find an SMP configuration at boot time, | |
1013 | * get out of here now! | |
1014 | */ | |
1015 | if (!smp_found_config && !acpi_lapic) { | |
1016 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1017 | smpboot_clear_io_apic_irqs(); |
1018 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1019 | if (APIC_init_uniprocessor()) | |
1020 | printk(KERN_NOTICE "Local APIC not detected." | |
1021 | " Using dummy APIC emulation.\n"); | |
1022 | map_cpu_to_logical_apicid(); | |
1023 | cpu_set(0, cpu_sibling_map[0]); | |
1024 | cpu_set(0, cpu_core_map[0]); | |
1025 | return; | |
1026 | } | |
1027 | ||
1028 | /* | |
1029 | * Should not be necessary because the MP table should list the boot | |
1030 | * CPU too, but we do it for the sake of robustness anyway. | |
1031 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1032 | */ | |
1033 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1034 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1035 | boot_cpu_physical_apicid); | |
1036 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1037 | } | |
1038 | ||
1039 | /* | |
1040 | * If we couldn't find a local APIC, then get out of here now! | |
1041 | */ | |
1042 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1043 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1044 | boot_cpu_physical_apicid); | |
1045 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1046 | smpboot_clear_io_apic_irqs(); | |
1047 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1048 | cpu_set(0, cpu_sibling_map[0]); | |
1049 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1050 | return; |
1051 | } | |
1052 | ||
1e4c85f9 LT |
1053 | verify_local_APIC(); |
1054 | ||
1da177e4 LT |
1055 | /* |
1056 | * If SMP should be disabled, then really disable it! | |
1057 | */ | |
1e4c85f9 LT |
1058 | if (!max_cpus) { |
1059 | smp_found_config = 0; | |
1060 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1061 | smpboot_clear_io_apic_irqs(); | |
1062 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1063 | cpu_set(0, cpu_sibling_map[0]); | |
1064 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1065 | return; |
1066 | } | |
1067 | ||
1e4c85f9 LT |
1068 | connect_bsp_APIC(); |
1069 | setup_local_APIC(); | |
1070 | map_cpu_to_logical_apicid(); | |
1071 | ||
1072 | ||
1da177e4 LT |
1073 | setup_portio_remap(); |
1074 | ||
1075 | /* | |
1076 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1077 | * | |
1078 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1079 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1080 | * clustered apic ID. | |
1081 | */ | |
1082 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1083 | ||
1084 | kicked = 1; | |
1085 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1086 | apicid = cpu_present_to_apicid(bit); | |
1087 | /* | |
1088 | * Don't even attempt to start the boot CPU! | |
1089 | */ | |
1090 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1091 | continue; | |
1092 | ||
1093 | if (!check_apicid_present(bit)) | |
1094 | continue; | |
1095 | if (max_cpus <= cpucount+1) | |
1096 | continue; | |
1097 | ||
e1367daf | 1098 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1099 | printk("CPU #%d not responding - cannot use it.\n", |
1100 | apicid); | |
1101 | else | |
1102 | ++kicked; | |
1103 | } | |
1104 | ||
1105 | /* | |
1106 | * Cleanup possible dangling ends... | |
1107 | */ | |
1108 | smpboot_restore_warm_reset_vector(); | |
1109 | ||
1110 | /* | |
1111 | * Allow the user to impress friends. | |
1112 | */ | |
1113 | Dprintk("Before bogomips.\n"); | |
1114 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1115 | if (cpu_isset(cpu, cpu_callout_map)) | |
1116 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1117 | printk(KERN_INFO | |
1118 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1119 | cpucount+1, | |
1120 | bogosum/(500000/HZ), | |
1121 | (bogosum/(5000/HZ))%100); | |
1122 | ||
1123 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1124 | ||
1125 | if (smp_b_stepping) | |
1126 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1127 | ||
1128 | /* | |
1129 | * Don't taint if we are running SMP kernel on a single non-MP | |
1130 | * approved Athlon | |
1131 | */ | |
1132 | if (tainted & TAINT_UNSAFE_SMP) { | |
1133 | if (cpucount) | |
1134 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1135 | else | |
1136 | tainted &= ~TAINT_UNSAFE_SMP; | |
1137 | } | |
1138 | ||
1139 | Dprintk("Boot done.\n"); | |
1140 | ||
1141 | /* | |
1142 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1143 | * efficiently. | |
1144 | */ | |
3dd9d514 | 1145 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1146 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1147 | cpus_clear(cpu_core_map[cpu]); |
1148 | } | |
1da177e4 | 1149 | |
d720803a LS |
1150 | cpu_set(0, cpu_sibling_map[0]); |
1151 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1152 | |
1e4c85f9 LT |
1153 | smpboot_setup_io_apic(); |
1154 | ||
bbab4f3b | 1155 | setup_boot_clock(); |
1da177e4 LT |
1156 | } |
1157 | ||
1158 | /* These are wrappers to interface to the new boot process. Someone | |
1159 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
01a2f435 | 1160 | void __init native_smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 1161 | { |
f3705136 ZM |
1162 | smp_commenced_mask = cpumask_of_cpu(0); |
1163 | cpu_callin_map = cpumask_of_cpu(0); | |
1164 | mb(); | |
1da177e4 LT |
1165 | smp_boot_cpus(max_cpus); |
1166 | } | |
1167 | ||
01a2f435 | 1168 | void __init native_smp_prepare_boot_cpu(void) |
bf504672 RR |
1169 | { |
1170 | unsigned int cpu = smp_processor_id(); | |
1171 | ||
7c3576d2 | 1172 | init_gdt(cpu); |
bf504672 RR |
1173 | switch_to_new_gdt(); |
1174 | ||
1175 | cpu_set(cpu, cpu_online_map); | |
1176 | cpu_set(cpu, cpu_callout_map); | |
1177 | cpu_set(cpu, cpu_present_map); | |
1178 | cpu_set(cpu, cpu_possible_map); | |
1179 | __get_cpu_var(cpu_state) = CPU_ONLINE; | |
1da177e4 LT |
1180 | } |
1181 | ||
f3705136 | 1182 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1183 | static void |
1184 | remove_siblinginfo(int cpu) | |
1da177e4 | 1185 | { |
e1367daf | 1186 | int sibling; |
94605eff | 1187 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1188 | |
94605eff SS |
1189 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1190 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1191 | /* | |
1192 | * last thread sibling in this cpu core going down | |
1193 | */ | |
1194 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1195 | c[sibling].booted_cores--; | |
1196 | } | |
1197 | ||
e1367daf LS |
1198 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1199 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1200 | cpus_clear(cpu_sibling_map[cpu]); |
1201 | cpus_clear(cpu_core_map[cpu]); | |
4b89aff9 RS |
1202 | c[cpu].phys_proc_id = 0; |
1203 | c[cpu].cpu_core_id = 0; | |
94605eff | 1204 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1205 | } |
1206 | ||
1207 | int __cpu_disable(void) | |
1208 | { | |
1209 | cpumask_t map = cpu_online_map; | |
1210 | int cpu = smp_processor_id(); | |
1211 | ||
1212 | /* | |
1213 | * Perhaps use cpufreq to drop frequency, but that could go | |
1214 | * into generic code. | |
1215 | * | |
1216 | * We won't take down the boot processor on i386 due to some | |
1217 | * interrupts only being able to be serviced by the BSP. | |
1218 | * Especially so if we're not using an IOAPIC -zwane | |
1219 | */ | |
1220 | if (cpu == 0) | |
1221 | return -EBUSY; | |
4038f901 SL |
1222 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1223 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1224 | clear_local_APIC(); |
f3705136 ZM |
1225 | /* Allow any queued timer interrupts to get serviced */ |
1226 | local_irq_enable(); | |
1227 | mdelay(1); | |
1228 | local_irq_disable(); | |
1229 | ||
e1367daf LS |
1230 | remove_siblinginfo(cpu); |
1231 | ||
f3705136 ZM |
1232 | cpu_clear(cpu, map); |
1233 | fixup_irqs(map); | |
1234 | /* It's now safe to remove this processor from the online map */ | |
1235 | cpu_clear(cpu, cpu_online_map); | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | void __cpu_die(unsigned int cpu) | |
1240 | { | |
1241 | /* We don't do anything here: idle task is faking death itself. */ | |
1242 | unsigned int i; | |
1243 | ||
1244 | for (i = 0; i < 10; i++) { | |
1245 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1246 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1247 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1248 | if (1 == num_online_cpus()) |
1249 | alternatives_smp_switch(0); | |
f3705136 | 1250 | return; |
e1367daf | 1251 | } |
aeb8397b | 1252 | msleep(100); |
1da177e4 | 1253 | } |
f3705136 ZM |
1254 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1255 | } | |
1256 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1257 | int __cpu_disable(void) | |
1258 | { | |
1259 | return -ENOSYS; | |
1260 | } | |
1da177e4 | 1261 | |
f3705136 ZM |
1262 | void __cpu_die(unsigned int cpu) |
1263 | { | |
1264 | /* We said "no" in __cpu_disable */ | |
1265 | BUG(); | |
1266 | } | |
1267 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1268 | ||
01a2f435 | 1269 | int __cpuinit native_cpu_up(unsigned int cpu) |
f3705136 | 1270 | { |
d04f41e3 | 1271 | unsigned long flags; |
34f361ad | 1272 | #ifdef CONFIG_HOTPLUG_CPU |
d04f41e3 | 1273 | int ret = 0; |
34f361ad AR |
1274 | |
1275 | /* | |
1276 | * We do warm boot only on cpus that had booted earlier | |
1277 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1278 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1279 | * when a cpu is taken offline from cpu_exit_clear(). | |
1280 | */ | |
1281 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1282 | ret = __smp_prepare_cpu(cpu); | |
1283 | ||
1284 | if (ret) | |
1285 | return -EIO; | |
1286 | #endif | |
1287 | ||
1da177e4 LT |
1288 | /* In case one didn't come up */ |
1289 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1290 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1291 | return -EIO; |
1292 | } | |
1293 | ||
e1367daf | 1294 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1295 | /* Unleash the CPU! */ |
1296 | cpu_set(cpu, smp_commenced_mask); | |
95492e46 IM |
1297 | |
1298 | /* | |
d04f41e3 IM |
1299 | * Check TSC synchronization with the AP (keep irqs disabled |
1300 | * while doing so): | |
95492e46 | 1301 | */ |
d04f41e3 | 1302 | local_irq_save(flags); |
95492e46 | 1303 | check_tsc_sync_source(cpu); |
d04f41e3 | 1304 | local_irq_restore(flags); |
95492e46 | 1305 | |
d04f41e3 | 1306 | while (!cpu_isset(cpu, cpu_online_map)) { |
18698917 | 1307 | cpu_relax(); |
d04f41e3 IM |
1308 | touch_nmi_watchdog(); |
1309 | } | |
b0d0a4ba | 1310 | |
1da177e4 LT |
1311 | return 0; |
1312 | } | |
1313 | ||
01a2f435 | 1314 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1da177e4 LT |
1315 | { |
1316 | #ifdef CONFIG_X86_IO_APIC | |
1317 | setup_ioapic_dest(); | |
1318 | #endif | |
1319 | zap_low_mappings(); | |
e1367daf | 1320 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1321 | /* |
1322 | * Disable executability of the SMP trampoline: | |
1323 | */ | |
1324 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1325 | #endif |
1da177e4 LT |
1326 | } |
1327 | ||
1328 | void __init smp_intr_init(void) | |
1329 | { | |
1330 | /* | |
1331 | * IRQ0 must be given a fixed assignment and initialized, | |
1332 | * because it's used before the IO-APIC is set up. | |
1333 | */ | |
1334 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1335 | ||
1336 | /* | |
1337 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1338 | * IPI, driven by wakeup. | |
1339 | */ | |
1340 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1341 | ||
1342 | /* IPI for invalidation */ | |
1343 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1344 | ||
1345 | /* IPI for generic function call */ | |
1346 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1347 | } | |
1a3f239d RR |
1348 | |
1349 | /* | |
1350 | * If the BIOS enumerates physical processors before logical, | |
1351 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1352 | */ | |
1353 | static int __init parse_maxcpus(char *arg) | |
1354 | { | |
1355 | extern unsigned int maxcpus; | |
1356 | ||
1357 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1358 | return 0; | |
1359 | } | |
1360 | early_param("maxcpus", parse_maxcpus); |