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1da177e4 LT |
1 | /* |
2 | * linux/arch/i386/kernel/time.c | |
3 | * | |
4 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
5 | * | |
6 | * This file contains the PC-specific time handling details: | |
7 | * reading the RTC at bootup, etc.. | |
8 | * 1994-07-02 Alan Modra | |
9 | * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime | |
10 | * 1995-03-26 Markus Kuhn | |
11 | * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887 | |
12 | * precision CMOS clock update | |
13 | * 1996-05-03 Ingo Molnar | |
14 | * fixed time warps in do_[slow|fast]_gettimeoffset() | |
15 | * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 | |
16 | * "A Kernel Model for Precision Timekeeping" by Dave Mills | |
17 | * 1998-09-05 (Various) | |
18 | * More robust do_fast_gettimeoffset() algorithm implemented | |
19 | * (works with APM, Cyrix 6x86MX and Centaur C6), | |
20 | * monotonic gettimeofday() with fast_get_timeoffset(), | |
21 | * drift-proof precision TSC calibration on boot | |
22 | * (C. Scott Ananian <cananian@alumni.princeton.edu>, Andrew D. | |
23 | * Balsa <andrebalsa@altern.org>, Philip Gladstone <philip@raptor.com>; | |
24 | * ported from 2.0.35 Jumbo-9 by Michael Krause <m.krause@tu-harburg.de>). | |
25 | * 1998-12-16 Andrea Arcangeli | |
26 | * Fixed Jumbo-9 code in 2.1.131: do_gettimeofday was missing 1 jiffy | |
27 | * because was not accounting lost_ticks. | |
28 | * 1998-12-24 Copyright (C) 1998 Andrea Arcangeli | |
29 | * Fixed a xtime SMP race (we need the xtime_lock rw spinlock to | |
30 | * serialize accesses to xtime/lost_ticks). | |
31 | */ | |
32 | ||
33 | #include <linux/errno.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/param.h> | |
37 | #include <linux/string.h> | |
38 | #include <linux/mm.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/time.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/smp.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/sysdev.h> | |
46 | #include <linux/bcd.h> | |
47 | #include <linux/efi.h> | |
48 | #include <linux/mca.h> | |
49 | ||
50 | #include <asm/io.h> | |
51 | #include <asm/smp.h> | |
52 | #include <asm/irq.h> | |
53 | #include <asm/msr.h> | |
54 | #include <asm/delay.h> | |
55 | #include <asm/mpspec.h> | |
56 | #include <asm/uaccess.h> | |
57 | #include <asm/processor.h> | |
58 | #include <asm/timer.h> | |
d3561b7f | 59 | #include <asm/time.h> |
1da177e4 LT |
60 | |
61 | #include "mach_time.h" | |
62 | ||
63 | #include <linux/timex.h> | |
1da177e4 LT |
64 | |
65 | #include <asm/hpet.h> | |
66 | ||
67 | #include <asm/arch_hooks.h> | |
68 | ||
69 | #include "io_ports.h" | |
70 | ||
306e440d IM |
71 | #include <asm/i8259.h> |
72 | ||
1da177e4 LT |
73 | int pit_latch_buggy; /* extern */ |
74 | ||
75 | #include "do_timer.h" | |
76 | ||
a3a255e7 | 77 | unsigned int cpu_khz; /* Detected as we calibrate the TSC */ |
129f6946 | 78 | EXPORT_SYMBOL(cpu_khz); |
1da177e4 | 79 | |
1da177e4 | 80 | DEFINE_SPINLOCK(rtc_lock); |
129f6946 | 81 | EXPORT_SYMBOL(rtc_lock); |
1da177e4 | 82 | |
1da177e4 LT |
83 | /* |
84 | * This is a special lock that is owned by the CPU and holds the index | |
85 | * register we are working with. It is required for NMI access to the | |
86 | * CMOS/RTC registers. See include/asm-i386/mc146818rtc.h for details. | |
87 | */ | |
88 | volatile unsigned long cmos_lock = 0; | |
89 | EXPORT_SYMBOL(cmos_lock); | |
90 | ||
91 | /* Routines for accessing the CMOS RAM/RTC. */ | |
92 | unsigned char rtc_cmos_read(unsigned char addr) | |
93 | { | |
94 | unsigned char val; | |
95 | lock_cmos_prefix(addr); | |
96 | outb_p(addr, RTC_PORT(0)); | |
97 | val = inb_p(RTC_PORT(1)); | |
98 | lock_cmos_suffix(addr); | |
99 | return val; | |
100 | } | |
101 | EXPORT_SYMBOL(rtc_cmos_read); | |
102 | ||
103 | void rtc_cmos_write(unsigned char val, unsigned char addr) | |
104 | { | |
105 | lock_cmos_prefix(addr); | |
106 | outb_p(addr, RTC_PORT(0)); | |
107 | outb_p(val, RTC_PORT(1)); | |
108 | lock_cmos_suffix(addr); | |
109 | } | |
110 | EXPORT_SYMBOL(rtc_cmos_write); | |
111 | ||
1da177e4 LT |
112 | static int set_rtc_mmss(unsigned long nowtime) |
113 | { | |
114 | int retval; | |
6f84fa2f | 115 | unsigned long flags; |
1da177e4 LT |
116 | |
117 | /* gets recalled with irq locally disabled */ | |
6f84fa2f JS |
118 | /* XXX - does irqsave resolve this? -johnstul */ |
119 | spin_lock_irqsave(&rtc_lock, flags); | |
d3561b7f | 120 | retval = set_wallclock(nowtime); |
6f84fa2f | 121 | spin_unlock_irqrestore(&rtc_lock, flags); |
1da177e4 LT |
122 | |
123 | return retval; | |
124 | } | |
125 | ||
126 | ||
127 | int timer_ack; | |
128 | ||
1da177e4 LT |
129 | unsigned long profile_pc(struct pt_regs *regs) |
130 | { | |
131 | unsigned long pc = instruction_pointer(regs); | |
132 | ||
0cb91a22 AK |
133 | #ifdef CONFIG_SMP |
134 | if (!user_mode_vm(regs) && in_lock_functions(pc)) { | |
135 | #ifdef CONFIG_FRAME_POINTER | |
1da177e4 | 136 | return *(unsigned long *)(regs->ebp + 4); |
0cb91a22 AK |
137 | #else |
138 | unsigned long *sp; | |
139 | if ((regs->xcs & 3) == 0) | |
140 | sp = (unsigned long *)®s->esp; | |
141 | else | |
142 | sp = (unsigned long *)regs->esp; | |
143 | /* Return address is either directly at stack pointer | |
144 | or above a saved eflags. Eflags has bits 22-31 zero, | |
145 | kernel addresses don't. */ | |
146 | if (sp[0] >> 22) | |
147 | return sp[0]; | |
148 | if (sp[1] >> 22) | |
149 | return sp[1]; | |
150 | #endif | |
151 | } | |
152 | #endif | |
1da177e4 LT |
153 | return pc; |
154 | } | |
155 | EXPORT_SYMBOL(profile_pc); | |
1da177e4 LT |
156 | |
157 | /* | |
6f84fa2f JS |
158 | * This is the same as the above, except we _also_ save the current |
159 | * Time Stamp Counter value at the time of the timer interrupt, so that | |
160 | * we later on can estimate the time of day more exactly. | |
1da177e4 | 161 | */ |
7d12e780 | 162 | irqreturn_t timer_interrupt(int irq, void *dev_id) |
1da177e4 | 163 | { |
6f84fa2f JS |
164 | /* |
165 | * Here we are in the timer irq handler. We just have irqs locally | |
166 | * disabled but we don't know if the timer_bh is running on the other | |
167 | * CPU. We need to avoid to SMP race with it. NOTE: we don' t need | |
168 | * the irq version of write_lock because as just said we have irq | |
169 | * locally disabled. -arca | |
170 | */ | |
171 | write_seqlock(&xtime_lock); | |
172 | ||
1da177e4 LT |
173 | #ifdef CONFIG_X86_IO_APIC |
174 | if (timer_ack) { | |
175 | /* | |
176 | * Subtle, when I/O APICs are used we have to ack timer IRQ | |
177 | * manually to reset the IRR bit for do_slow_gettimeoffset(). | |
178 | * This will also deassert NMI lines for the watchdog if run | |
179 | * on an 82489DX-based system. | |
180 | */ | |
181 | spin_lock(&i8259A_lock); | |
182 | outb(0x0c, PIC_MASTER_OCW3); | |
183 | /* Ack the IRQ; AEOI will end it automatically. */ | |
184 | inb(PIC_MASTER_POLL); | |
185 | spin_unlock(&i8259A_lock); | |
186 | } | |
187 | #endif | |
188 | ||
7d12e780 | 189 | do_timer_interrupt_hook(); |
1da177e4 LT |
190 | |
191 | ||
192 | if (MCA_bus) { | |
193 | /* The PS/2 uses level-triggered interrupts. You can't | |
194 | turn them off, nor would you want to (any attempt to | |
195 | enable edge-triggered interrupts usually gets intercepted by a | |
196 | special hardware circuit). Hence we have to acknowledge | |
197 | the timer interrupt. Through some incredibly stupid | |
198 | design idea, the reset for IRQ 0 is done by setting the | |
199 | high bit of the PPI port B (0x61). Note that some PS/2s, | |
200 | notably the 55SX, work fine if this is removed. */ | |
201 | ||
86d91bab JG |
202 | u8 irq_v = inb_p( 0x61 ); /* read the current state */ |
203 | outb_p( irq_v|0x80, 0x61 ); /* reset the IRQ */ | |
1da177e4 | 204 | } |
1da177e4 LT |
205 | |
206 | write_sequnlock(&xtime_lock); | |
6eb0a0fd VP |
207 | |
208 | #ifdef CONFIG_X86_LOCAL_APIC | |
209 | if (using_apic_timer) | |
7d12e780 | 210 | smp_send_timer_broadcast_ipi(); |
6eb0a0fd VP |
211 | #endif |
212 | ||
1da177e4 LT |
213 | return IRQ_HANDLED; |
214 | } | |
215 | ||
216 | /* not static: needed by APM */ | |
217 | unsigned long get_cmos_time(void) | |
218 | { | |
219 | unsigned long retval; | |
7ba1c6c8 | 220 | unsigned long flags; |
1da177e4 | 221 | |
7ba1c6c8 | 222 | spin_lock_irqsave(&rtc_lock, flags); |
1da177e4 | 223 | |
d3561b7f | 224 | retval = get_wallclock(); |
1da177e4 | 225 | |
7ba1c6c8 | 226 | spin_unlock_irqrestore(&rtc_lock, flags); |
1da177e4 LT |
227 | |
228 | return retval; | |
229 | } | |
129f6946 AD |
230 | EXPORT_SYMBOL(get_cmos_time); |
231 | ||
1da177e4 LT |
232 | static void sync_cmos_clock(unsigned long dummy); |
233 | ||
8d06afab | 234 | static DEFINE_TIMER(sync_cmos_timer, sync_cmos_clock, 0, 0); |
1da177e4 LT |
235 | |
236 | static void sync_cmos_clock(unsigned long dummy) | |
237 | { | |
238 | struct timeval now, next; | |
239 | int fail = 1; | |
240 | ||
241 | /* | |
242 | * If we have an externally synchronized Linux clock, then update | |
243 | * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be | |
244 | * called as close as possible to 500 ms before the new second starts. | |
245 | * This code is run on a timer. If the clock is set, that timer | |
246 | * may not expire at the correct time. Thus, we adjust... | |
247 | */ | |
b149ee22 | 248 | if (!ntp_synced()) |
1da177e4 LT |
249 | /* |
250 | * Not synced, exit, do not restart a timer (if one is | |
251 | * running, let it run out). | |
252 | */ | |
253 | return; | |
254 | ||
255 | do_gettimeofday(&now); | |
256 | if (now.tv_usec >= USEC_AFTER - ((unsigned) TICK_SIZE) / 2 && | |
257 | now.tv_usec <= USEC_BEFORE + ((unsigned) TICK_SIZE) / 2) | |
258 | fail = set_rtc_mmss(now.tv_sec); | |
259 | ||
260 | next.tv_usec = USEC_AFTER - now.tv_usec; | |
261 | if (next.tv_usec <= 0) | |
262 | next.tv_usec += USEC_PER_SEC; | |
263 | ||
264 | if (!fail) | |
265 | next.tv_sec = 659; | |
266 | else | |
267 | next.tv_sec = 0; | |
268 | ||
269 | if (next.tv_usec >= USEC_PER_SEC) { | |
270 | next.tv_sec++; | |
271 | next.tv_usec -= USEC_PER_SEC; | |
272 | } | |
273 | mod_timer(&sync_cmos_timer, jiffies + timeval_to_jiffies(&next)); | |
274 | } | |
275 | ||
276 | void notify_arch_cmos_timer(void) | |
277 | { | |
278 | mod_timer(&sync_cmos_timer, jiffies + 1); | |
279 | } | |
280 | ||
7d145aa3 RW |
281 | static long clock_cmos_diff; |
282 | static unsigned long sleep_start; | |
1da177e4 | 283 | |
438510f6 | 284 | static int timer_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
285 | { |
286 | /* | |
287 | * Estimate time zone so that set_time can update the clock | |
288 | */ | |
7d145aa3 RW |
289 | unsigned long ctime = get_cmos_time(); |
290 | ||
291 | clock_cmos_diff = -ctime; | |
1da177e4 | 292 | clock_cmos_diff += get_seconds(); |
7d145aa3 | 293 | sleep_start = ctime; |
1da177e4 LT |
294 | return 0; |
295 | } | |
296 | ||
297 | static int timer_resume(struct sys_device *dev) | |
298 | { | |
299 | unsigned long flags; | |
300 | unsigned long sec; | |
7d145aa3 RW |
301 | unsigned long ctime = get_cmos_time(); |
302 | long sleep_length = (ctime - sleep_start) * HZ; | |
c7f40ff1 | 303 | struct timespec ts; |
7d145aa3 RW |
304 | |
305 | if (sleep_length < 0) { | |
306 | printk(KERN_WARNING "CMOS clock skew detected in timer resume!\n"); | |
307 | /* The time after the resume must not be earlier than the time | |
308 | * before the suspend or some nasty things will happen | |
309 | */ | |
310 | sleep_length = 0; | |
311 | ctime = sleep_start; | |
312 | } | |
1da177e4 LT |
313 | #ifdef CONFIG_HPET_TIMER |
314 | if (is_hpet_enabled()) | |
315 | hpet_reenable(); | |
316 | #endif | |
c3c433e4 | 317 | setup_pit_timer(); |
c7f40ff1 | 318 | |
7d145aa3 | 319 | sec = ctime + clock_cmos_diff; |
c7f40ff1 JS |
320 | ts.tv_sec = sec; |
321 | ts.tv_nsec = 0; | |
322 | do_settimeofday(&ts); | |
1da177e4 | 323 | write_seqlock_irqsave(&xtime_lock, flags); |
f7c09bd9 | 324 | jiffies_64 += sleep_length; |
f7c09bd9 | 325 | write_sequnlock_irqrestore(&xtime_lock, flags); |
8446f1d3 | 326 | touch_softlockup_watchdog(); |
1da177e4 LT |
327 | return 0; |
328 | } | |
329 | ||
330 | static struct sysdev_class timer_sysclass = { | |
331 | .resume = timer_resume, | |
332 | .suspend = timer_suspend, | |
333 | set_kset_name("timer"), | |
334 | }; | |
335 | ||
336 | ||
337 | /* XXX this driverfs stuff should probably go elsewhere later -john */ | |
338 | static struct sys_device device_timer = { | |
339 | .id = 0, | |
340 | .cls = &timer_sysclass, | |
341 | }; | |
342 | ||
343 | static int time_init_device(void) | |
344 | { | |
345 | int error = sysdev_class_register(&timer_sysclass); | |
346 | if (!error) | |
347 | error = sysdev_register(&device_timer); | |
348 | return error; | |
349 | } | |
350 | ||
351 | device_initcall(time_init_device); | |
352 | ||
f2b36db6 | 353 | #ifdef CONFIG_HPET_TIMER |
1e4c85f9 | 354 | extern void (*late_time_init)(void); |
1da177e4 LT |
355 | /* Duplicate of time_init() below, with hpet_enable part added */ |
356 | static void __init hpet_time_init(void) | |
357 | { | |
c7f40ff1 JS |
358 | struct timespec ts; |
359 | ts.tv_sec = get_cmos_time(); | |
360 | ts.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); | |
361 | ||
362 | do_settimeofday(&ts); | |
1da177e4 | 363 | |
35492df5 | 364 | if ((hpet_enable() >= 0) && hpet_use_timer) { |
1da177e4 LT |
365 | printk("Using HPET for base-timer\n"); |
366 | } | |
367 | ||
d3561b7f | 368 | do_time_init(); |
1da177e4 LT |
369 | } |
370 | #endif | |
371 | ||
372 | void __init time_init(void) | |
373 | { | |
c7f40ff1 | 374 | struct timespec ts; |
1da177e4 LT |
375 | #ifdef CONFIG_HPET_TIMER |
376 | if (is_hpet_capable()) { | |
377 | /* | |
378 | * HPET initialization needs to do memory-mapped io. So, let | |
379 | * us do a late initialization after mem_init(). | |
380 | */ | |
381 | late_time_init = hpet_time_init; | |
382 | return; | |
383 | } | |
384 | #endif | |
c7f40ff1 JS |
385 | ts.tv_sec = get_cmos_time(); |
386 | ts.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); | |
387 | ||
388 | do_settimeofday(&ts); | |
1da177e4 | 389 | |
d3561b7f | 390 | do_time_init(); |
1da177e4 | 391 | } |