[mirror_ubuntu-artful-kernel.git] / arch / i386 / oprofile / op_model_ppro.c

/**
 * @file op_model_ppro.h
 * pentium pro / P6 model-specific MSR operations
 *
 * @remark Copyright 2002 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon
 * @author Philippe Elie
 * @author Graydon Hoare
 */

#include <linux/oprofile.h>
#include <asm/ptrace.h>
#include <asm/msr.h>
#include <asm/apic.h>
#include <asm/nmi.h>
 
#include "op_x86_model.h"
#include "op_counter.h"

#define NUM_COUNTERS 2
#define NUM_CONTROLS 2

#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)
#define CTR_READ(l,h,msrs,c) do {rdmsr(msrs->counters[(c)].addr, (l), (h));} while (0)
#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), -1);} while (0)
#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))

#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
#define CTRL_READ(l,h,msrs,c) do {rdmsr((msrs->controls[(c)].addr), (l), (h));} while (0)
#define CTRL_WRITE(l,h,msrs,c) do {wrmsr((msrs->controls[(c)].addr), (l), (h));} while (0)
#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
#define CTRL_CLEAR(x) (x &= (1<<21))
#define CTRL_SET_ENABLE(val) (val |= 1<<20)
#define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16))
#define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17))
#define CTRL_SET_UM(val, m) (val |= (m << 8))
#define CTRL_SET_EVENT(val, e) (val |= e)

static unsigned long reset_value[NUM_COUNTERS];
 
static void ppro_fill_in_addresses(struct op_msrs * const msrs)
{
	int i;

	for (i=0; i < NUM_COUNTERS; i++) {
		if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
			msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
		else
			msrs->counters[i].addr = 0;
	}
	
	for (i=0; i < NUM_CONTROLS; i++) {
		if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
			msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
		else
			msrs->controls[i].addr = 0;
	}
}


static void ppro_setup_ctrs(struct op_msrs const * const msrs)
{
	unsigned int low, high;
	int i;

	/* clear all counters */
	for (i = 0 ; i < NUM_CONTROLS; ++i) {
		if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
			continue;
		CTRL_READ(low, high, msrs, i);
		CTRL_CLEAR(low);
		CTRL_WRITE(low, high, msrs, i);
	}
	
	/* avoid a false detection of ctr overflows in NMI handler */
	for (i = 0; i < NUM_COUNTERS; ++i) {
		if (unlikely(!CTR_IS_RESERVED(msrs,i)))
			continue;
		CTR_WRITE(1, msrs, i);
	}

	/* enable active counters */
	for (i = 0; i < NUM_COUNTERS; ++i) {
		if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs,i))) {
			reset_value[i] = counter_config[i].count;

			CTR_WRITE(counter_config[i].count, msrs, i);

			CTRL_READ(low, high, msrs, i);
			CTRL_CLEAR(low);
			CTRL_SET_ENABLE(low);
			CTRL_SET_USR(low, counter_config[i].user);
			CTRL_SET_KERN(low, counter_config[i].kernel);
			CTRL_SET_UM(low, counter_config[i].unit_mask);
			CTRL_SET_EVENT(low, counter_config[i].event);
			CTRL_WRITE(low, high, msrs, i);
		} else {
			reset_value[i] = 0;
		}
	}
}

 
static int ppro_check_ctrs(struct pt_regs * const regs,
			   struct op_msrs const * const msrs)
{
	unsigned int low, high;
	int i;
 
	for (i = 0 ; i < NUM_COUNTERS; ++i) {
		if (!reset_value[i])
			continue;
		CTR_READ(low, high, msrs, i);
		if (CTR_OVERFLOWED(low)) {
			oprofile_add_sample(regs, i);
			CTR_WRITE(reset_value[i], msrs, i);
		}
	}

	/* Only P6 based Pentium M need to re-unmask the apic vector but it
	 * doesn't hurt other P6 variant */
	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);

	/* We can't work out if we really handled an interrupt. We
	 * might have caught a *second* counter just after overflowing
	 * the interrupt for this counter then arrives
	 * and we don't find a counter that's overflowed, so we
	 * would return 0 and get dazed + confused. Instead we always
	 * assume we found an overflow. This sucks.
	 */
	return 1;
}

 
static void ppro_start(struct op_msrs const * const msrs)
{
	unsigned int low,high;

	if (reset_value[0]) {
		CTRL_READ(low, high, msrs, 0);
		CTRL_SET_ACTIVE(low);
		CTRL_WRITE(low, high, msrs, 0);
	}
}


static void ppro_stop(struct op_msrs const * const msrs)
{
	unsigned int low,high;

	if (reset_value[0]) {
		CTRL_READ(low, high, msrs, 0);
		CTRL_SET_INACTIVE(low);
		CTRL_WRITE(low, high, msrs, 0);
	}
}

static void ppro_shutdown(struct op_msrs const * const msrs)
{
	int i;

	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
		if (CTR_IS_RESERVED(msrs,i))
			release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
	}
	for (i = 0 ; i < NUM_CONTROLS ; ++i) {
		if (CTRL_IS_RESERVED(msrs,i))
			release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
	}
}


struct op_x86_model_spec const op_ppro_spec = {
	.num_counters = NUM_COUNTERS,
	.num_controls = NUM_CONTROLS,
	.fill_in_addresses = &ppro_fill_in_addresses,
	.setup_ctrs = &ppro_setup_ctrs,
	.check_ctrs = &ppro_check_ctrs,
	.start = &ppro_start,
	.stop = &ppro_stop,
	.shutdown = &ppro_shutdown
};
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file op_model_ppro.h
	3	* pentium pro / P6 model-specific MSR operations
	4	*
	5	* @remark Copyright 2002 OProfile authors
	6	* @remark Read the file COPYING
	7	*
	8	* @author John Levon
	9	* @author Philippe Elie
	10	* @author Graydon Hoare
	11	*/
	12
	13	#include <linux/oprofile.h>
	14	#include <asm/ptrace.h>
	15	#include <asm/msr.h>
	16	#include <asm/apic.h>
3e4ff115	17	#include <asm/nmi.h>
1da177e4 LT	18
	19	#include "op_x86_model.h"
	20	#include "op_counter.h"
	21
	22	#define NUM_COUNTERS 2
	23	#define NUM_CONTROLS 2
	24
cb9c448c	25	#define CTR_IS_RESERVED(msrs,c) (msrs->counters[(c)].addr ? 1 : 0)
1da177e4 LT	26	#define CTR_READ(l,h,msrs,c) do {rdmsr(msrs->counters[(c)].addr, (l), (h));} while (0)
	27	#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(u32)(l), -1);} while (0)
	28	#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
	29
cb9c448c	30	#define CTRL_IS_RESERVED(msrs,c) (msrs->controls[(c)].addr ? 1 : 0)
1da177e4 LT	31	#define CTRL_READ(l,h,msrs,c) do {rdmsr((msrs->controls[(c)].addr), (l), (h));} while (0)
	32	#define CTRL_WRITE(l,h,msrs,c) do {wrmsr((msrs->controls[(c)].addr), (l), (h));} while (0)
	33	#define CTRL_SET_ACTIVE(n) (n \|= (1<<22))
	34	#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
	35	#define CTRL_CLEAR(x) (x &= (1<<21))
	36	#define CTRL_SET_ENABLE(val) (val \|= 1<<20)
	37	#define CTRL_SET_USR(val,u) (val \|= ((u & 1) << 16))
	38	#define CTRL_SET_KERN(val,k) (val \|= ((k & 1) << 17))
	39	#define CTRL_SET_UM(val, m) (val \|= (m << 8))
	40	#define CTRL_SET_EVENT(val, e) (val \|= e)
	41
	42	static unsigned long reset_value[NUM_COUNTERS];
	43
	44	static void ppro_fill_in_addresses(struct op_msrs * const msrs)
	45	{
cb9c448c DZ	46	int i;
	47
	48	for (i=0; i < NUM_COUNTERS; i++) {
	49	if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
	50	msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
	51	else
	52	msrs->counters[i].addr = 0;
	53	}
1da177e4	54
cb9c448c DZ	55	for (i=0; i < NUM_CONTROLS; i++) {
	56	if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
	57	msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
	58	else
	59	msrs->controls[i].addr = 0;
	60	}
1da177e4 LT	61	}
	62
	63
	64	static void ppro_setup_ctrs(struct op_msrs const * const msrs)
	65	{
	66	unsigned int low, high;
	67	int i;
	68
	69	/* clear all counters */
	70	for (i = 0 ; i < NUM_CONTROLS; ++i) {
cb9c448c DZ	71	if (unlikely(!CTRL_IS_RESERVED(msrs,i)))
cb9c448c DZ	72	continue;
1da177e4 LT	73	CTRL_READ(low, high, msrs, i);
	74	CTRL_CLEAR(low);
	75	CTRL_WRITE(low, high, msrs, i);
	76	}
	77
	78	/* avoid a false detection of ctr overflows in NMI handler */
	79	for (i = 0; i < NUM_COUNTERS; ++i) {
cb9c448c DZ	80	if (unlikely(!CTR_IS_RESERVED(msrs,i)))
cb9c448c DZ	81	continue;
1da177e4 LT	82	CTR_WRITE(1, msrs, i);
	83	}
	84
	85	/* enable active counters */
	86	for (i = 0; i < NUM_COUNTERS; ++i) {
cb9c448c	87	if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs,i))) {
1da177e4 LT	88	reset_value[i] = counter_config[i].count;
	89
	90	CTR_WRITE(counter_config[i].count, msrs, i);
	91
	92	CTRL_READ(low, high, msrs, i);
	93	CTRL_CLEAR(low);
	94	CTRL_SET_ENABLE(low);
	95	CTRL_SET_USR(low, counter_config[i].user);
	96	CTRL_SET_KERN(low, counter_config[i].kernel);
	97	CTRL_SET_UM(low, counter_config[i].unit_mask);
	98	CTRL_SET_EVENT(low, counter_config[i].event);
	99	CTRL_WRITE(low, high, msrs, i);
cb9c448c DZ	100	} else {
cb9c448c DZ	101	reset_value[i] = 0;
1da177e4 LT	102	}
	103	}
	104	}
	105
	106
	107	static int ppro_check_ctrs(struct pt_regs * const regs,
	108	struct op_msrs const * const msrs)
	109	{
	110	unsigned int low, high;
	111	int i;
	112
	113	for (i = 0 ; i < NUM_COUNTERS; ++i) {
cb9c448c DZ	114	if (!reset_value[i])
cb9c448c DZ	115	continue;
1da177e4 LT	116	CTR_READ(low, high, msrs, i);
	117	if (CTR_OVERFLOWED(low)) {
	118	oprofile_add_sample(regs, i);
	119	CTR_WRITE(reset_value[i], msrs, i);
	120	}
	121	}
	122
	123	/* Only P6 based Pentium M need to re-unmask the apic vector but it
	124	* doesn't hurt other P6 variant */
	125	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
	126
	127	/* We can't work out if we really handled an interrupt. We
	128	* might have caught a second counter just after overflowing
	129	* the interrupt for this counter then arrives
	130	* and we don't find a counter that's overflowed, so we
	131	* would return 0 and get dazed + confused. Instead we always
	132	* assume we found an overflow. This sucks.
	133	*/
	134	return 1;
	135	}
	136
	137
	138	static void ppro_start(struct op_msrs const * const msrs)
	139	{
	140	unsigned int low,high;
cb9c448c DZ	141
	142	if (reset_value[0]) {
	143	CTRL_READ(low, high, msrs, 0);
	144	CTRL_SET_ACTIVE(low);
	145	CTRL_WRITE(low, high, msrs, 0);
	146	}
1da177e4 LT	147	}
	148
	149
	150	static void ppro_stop(struct op_msrs const * const msrs)
	151	{
	152	unsigned int low,high;
cb9c448c DZ	153
	154	if (reset_value[0]) {
	155	CTRL_READ(low, high, msrs, 0);
	156	CTRL_SET_INACTIVE(low);
	157	CTRL_WRITE(low, high, msrs, 0);
	158	}
	159	}
	160
	161	static void ppro_shutdown(struct op_msrs const * const msrs)
	162	{
	163	int i;
	164
	165	for (i = 0 ; i < NUM_COUNTERS ; ++i) {
	166	if (CTR_IS_RESERVED(msrs,i))
	167	release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
	168	}
	169	for (i = 0 ; i < NUM_CONTROLS ; ++i) {
	170	if (CTRL_IS_RESERVED(msrs,i))
	171	release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
	172	}
1da177e4 LT	173	}
	174
	175
	176	struct op_x86_model_spec const op_ppro_spec = {
	177	.num_counters = NUM_COUNTERS,
	178	.num_controls = NUM_CONTROLS,
	179	.fill_in_addresses = &ppro_fill_in_addresses,
	180	.setup_ctrs = &ppro_setup_ctrs,
	181	.check_ctrs = &ppro_check_ctrs,
	182	.start = &ppro_start,
cb9c448c DZ	183	.stop = &ppro_stop,
cb9c448c DZ	184	.shutdown = &ppro_shutdown
1da177e4	185	};