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1da177e4 LT |
1 | /* |
2 | ** IA64 System Bus Adapter (SBA) I/O MMU manager | |
3 | ** | |
5f6602a1 | 4 | ** (c) Copyright 2002-2005 Alex Williamson |
1da177e4 | 5 | ** (c) Copyright 2002-2003 Grant Grundler |
5f6602a1 | 6 | ** (c) Copyright 2002-2005 Hewlett-Packard Company |
1da177e4 LT |
7 | ** |
8 | ** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code) | |
9 | ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) | |
10 | ** | |
11 | ** This program is free software; you can redistribute it and/or modify | |
12 | ** it under the terms of the GNU General Public License as published by | |
13 | ** the Free Software Foundation; either version 2 of the License, or | |
14 | ** (at your option) any later version. | |
15 | ** | |
16 | ** | |
17 | ** This module initializes the IOC (I/O Controller) found on HP | |
18 | ** McKinley machines and their successors. | |
19 | ** | |
20 | */ | |
21 | ||
1da177e4 LT |
22 | #include <linux/types.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/proc_fs.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/acpi.h> | |
34 | #include <linux/efi.h> | |
35 | #include <linux/nodemask.h> | |
36 | #include <linux/bitops.h> /* hweight64() */ | |
51b58e3e | 37 | #include <linux/crash_dump.h> |
b34eb53c | 38 | #include <linux/iommu-helper.h> |
0e9cbb9b | 39 | #include <linux/dma-mapping.h> |
1da177e4 LT |
40 | |
41 | #include <asm/delay.h> /* ia64_get_itc() */ | |
42 | #include <asm/io.h> | |
43 | #include <asm/page.h> /* PAGE_OFFSET */ | |
44 | #include <asm/dma.h> | |
45 | #include <asm/system.h> /* wmb() */ | |
46 | ||
47 | #include <asm/acpi-ext.h> | |
48 | ||
51b58e3e TL |
49 | extern int swiotlb_late_init_with_default_size (size_t size); |
50 | ||
1da177e4 LT |
51 | #define PFX "IOC: " |
52 | ||
53 | /* | |
54 | ** Enabling timing search of the pdir resource map. Output in /proc. | |
55 | ** Disabled by default to optimize performance. | |
56 | */ | |
57 | #undef PDIR_SEARCH_TIMING | |
58 | ||
59 | /* | |
60 | ** This option allows cards capable of 64bit DMA to bypass the IOMMU. If | |
61 | ** not defined, all DMA will be 32bit and go through the TLB. | |
62 | ** There's potentially a conflict in the bio merge code with us | |
63 | ** advertising an iommu, but then bypassing it. Since I/O MMU bypassing | |
64 | ** appears to give more performance than bio-level virtual merging, we'll | |
65 | ** do the former for now. NOTE: BYPASS_SG also needs to be undef'd to | |
66 | ** completely restrict DMA to the IOMMU. | |
67 | */ | |
68 | #define ALLOW_IOV_BYPASS | |
69 | ||
70 | /* | |
71 | ** This option specifically allows/disallows bypassing scatterlists with | |
72 | ** multiple entries. Coalescing these entries can allow better DMA streaming | |
73 | ** and in some cases shows better performance than entirely bypassing the | |
74 | ** IOMMU. Performance increase on the order of 1-2% sequential output/input | |
75 | ** using bonnie++ on a RAID0 MD device (sym2 & mpt). | |
76 | */ | |
77 | #undef ALLOW_IOV_BYPASS_SG | |
78 | ||
79 | /* | |
80 | ** If a device prefetches beyond the end of a valid pdir entry, it will cause | |
81 | ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should | |
82 | ** disconnect on 4k boundaries and prevent such issues. If the device is | |
0779bf2d | 83 | ** particularly aggressive, this option will keep the entire pdir valid such |
1da177e4 LT |
84 | ** that prefetching will hit a valid address. This could severely impact |
85 | ** error containment, and is therefore off by default. The page that is | |
86 | ** used for spill-over is poisoned, so that should help debugging somewhat. | |
87 | */ | |
88 | #undef FULL_VALID_PDIR | |
89 | ||
90 | #define ENABLE_MARK_CLEAN | |
91 | ||
92 | /* | |
93 | ** The number of debug flags is a clue - this code is fragile. NOTE: since | |
94 | ** tightening the use of res_lock the resource bitmap and actual pdir are no | |
95 | ** longer guaranteed to stay in sync. The sanity checking code isn't going to | |
96 | ** like that. | |
97 | */ | |
98 | #undef DEBUG_SBA_INIT | |
99 | #undef DEBUG_SBA_RUN | |
100 | #undef DEBUG_SBA_RUN_SG | |
101 | #undef DEBUG_SBA_RESOURCE | |
102 | #undef ASSERT_PDIR_SANITY | |
103 | #undef DEBUG_LARGE_SG_ENTRIES | |
104 | #undef DEBUG_BYPASS | |
105 | ||
106 | #if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY) | |
107 | #error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive | |
108 | #endif | |
109 | ||
110 | #define SBA_INLINE __inline__ | |
111 | /* #define SBA_INLINE */ | |
112 | ||
113 | #ifdef DEBUG_SBA_INIT | |
114 | #define DBG_INIT(x...) printk(x) | |
115 | #else | |
116 | #define DBG_INIT(x...) | |
117 | #endif | |
118 | ||
119 | #ifdef DEBUG_SBA_RUN | |
120 | #define DBG_RUN(x...) printk(x) | |
121 | #else | |
122 | #define DBG_RUN(x...) | |
123 | #endif | |
124 | ||
125 | #ifdef DEBUG_SBA_RUN_SG | |
126 | #define DBG_RUN_SG(x...) printk(x) | |
127 | #else | |
128 | #define DBG_RUN_SG(x...) | |
129 | #endif | |
130 | ||
131 | ||
132 | #ifdef DEBUG_SBA_RESOURCE | |
133 | #define DBG_RES(x...) printk(x) | |
134 | #else | |
135 | #define DBG_RES(x...) | |
136 | #endif | |
137 | ||
138 | #ifdef DEBUG_BYPASS | |
139 | #define DBG_BYPASS(x...) printk(x) | |
140 | #else | |
141 | #define DBG_BYPASS(x...) | |
142 | #endif | |
143 | ||
144 | #ifdef ASSERT_PDIR_SANITY | |
145 | #define ASSERT(expr) \ | |
146 | if(!(expr)) { \ | |
147 | printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \ | |
148 | panic(#expr); \ | |
149 | } | |
150 | #else | |
151 | #define ASSERT(expr) | |
152 | #endif | |
153 | ||
154 | /* | |
155 | ** The number of pdir entries to "free" before issuing | |
156 | ** a read to PCOM register to flush out PCOM writes. | |
157 | ** Interacts with allocation granularity (ie 4 or 8 entries | |
158 | ** allocated and free'd/purged at a time might make this | |
159 | ** less interesting). | |
160 | */ | |
161 | #define DELAYED_RESOURCE_CNT 64 | |
162 | ||
e15da401 BH |
163 | #define PCI_DEVICE_ID_HP_SX2000_IOC 0x12ec |
164 | ||
1da177e4 LT |
165 | #define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP) |
166 | #define ZX2_IOC_ID ((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP) | |
167 | #define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP) | |
168 | #define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP) | |
e15da401 | 169 | #define SX2000_IOC_ID ((PCI_DEVICE_ID_HP_SX2000_IOC << 16) | PCI_VENDOR_ID_HP) |
1da177e4 LT |
170 | |
171 | #define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ | |
172 | ||
173 | #define IOC_FUNC_ID 0x000 | |
174 | #define IOC_FCLASS 0x008 /* function class, bist, header, rev... */ | |
175 | #define IOC_IBASE 0x300 /* IO TLB */ | |
176 | #define IOC_IMASK 0x308 | |
177 | #define IOC_PCOM 0x310 | |
178 | #define IOC_TCNFG 0x318 | |
179 | #define IOC_PDIR_BASE 0x320 | |
180 | ||
181 | #define IOC_ROPE0_CFG 0x500 | |
182 | #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */ | |
183 | ||
184 | ||
185 | /* AGP GART driver looks for this */ | |
186 | #define ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL | |
187 | ||
188 | /* | |
189 | ** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register) | |
190 | ** | |
191 | ** Some IOCs (sx1000) can run at the above pages sizes, but are | |
192 | ** really only supported using the IOC at a 4k page size. | |
193 | ** | |
194 | ** iovp_size could only be greater than PAGE_SIZE if we are | |
195 | ** confident the drivers really only touch the next physical | |
196 | ** page iff that driver instance owns it. | |
197 | */ | |
198 | static unsigned long iovp_size; | |
199 | static unsigned long iovp_shift; | |
200 | static unsigned long iovp_mask; | |
201 | ||
202 | struct ioc { | |
203 | void __iomem *ioc_hpa; /* I/O MMU base address */ | |
204 | char *res_map; /* resource map, bit == pdir entry */ | |
205 | u64 *pdir_base; /* physical base address */ | |
206 | unsigned long ibase; /* pdir IOV Space base */ | |
207 | unsigned long imask; /* pdir IOV Space mask */ | |
208 | ||
209 | unsigned long *res_hint; /* next avail IOVP - circular search */ | |
210 | unsigned long dma_mask; | |
211 | spinlock_t res_lock; /* protects the resource bitmap, but must be held when */ | |
212 | /* clearing pdir to prevent races with allocations. */ | |
213 | unsigned int res_bitshift; /* from the RIGHT! */ | |
214 | unsigned int res_size; /* size of resource map in bytes */ | |
215 | #ifdef CONFIG_NUMA | |
216 | unsigned int node; /* node where this IOC lives */ | |
217 | #endif | |
218 | #if DELAYED_RESOURCE_CNT > 0 | |
219 | spinlock_t saved_lock; /* may want to try to get this on a separate cacheline */ | |
220 | /* than res_lock for bigger systems. */ | |
221 | int saved_cnt; | |
222 | struct sba_dma_pair { | |
223 | dma_addr_t iova; | |
224 | size_t size; | |
225 | } saved[DELAYED_RESOURCE_CNT]; | |
226 | #endif | |
227 | ||
228 | #ifdef PDIR_SEARCH_TIMING | |
229 | #define SBA_SEARCH_SAMPLE 0x100 | |
230 | unsigned long avg_search[SBA_SEARCH_SAMPLE]; | |
231 | unsigned long avg_idx; /* current index into avg_search */ | |
232 | #endif | |
233 | ||
234 | /* Stuff we don't need in performance path */ | |
235 | struct ioc *next; /* list of IOC's in system */ | |
236 | acpi_handle handle; /* for multiple IOC's */ | |
237 | const char *name; | |
238 | unsigned int func_id; | |
239 | unsigned int rev; /* HW revision of chip */ | |
240 | u32 iov_size; | |
241 | unsigned int pdir_size; /* in bytes, determined by IOV Space size */ | |
242 | struct pci_dev *sac_only_dev; | |
243 | }; | |
244 | ||
245 | static struct ioc *ioc_list; | |
246 | static int reserve_sba_gart = 1; | |
247 | ||
248 | static SBA_INLINE void sba_mark_invalid(struct ioc *, dma_addr_t, size_t); | |
249 | static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t); | |
250 | ||
58b053e4 | 251 | #define sba_sg_address(sg) sg_virt((sg)) |
1da177e4 LT |
252 | |
253 | #ifdef FULL_VALID_PDIR | |
254 | static u64 prefetch_spill_page; | |
255 | #endif | |
256 | ||
257 | #ifdef CONFIG_PCI | |
258 | # define GET_IOC(dev) (((dev)->bus == &pci_bus_type) \ | |
259 | ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL) | |
260 | #else | |
261 | # define GET_IOC(dev) NULL | |
262 | #endif | |
263 | ||
264 | /* | |
265 | ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up | |
0779bf2d | 266 | ** (or rather not merge) DMAs into manageable chunks. |
1da177e4 | 267 | ** On parisc, this is more of the software/tuning constraint |
0779bf2d ML |
268 | ** rather than the HW. I/O MMU allocation algorithms can be |
269 | ** faster with smaller sizes (to some degree). | |
1da177e4 LT |
270 | */ |
271 | #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size) | |
272 | ||
273 | #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1)) | |
274 | ||
275 | /************************************ | |
276 | ** SBA register read and write support | |
277 | ** | |
278 | ** BE WARNED: register writes are posted. | |
279 | ** (ie follow writes which must reach HW with a read) | |
280 | ** | |
281 | */ | |
282 | #define READ_REG(addr) __raw_readq(addr) | |
283 | #define WRITE_REG(val, addr) __raw_writeq(val, addr) | |
284 | ||
285 | #ifdef DEBUG_SBA_INIT | |
286 | ||
287 | /** | |
288 | * sba_dump_tlb - debugging only - print IOMMU operating parameters | |
289 | * @hpa: base address of the IOMMU | |
290 | * | |
291 | * Print the size/location of the IO MMU PDIR. | |
292 | */ | |
293 | static void | |
294 | sba_dump_tlb(char *hpa) | |
295 | { | |
296 | DBG_INIT("IO TLB at 0x%p\n", (void *)hpa); | |
297 | DBG_INIT("IOC_IBASE : %016lx\n", READ_REG(hpa+IOC_IBASE)); | |
298 | DBG_INIT("IOC_IMASK : %016lx\n", READ_REG(hpa+IOC_IMASK)); | |
299 | DBG_INIT("IOC_TCNFG : %016lx\n", READ_REG(hpa+IOC_TCNFG)); | |
300 | DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE)); | |
301 | DBG_INIT("\n"); | |
302 | } | |
303 | #endif | |
304 | ||
305 | ||
306 | #ifdef ASSERT_PDIR_SANITY | |
307 | ||
308 | /** | |
309 | * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry | |
310 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
311 | * @msg: text to print ont the output line. | |
312 | * @pide: pdir index. | |
313 | * | |
314 | * Print one entry of the IO MMU PDIR in human readable form. | |
315 | */ | |
316 | static void | |
317 | sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) | |
318 | { | |
319 | /* start printing from lowest pde in rval */ | |
320 | u64 *ptr = &ioc->pdir_base[pide & ~(BITS_PER_LONG - 1)]; | |
321 | unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)]; | |
322 | uint rcnt; | |
323 | ||
324 | printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", | |
325 | msg, rptr, pide & (BITS_PER_LONG - 1), *rptr); | |
326 | ||
327 | rcnt = 0; | |
328 | while (rcnt < BITS_PER_LONG) { | |
329 | printk(KERN_DEBUG "%s %2d %p %016Lx\n", | |
330 | (rcnt == (pide & (BITS_PER_LONG - 1))) | |
331 | ? " -->" : " ", | |
332 | rcnt, ptr, (unsigned long long) *ptr ); | |
333 | rcnt++; | |
334 | ptr++; | |
335 | } | |
336 | printk(KERN_DEBUG "%s", msg); | |
337 | } | |
338 | ||
339 | ||
340 | /** | |
341 | * sba_check_pdir - debugging only - consistency checker | |
342 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
343 | * @msg: text to print ont the output line. | |
344 | * | |
345 | * Verify the resource map and pdir state is consistent | |
346 | */ | |
347 | static int | |
348 | sba_check_pdir(struct ioc *ioc, char *msg) | |
349 | { | |
350 | u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]); | |
351 | u64 *rptr = (u64 *) ioc->res_map; /* resource map ptr */ | |
352 | u64 *pptr = ioc->pdir_base; /* pdir ptr */ | |
353 | uint pide = 0; | |
354 | ||
355 | while (rptr < rptr_end) { | |
356 | u64 rval; | |
357 | int rcnt; /* number of bits we might check */ | |
358 | ||
359 | rval = *rptr; | |
360 | rcnt = 64; | |
361 | ||
362 | while (rcnt) { | |
363 | /* Get last byte and highest bit from that */ | |
364 | u32 pde = ((u32)((*pptr >> (63)) & 0x1)); | |
365 | if ((rval & 0x1) ^ pde) | |
366 | { | |
367 | /* | |
368 | ** BUMMER! -- res_map != pdir -- | |
369 | ** Dump rval and matching pdir entries | |
370 | */ | |
371 | sba_dump_pdir_entry(ioc, msg, pide); | |
372 | return(1); | |
373 | } | |
374 | rcnt--; | |
375 | rval >>= 1; /* try the next bit */ | |
376 | pptr++; | |
377 | pide++; | |
378 | } | |
379 | rptr++; /* look at next word of res_map */ | |
380 | } | |
381 | /* It'd be nice if we always got here :^) */ | |
382 | return 0; | |
383 | } | |
384 | ||
385 | ||
386 | /** | |
387 | * sba_dump_sg - debugging only - print Scatter-Gather list | |
388 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
389 | * @startsg: head of the SG list | |
390 | * @nents: number of entries in SG list | |
391 | * | |
392 | * print the SG list so we can verify it's correct by hand. | |
393 | */ | |
394 | static void | |
395 | sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) | |
396 | { | |
397 | while (nents-- > 0) { | |
398 | printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents, | |
399 | startsg->dma_address, startsg->dma_length, | |
400 | sba_sg_address(startsg)); | |
9b6eccfc | 401 | startsg = sg_next(startsg); |
1da177e4 LT |
402 | } |
403 | } | |
404 | ||
405 | static void | |
406 | sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) | |
407 | { | |
408 | struct scatterlist *the_sg = startsg; | |
409 | int the_nents = nents; | |
410 | ||
411 | while (the_nents-- > 0) { | |
412 | if (sba_sg_address(the_sg) == 0x0UL) | |
413 | sba_dump_sg(NULL, startsg, nents); | |
9b6eccfc | 414 | the_sg = sg_next(the_sg); |
1da177e4 LT |
415 | } |
416 | } | |
417 | ||
418 | #endif /* ASSERT_PDIR_SANITY */ | |
419 | ||
420 | ||
421 | ||
422 | ||
423 | /************************************************************** | |
424 | * | |
425 | * I/O Pdir Resource Management | |
426 | * | |
427 | * Bits set in the resource map are in use. | |
428 | * Each bit can represent a number of pages. | |
429 | * LSbs represent lower addresses (IOVA's). | |
430 | * | |
431 | ***************************************************************/ | |
432 | #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ | |
433 | ||
434 | /* Convert from IOVP to IOVA and vice versa. */ | |
435 | #define SBA_IOVA(ioc,iovp,offset) ((ioc->ibase) | (iovp) | (offset)) | |
436 | #define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase)) | |
437 | ||
438 | #define PDIR_ENTRY_SIZE sizeof(u64) | |
439 | ||
440 | #define PDIR_INDEX(iovp) ((iovp)>>iovp_shift) | |
441 | ||
442 | #define RESMAP_MASK(n) ~(~0UL << (n)) | |
443 | #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) | |
444 | ||
445 | ||
446 | /** | |
447 | * For most cases the normal get_order is sufficient, however it limits us | |
448 | * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity. | |
449 | * It only incurs about 1 clock cycle to use this one with the static variable | |
450 | * and makes the code more intuitive. | |
451 | */ | |
452 | static SBA_INLINE int | |
453 | get_iovp_order (unsigned long size) | |
454 | { | |
455 | long double d = size - 1; | |
456 | long order; | |
457 | ||
458 | order = ia64_getf_exp(d); | |
459 | order = order - iovp_shift - 0xffff + 1; | |
460 | if (order < 0) | |
461 | order = 0; | |
462 | return order; | |
463 | } | |
464 | ||
b34eb53c FT |
465 | static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr, |
466 | unsigned int bitshiftcnt) | |
467 | { | |
468 | return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3) | |
469 | + bitshiftcnt; | |
470 | } | |
471 | ||
1da177e4 LT |
472 | /** |
473 | * sba_search_bitmap - find free space in IO PDIR resource bitmap | |
474 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
475 | * @bits_wanted: number of entries we need. | |
5f6602a1 | 476 | * @use_hint: use res_hint to indicate where to start looking |
1da177e4 LT |
477 | * |
478 | * Find consecutive free bits in resource bitmap. | |
479 | * Each bit represents one entry in the IO Pdir. | |
480 | * Cool perf optimization: search for log2(size) bits at a time. | |
481 | */ | |
482 | static SBA_INLINE unsigned long | |
b34eb53c FT |
483 | sba_search_bitmap(struct ioc *ioc, struct device *dev, |
484 | unsigned long bits_wanted, int use_hint) | |
1da177e4 | 485 | { |
5f6602a1 | 486 | unsigned long *res_ptr; |
1da177e4 | 487 | unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); |
b34eb53c FT |
488 | unsigned long flags, pide = ~0UL, tpide; |
489 | unsigned long boundary_size; | |
490 | unsigned long shift; | |
491 | int ret; | |
1da177e4 LT |
492 | |
493 | ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0); | |
494 | ASSERT(res_ptr < res_end); | |
495 | ||
b34eb53c FT |
496 | boundary_size = (unsigned long long)dma_get_seg_boundary(dev) + 1; |
497 | boundary_size = ALIGN(boundary_size, 1ULL << iovp_shift) >> iovp_shift; | |
498 | ||
499 | BUG_ON(ioc->ibase & ~iovp_mask); | |
500 | shift = ioc->ibase >> iovp_shift; | |
501 | ||
5f6602a1 AW |
502 | spin_lock_irqsave(&ioc->res_lock, flags); |
503 | ||
504 | /* Allow caller to force a search through the entire resource space */ | |
505 | if (likely(use_hint)) { | |
506 | res_ptr = ioc->res_hint; | |
507 | } else { | |
508 | res_ptr = (ulong *)ioc->res_map; | |
509 | ioc->res_bitshift = 0; | |
510 | } | |
511 | ||
1da177e4 LT |
512 | /* |
513 | * N.B. REO/Grande defect AR2305 can cause TLB fetch timeouts | |
514 | * if a TLB entry is purged while in use. sba_mark_invalid() | |
515 | * purges IOTLB entries in power-of-two sizes, so we also | |
516 | * allocate IOVA space in power-of-two sizes. | |
517 | */ | |
518 | bits_wanted = 1UL << get_iovp_order(bits_wanted << iovp_shift); | |
519 | ||
520 | if (likely(bits_wanted == 1)) { | |
521 | unsigned int bitshiftcnt; | |
522 | for(; res_ptr < res_end ; res_ptr++) { | |
523 | if (likely(*res_ptr != ~0UL)) { | |
524 | bitshiftcnt = ffz(*res_ptr); | |
525 | *res_ptr |= (1UL << bitshiftcnt); | |
b34eb53c | 526 | pide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); |
1da177e4 LT |
527 | ioc->res_bitshift = bitshiftcnt + bits_wanted; |
528 | goto found_it; | |
529 | } | |
530 | } | |
531 | goto not_found; | |
532 | ||
533 | } | |
534 | ||
535 | if (likely(bits_wanted <= BITS_PER_LONG/2)) { | |
536 | /* | |
537 | ** Search the resource bit map on well-aligned values. | |
538 | ** "o" is the alignment. | |
539 | ** We need the alignment to invalidate I/O TLB using | |
540 | ** SBA HW features in the unmap path. | |
541 | */ | |
542 | unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift); | |
543 | uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o); | |
544 | unsigned long mask, base_mask; | |
545 | ||
546 | base_mask = RESMAP_MASK(bits_wanted); | |
547 | mask = base_mask << bitshiftcnt; | |
548 | ||
d4ed8084 | 549 | DBG_RES("%s() o %ld %p", __func__, o, res_ptr); |
1da177e4 LT |
550 | for(; res_ptr < res_end ; res_ptr++) |
551 | { | |
552 | DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); | |
553 | ASSERT(0 != mask); | |
554 | for (; mask ; mask <<= o, bitshiftcnt += o) { | |
b34eb53c FT |
555 | tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt); |
556 | ret = iommu_is_span_boundary(tpide, bits_wanted, | |
557 | shift, | |
558 | boundary_size); | |
559 | if ((0 == ((*res_ptr) & mask)) && !ret) { | |
1da177e4 | 560 | *res_ptr |= mask; /* mark resources busy! */ |
b34eb53c | 561 | pide = tpide; |
1da177e4 LT |
562 | ioc->res_bitshift = bitshiftcnt + bits_wanted; |
563 | goto found_it; | |
564 | } | |
565 | } | |
566 | ||
567 | bitshiftcnt = 0; | |
568 | mask = base_mask; | |
569 | ||
570 | } | |
571 | ||
572 | } else { | |
573 | int qwords, bits, i; | |
574 | unsigned long *end; | |
575 | ||
576 | qwords = bits_wanted >> 6; /* /64 */ | |
577 | bits = bits_wanted - (qwords * BITS_PER_LONG); | |
578 | ||
579 | end = res_end - qwords; | |
580 | ||
581 | for (; res_ptr < end; res_ptr++) { | |
b34eb53c FT |
582 | tpide = ptr_to_pide(ioc, res_ptr, 0); |
583 | ret = iommu_is_span_boundary(tpide, bits_wanted, | |
584 | shift, boundary_size); | |
585 | if (ret) | |
586 | goto next_ptr; | |
1da177e4 LT |
587 | for (i = 0 ; i < qwords ; i++) { |
588 | if (res_ptr[i] != 0) | |
589 | goto next_ptr; | |
590 | } | |
591 | if (bits && res_ptr[i] && (__ffs(res_ptr[i]) < bits)) | |
592 | continue; | |
593 | ||
594 | /* Found it, mark it */ | |
595 | for (i = 0 ; i < qwords ; i++) | |
596 | res_ptr[i] = ~0UL; | |
597 | res_ptr[i] |= RESMAP_MASK(bits); | |
598 | ||
b34eb53c | 599 | pide = tpide; |
1da177e4 LT |
600 | res_ptr += qwords; |
601 | ioc->res_bitshift = bits; | |
602 | goto found_it; | |
603 | next_ptr: | |
604 | ; | |
605 | } | |
606 | } | |
607 | ||
608 | not_found: | |
609 | prefetch(ioc->res_map); | |
610 | ioc->res_hint = (unsigned long *) ioc->res_map; | |
611 | ioc->res_bitshift = 0; | |
5f6602a1 | 612 | spin_unlock_irqrestore(&ioc->res_lock, flags); |
1da177e4 LT |
613 | return (pide); |
614 | ||
615 | found_it: | |
616 | ioc->res_hint = res_ptr; | |
5f6602a1 | 617 | spin_unlock_irqrestore(&ioc->res_lock, flags); |
1da177e4 LT |
618 | return (pide); |
619 | } | |
620 | ||
621 | ||
622 | /** | |
623 | * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap | |
624 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
625 | * @size: number of bytes to create a mapping for | |
626 | * | |
627 | * Given a size, find consecutive unmarked and then mark those bits in the | |
628 | * resource bit map. | |
629 | */ | |
630 | static int | |
b34eb53c | 631 | sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) |
1da177e4 LT |
632 | { |
633 | unsigned int pages_needed = size >> iovp_shift; | |
634 | #ifdef PDIR_SEARCH_TIMING | |
635 | unsigned long itc_start; | |
636 | #endif | |
637 | unsigned long pide; | |
1da177e4 LT |
638 | |
639 | ASSERT(pages_needed); | |
640 | ASSERT(0 == (size & ~iovp_mask)); | |
641 | ||
1da177e4 LT |
642 | #ifdef PDIR_SEARCH_TIMING |
643 | itc_start = ia64_get_itc(); | |
644 | #endif | |
645 | /* | |
646 | ** "seek and ye shall find"...praying never hurts either... | |
647 | */ | |
b34eb53c | 648 | pide = sba_search_bitmap(ioc, dev, pages_needed, 1); |
1da177e4 | 649 | if (unlikely(pide >= (ioc->res_size << 3))) { |
b34eb53c | 650 | pide = sba_search_bitmap(ioc, dev, pages_needed, 0); |
1da177e4 LT |
651 | if (unlikely(pide >= (ioc->res_size << 3))) { |
652 | #if DELAYED_RESOURCE_CNT > 0 | |
5f6602a1 AW |
653 | unsigned long flags; |
654 | ||
1da177e4 LT |
655 | /* |
656 | ** With delayed resource freeing, we can give this one more shot. We're | |
657 | ** getting close to being in trouble here, so do what we can to make this | |
658 | ** one count. | |
659 | */ | |
5f6602a1 | 660 | spin_lock_irqsave(&ioc->saved_lock, flags); |
1da177e4 LT |
661 | if (ioc->saved_cnt > 0) { |
662 | struct sba_dma_pair *d; | |
663 | int cnt = ioc->saved_cnt; | |
664 | ||
5f6602a1 | 665 | d = &(ioc->saved[ioc->saved_cnt - 1]); |
1da177e4 | 666 | |
5f6602a1 | 667 | spin_lock(&ioc->res_lock); |
1da177e4 LT |
668 | while (cnt--) { |
669 | sba_mark_invalid(ioc, d->iova, d->size); | |
670 | sba_free_range(ioc, d->iova, d->size); | |
671 | d--; | |
672 | } | |
673 | ioc->saved_cnt = 0; | |
674 | READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ | |
5f6602a1 | 675 | spin_unlock(&ioc->res_lock); |
1da177e4 | 676 | } |
5f6602a1 | 677 | spin_unlock_irqrestore(&ioc->saved_lock, flags); |
1da177e4 | 678 | |
b34eb53c | 679 | pide = sba_search_bitmap(ioc, dev, pages_needed, 0); |
1da177e4 LT |
680 | if (unlikely(pide >= (ioc->res_size << 3))) |
681 | panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n", | |
682 | ioc->ioc_hpa); | |
683 | #else | |
684 | panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n", | |
685 | ioc->ioc_hpa); | |
686 | #endif | |
687 | } | |
688 | } | |
689 | ||
690 | #ifdef PDIR_SEARCH_TIMING | |
691 | ioc->avg_search[ioc->avg_idx++] = (ia64_get_itc() - itc_start) / pages_needed; | |
692 | ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; | |
693 | #endif | |
694 | ||
695 | prefetchw(&(ioc->pdir_base[pide])); | |
696 | ||
697 | #ifdef ASSERT_PDIR_SANITY | |
698 | /* verify the first enable bit is clear */ | |
699 | if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) { | |
700 | sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); | |
701 | } | |
702 | #endif | |
703 | ||
704 | DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", | |
d4ed8084 | 705 | __func__, size, pages_needed, pide, |
1da177e4 LT |
706 | (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), |
707 | ioc->res_bitshift ); | |
708 | ||
1da177e4 LT |
709 | return (pide); |
710 | } | |
711 | ||
712 | ||
713 | /** | |
714 | * sba_free_range - unmark bits in IO PDIR resource bitmap | |
715 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
716 | * @iova: IO virtual address which was previously allocated. | |
717 | * @size: number of bytes to create a mapping for | |
718 | * | |
719 | * clear bits in the ioc's resource map | |
720 | */ | |
721 | static SBA_INLINE void | |
722 | sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) | |
723 | { | |
724 | unsigned long iovp = SBA_IOVP(ioc, iova); | |
725 | unsigned int pide = PDIR_INDEX(iovp); | |
726 | unsigned int ridx = pide >> 3; /* convert bit to byte address */ | |
727 | unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); | |
728 | int bits_not_wanted = size >> iovp_shift; | |
729 | unsigned long m; | |
730 | ||
731 | /* Round up to power-of-two size: see AR2305 note above */ | |
732 | bits_not_wanted = 1UL << get_iovp_order(bits_not_wanted << iovp_shift); | |
733 | for (; bits_not_wanted > 0 ; res_ptr++) { | |
734 | ||
735 | if (unlikely(bits_not_wanted > BITS_PER_LONG)) { | |
736 | ||
737 | /* these mappings start 64bit aligned */ | |
738 | *res_ptr = 0UL; | |
739 | bits_not_wanted -= BITS_PER_LONG; | |
740 | pide += BITS_PER_LONG; | |
741 | ||
742 | } else { | |
743 | ||
744 | /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ | |
745 | m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1)); | |
746 | bits_not_wanted = 0; | |
747 | ||
d4ed8084 HH |
748 | DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", __func__, (uint) iova, size, |
749 | bits_not_wanted, m, pide, res_ptr, *res_ptr); | |
1da177e4 LT |
750 | |
751 | ASSERT(m != 0); | |
752 | ASSERT(bits_not_wanted); | |
753 | ASSERT((*res_ptr & m) == m); /* verify same bits are set */ | |
754 | *res_ptr &= ~m; | |
755 | } | |
756 | } | |
757 | } | |
758 | ||
759 | ||
760 | /************************************************************** | |
761 | * | |
762 | * "Dynamic DMA Mapping" support (aka "Coherent I/O") | |
763 | * | |
764 | ***************************************************************/ | |
765 | ||
766 | /** | |
767 | * sba_io_pdir_entry - fill in one IO PDIR entry | |
768 | * @pdir_ptr: pointer to IO PDIR entry | |
769 | * @vba: Virtual CPU address of buffer to map | |
770 | * | |
771 | * SBA Mapping Routine | |
772 | * | |
773 | * Given a virtual address (vba, arg1) sba_io_pdir_entry() | |
774 | * loads the I/O PDIR entry pointed to by pdir_ptr (arg0). | |
775 | * Each IO Pdir entry consists of 8 bytes as shown below | |
776 | * (LSB == bit 0): | |
777 | * | |
778 | * 63 40 11 7 0 | |
779 | * +-+---------------------+----------------------------------+----+--------+ | |
780 | * |V| U | PPN[39:12] | U | FF | | |
781 | * +-+---------------------+----------------------------------+----+--------+ | |
782 | * | |
783 | * V == Valid Bit | |
784 | * U == Unused | |
785 | * PPN == Physical Page Number | |
786 | * | |
787 | * The physical address fields are filled with the results of virt_to_phys() | |
788 | * on the vba. | |
789 | */ | |
790 | ||
791 | #if 1 | |
792 | #define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL) \ | |
793 | | 0x8000000000000000ULL) | |
794 | #else | |
795 | void SBA_INLINE | |
796 | sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba) | |
797 | { | |
798 | *pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL); | |
799 | } | |
800 | #endif | |
801 | ||
802 | #ifdef ENABLE_MARK_CLEAN | |
803 | /** | |
804 | * Since DMA is i-cache coherent, any (complete) pages that were written via | |
805 | * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to | |
806 | * flush them when they get mapped into an executable vm-area. | |
807 | */ | |
808 | static void | |
809 | mark_clean (void *addr, size_t size) | |
810 | { | |
811 | unsigned long pg_addr, end; | |
812 | ||
813 | pg_addr = PAGE_ALIGN((unsigned long) addr); | |
814 | end = (unsigned long) addr + size; | |
815 | while (pg_addr + PAGE_SIZE <= end) { | |
816 | struct page *page = virt_to_page((void *)pg_addr); | |
817 | set_bit(PG_arch_1, &page->flags); | |
818 | pg_addr += PAGE_SIZE; | |
819 | } | |
820 | } | |
821 | #endif | |
822 | ||
823 | /** | |
824 | * sba_mark_invalid - invalidate one or more IO PDIR entries | |
825 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
826 | * @iova: IO Virtual Address mapped earlier | |
827 | * @byte_cnt: number of bytes this mapping covers. | |
828 | * | |
829 | * Marking the IO PDIR entry(ies) as Invalid and invalidate | |
830 | * corresponding IO TLB entry. The PCOM (Purge Command Register) | |
831 | * is to purge stale entries in the IO TLB when unmapping entries. | |
832 | * | |
833 | * The PCOM register supports purging of multiple pages, with a minium | |
834 | * of 1 page and a maximum of 2GB. Hardware requires the address be | |
835 | * aligned to the size of the range being purged. The size of the range | |
836 | * must be a power of 2. The "Cool perf optimization" in the | |
837 | * allocation routine helps keep that true. | |
838 | */ | |
839 | static SBA_INLINE void | |
840 | sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) | |
841 | { | |
842 | u32 iovp = (u32) SBA_IOVP(ioc,iova); | |
843 | ||
844 | int off = PDIR_INDEX(iovp); | |
845 | ||
846 | /* Must be non-zero and rounded up */ | |
847 | ASSERT(byte_cnt > 0); | |
848 | ASSERT(0 == (byte_cnt & ~iovp_mask)); | |
849 | ||
850 | #ifdef ASSERT_PDIR_SANITY | |
851 | /* Assert first pdir entry is set */ | |
852 | if (!(ioc->pdir_base[off] >> 60)) { | |
853 | sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); | |
854 | } | |
855 | #endif | |
856 | ||
857 | if (byte_cnt <= iovp_size) | |
858 | { | |
859 | ASSERT(off < ioc->pdir_size); | |
860 | ||
861 | iovp |= iovp_shift; /* set "size" field for PCOM */ | |
862 | ||
863 | #ifndef FULL_VALID_PDIR | |
864 | /* | |
865 | ** clear I/O PDIR entry "valid" bit | |
866 | ** Do NOT clear the rest - save it for debugging. | |
867 | ** We should only clear bits that have previously | |
868 | ** been enabled. | |
869 | */ | |
870 | ioc->pdir_base[off] &= ~(0x80000000000000FFULL); | |
871 | #else | |
872 | /* | |
873 | ** If we want to maintain the PDIR as valid, put in | |
874 | ** the spill page so devices prefetching won't | |
875 | ** cause a hard fail. | |
876 | */ | |
877 | ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page); | |
878 | #endif | |
879 | } else { | |
880 | u32 t = get_iovp_order(byte_cnt) + iovp_shift; | |
881 | ||
882 | iovp |= t; | |
883 | ASSERT(t <= 31); /* 2GB! Max value of "size" field */ | |
884 | ||
885 | do { | |
886 | /* verify this pdir entry is enabled */ | |
887 | ASSERT(ioc->pdir_base[off] >> 63); | |
888 | #ifndef FULL_VALID_PDIR | |
889 | /* clear I/O Pdir entry "valid" bit first */ | |
890 | ioc->pdir_base[off] &= ~(0x80000000000000FFULL); | |
891 | #else | |
892 | ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page); | |
893 | #endif | |
894 | off++; | |
895 | byte_cnt -= iovp_size; | |
896 | } while (byte_cnt > 0); | |
897 | } | |
898 | ||
899 | WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM); | |
900 | } | |
901 | ||
902 | /** | |
309df0c5 | 903 | * sba_map_single_attrs - map one buffer and return IOVA for DMA |
1da177e4 LT |
904 | * @dev: instance of PCI owned by the driver that's asking. |
905 | * @addr: driver buffer to map. | |
906 | * @size: number of bytes to map in driver buffer. | |
907 | * @dir: R/W or both. | |
309df0c5 | 908 | * @attrs: optional dma attributes |
1da177e4 LT |
909 | * |
910 | * See Documentation/DMA-mapping.txt | |
911 | */ | |
055bcf99 | 912 | static dma_addr_t |
309df0c5 AK |
913 | sba_map_single_attrs(struct device *dev, void *addr, size_t size, int dir, |
914 | struct dma_attrs *attrs) | |
1da177e4 LT |
915 | { |
916 | struct ioc *ioc; | |
917 | dma_addr_t iovp; | |
918 | dma_addr_t offset; | |
919 | u64 *pdir_start; | |
920 | int pide; | |
921 | #ifdef ASSERT_PDIR_SANITY | |
922 | unsigned long flags; | |
923 | #endif | |
924 | #ifdef ALLOW_IOV_BYPASS | |
925 | unsigned long pci_addr = virt_to_phys(addr); | |
926 | #endif | |
927 | ||
928 | #ifdef ALLOW_IOV_BYPASS | |
929 | ASSERT(to_pci_dev(dev)->dma_mask); | |
930 | /* | |
931 | ** Check if the PCI device can DMA to ptr... if so, just return ptr | |
932 | */ | |
933 | if (likely((pci_addr & ~to_pci_dev(dev)->dma_mask) == 0)) { | |
934 | /* | |
935 | ** Device is bit capable of DMA'ing to the buffer... | |
936 | ** just return the PCI address of ptr | |
937 | */ | |
309df0c5 AK |
938 | DBG_BYPASS("sba_map_single_attrs() bypass mask/addr: " |
939 | "0x%lx/0x%lx\n", | |
1da177e4 LT |
940 | to_pci_dev(dev)->dma_mask, pci_addr); |
941 | return pci_addr; | |
942 | } | |
943 | #endif | |
944 | ioc = GET_IOC(dev); | |
945 | ASSERT(ioc); | |
946 | ||
947 | prefetch(ioc->res_hint); | |
948 | ||
949 | ASSERT(size > 0); | |
950 | ASSERT(size <= DMA_CHUNK_SIZE); | |
951 | ||
952 | /* save offset bits */ | |
953 | offset = ((dma_addr_t) (long) addr) & ~iovp_mask; | |
954 | ||
955 | /* round up to nearest iovp_size */ | |
956 | size = (size + offset + ~iovp_mask) & iovp_mask; | |
957 | ||
958 | #ifdef ASSERT_PDIR_SANITY | |
959 | spin_lock_irqsave(&ioc->res_lock, flags); | |
309df0c5 | 960 | if (sba_check_pdir(ioc,"Check before sba_map_single_attrs()")) |
1da177e4 LT |
961 | panic("Sanity check failed"); |
962 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
963 | #endif | |
964 | ||
b34eb53c | 965 | pide = sba_alloc_range(ioc, dev, size); |
1da177e4 LT |
966 | |
967 | iovp = (dma_addr_t) pide << iovp_shift; | |
968 | ||
d4ed8084 | 969 | DBG_RUN("%s() 0x%p -> 0x%lx\n", __func__, addr, (long) iovp | offset); |
1da177e4 LT |
970 | |
971 | pdir_start = &(ioc->pdir_base[pide]); | |
972 | ||
973 | while (size > 0) { | |
974 | ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */ | |
975 | sba_io_pdir_entry(pdir_start, (unsigned long) addr); | |
976 | ||
977 | DBG_RUN(" pdir 0x%p %lx\n", pdir_start, *pdir_start); | |
978 | ||
979 | addr += iovp_size; | |
980 | size -= iovp_size; | |
981 | pdir_start++; | |
982 | } | |
983 | /* force pdir update */ | |
984 | wmb(); | |
985 | ||
986 | /* form complete address */ | |
987 | #ifdef ASSERT_PDIR_SANITY | |
988 | spin_lock_irqsave(&ioc->res_lock, flags); | |
309df0c5 | 989 | sba_check_pdir(ioc,"Check after sba_map_single_attrs()"); |
1da177e4 LT |
990 | spin_unlock_irqrestore(&ioc->res_lock, flags); |
991 | #endif | |
992 | return SBA_IOVA(ioc, iovp, offset); | |
993 | } | |
994 | ||
5f6602a1 AW |
995 | #ifdef ENABLE_MARK_CLEAN |
996 | static SBA_INLINE void | |
997 | sba_mark_clean(struct ioc *ioc, dma_addr_t iova, size_t size) | |
998 | { | |
999 | u32 iovp = (u32) SBA_IOVP(ioc,iova); | |
1000 | int off = PDIR_INDEX(iovp); | |
1001 | void *addr; | |
1002 | ||
1003 | if (size <= iovp_size) { | |
1004 | addr = phys_to_virt(ioc->pdir_base[off] & | |
1005 | ~0xE000000000000FFFULL); | |
1006 | mark_clean(addr, size); | |
1007 | } else { | |
1008 | do { | |
1009 | addr = phys_to_virt(ioc->pdir_base[off] & | |
1010 | ~0xE000000000000FFFULL); | |
1011 | mark_clean(addr, min(size, iovp_size)); | |
1012 | off++; | |
1013 | size -= iovp_size; | |
1014 | } while (size > 0); | |
1015 | } | |
1016 | } | |
1017 | #endif | |
1018 | ||
1da177e4 | 1019 | /** |
309df0c5 | 1020 | * sba_unmap_single_attrs - unmap one IOVA and free resources |
1da177e4 LT |
1021 | * @dev: instance of PCI owned by the driver that's asking. |
1022 | * @iova: IOVA of driver buffer previously mapped. | |
1023 | * @size: number of bytes mapped in driver buffer. | |
1024 | * @dir: R/W or both. | |
309df0c5 | 1025 | * @attrs: optional dma attributes |
1da177e4 LT |
1026 | * |
1027 | * See Documentation/DMA-mapping.txt | |
1028 | */ | |
055bcf99 FT |
1029 | static void sba_unmap_single_attrs(struct device *dev, dma_addr_t iova, size_t size, |
1030 | int dir, struct dma_attrs *attrs) | |
1da177e4 LT |
1031 | { |
1032 | struct ioc *ioc; | |
1033 | #if DELAYED_RESOURCE_CNT > 0 | |
1034 | struct sba_dma_pair *d; | |
1035 | #endif | |
1036 | unsigned long flags; | |
1037 | dma_addr_t offset; | |
1038 | ||
1039 | ioc = GET_IOC(dev); | |
1040 | ASSERT(ioc); | |
1041 | ||
1042 | #ifdef ALLOW_IOV_BYPASS | |
1043 | if (likely((iova & ioc->imask) != ioc->ibase)) { | |
1044 | /* | |
1045 | ** Address does not fall w/in IOVA, must be bypassing | |
1046 | */ | |
309df0c5 AK |
1047 | DBG_BYPASS("sba_unmap_single_atttrs() bypass addr: 0x%lx\n", |
1048 | iova); | |
1da177e4 LT |
1049 | |
1050 | #ifdef ENABLE_MARK_CLEAN | |
1051 | if (dir == DMA_FROM_DEVICE) { | |
1052 | mark_clean(phys_to_virt(iova), size); | |
1053 | } | |
1054 | #endif | |
1055 | return; | |
1056 | } | |
1057 | #endif | |
1058 | offset = iova & ~iovp_mask; | |
1059 | ||
d4ed8084 | 1060 | DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size); |
1da177e4 LT |
1061 | |
1062 | iova ^= offset; /* clear offset bits */ | |
1063 | size += offset; | |
1064 | size = ROUNDUP(size, iovp_size); | |
1065 | ||
5f6602a1 AW |
1066 | #ifdef ENABLE_MARK_CLEAN |
1067 | if (dir == DMA_FROM_DEVICE) | |
1068 | sba_mark_clean(ioc, iova, size); | |
1069 | #endif | |
1da177e4 LT |
1070 | |
1071 | #if DELAYED_RESOURCE_CNT > 0 | |
1072 | spin_lock_irqsave(&ioc->saved_lock, flags); | |
1073 | d = &(ioc->saved[ioc->saved_cnt]); | |
1074 | d->iova = iova; | |
1075 | d->size = size; | |
1076 | if (unlikely(++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT)) { | |
1077 | int cnt = ioc->saved_cnt; | |
1078 | spin_lock(&ioc->res_lock); | |
1079 | while (cnt--) { | |
1080 | sba_mark_invalid(ioc, d->iova, d->size); | |
1081 | sba_free_range(ioc, d->iova, d->size); | |
1082 | d--; | |
1083 | } | |
1084 | ioc->saved_cnt = 0; | |
1085 | READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ | |
1086 | spin_unlock(&ioc->res_lock); | |
1087 | } | |
1088 | spin_unlock_irqrestore(&ioc->saved_lock, flags); | |
1089 | #else /* DELAYED_RESOURCE_CNT == 0 */ | |
1090 | spin_lock_irqsave(&ioc->res_lock, flags); | |
1091 | sba_mark_invalid(ioc, iova, size); | |
1092 | sba_free_range(ioc, iova, size); | |
1093 | READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ | |
1094 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
1095 | #endif /* DELAYED_RESOURCE_CNT == 0 */ | |
1da177e4 | 1096 | } |
1da177e4 LT |
1097 | |
1098 | /** | |
1099 | * sba_alloc_coherent - allocate/map shared mem for DMA | |
1100 | * @dev: instance of PCI owned by the driver that's asking. | |
1101 | * @size: number of bytes mapped in driver buffer. | |
1102 | * @dma_handle: IOVA of new buffer. | |
1103 | * | |
1104 | * See Documentation/DMA-mapping.txt | |
1105 | */ | |
055bcf99 | 1106 | static void * |
06a54497 | 1107 | sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 LT |
1108 | { |
1109 | struct ioc *ioc; | |
1110 | void *addr; | |
1111 | ||
1112 | ioc = GET_IOC(dev); | |
1113 | ASSERT(ioc); | |
1114 | ||
1115 | #ifdef CONFIG_NUMA | |
1116 | { | |
1117 | struct page *page; | |
1118 | page = alloc_pages_node(ioc->node == MAX_NUMNODES ? | |
1119 | numa_node_id() : ioc->node, flags, | |
1120 | get_order(size)); | |
1121 | ||
1122 | if (unlikely(!page)) | |
1123 | return NULL; | |
1124 | ||
1125 | addr = page_address(page); | |
1126 | } | |
1127 | #else | |
1128 | addr = (void *) __get_free_pages(flags, get_order(size)); | |
1129 | #endif | |
1130 | if (unlikely(!addr)) | |
1131 | return NULL; | |
1132 | ||
1133 | memset(addr, 0, size); | |
1134 | *dma_handle = virt_to_phys(addr); | |
1135 | ||
1136 | #ifdef ALLOW_IOV_BYPASS | |
1137 | ASSERT(dev->coherent_dma_mask); | |
1138 | /* | |
1139 | ** Check if the PCI device can DMA to ptr... if so, just return ptr | |
1140 | */ | |
1141 | if (likely((*dma_handle & ~dev->coherent_dma_mask) == 0)) { | |
1142 | DBG_BYPASS("sba_alloc_coherent() bypass mask/addr: 0x%lx/0x%lx\n", | |
1143 | dev->coherent_dma_mask, *dma_handle); | |
1144 | ||
1145 | return addr; | |
1146 | } | |
1147 | #endif | |
1148 | ||
1149 | /* | |
1150 | * If device can't bypass or bypass is disabled, pass the 32bit fake | |
1151 | * device to map single to get an iova mapping. | |
1152 | */ | |
309df0c5 AK |
1153 | *dma_handle = sba_map_single_attrs(&ioc->sac_only_dev->dev, addr, |
1154 | size, 0, NULL); | |
1da177e4 LT |
1155 | |
1156 | return addr; | |
1157 | } | |
1158 | ||
1159 | ||
1160 | /** | |
1161 | * sba_free_coherent - free/unmap shared mem for DMA | |
1162 | * @dev: instance of PCI owned by the driver that's asking. | |
1163 | * @size: number of bytes mapped in driver buffer. | |
1164 | * @vaddr: virtual address IOVA of "consistent" buffer. | |
1165 | * @dma_handler: IO virtual address of "consistent" buffer. | |
1166 | * | |
1167 | * See Documentation/DMA-mapping.txt | |
1168 | */ | |
055bcf99 FT |
1169 | static void sba_free_coherent (struct device *dev, size_t size, void *vaddr, |
1170 | dma_addr_t dma_handle) | |
1da177e4 | 1171 | { |
309df0c5 | 1172 | sba_unmap_single_attrs(dev, dma_handle, size, 0, NULL); |
1da177e4 LT |
1173 | free_pages((unsigned long) vaddr, get_order(size)); |
1174 | } | |
1175 | ||
1176 | ||
1177 | /* | |
1178 | ** Since 0 is a valid pdir_base index value, can't use that | |
1179 | ** to determine if a value is valid or not. Use a flag to indicate | |
1180 | ** the SG list entry contains a valid pdir index. | |
1181 | */ | |
1182 | #define PIDE_FLAG 0x1UL | |
1183 | ||
1184 | #ifdef DEBUG_LARGE_SG_ENTRIES | |
1185 | int dump_run_sg = 0; | |
1186 | #endif | |
1187 | ||
1188 | ||
1189 | /** | |
1190 | * sba_fill_pdir - write allocated SG entries into IO PDIR | |
1191 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
1192 | * @startsg: list of IOVA/size pairs | |
1193 | * @nents: number of entries in startsg list | |
1194 | * | |
1195 | * Take preprocessed SG list and write corresponding entries | |
1196 | * in the IO PDIR. | |
1197 | */ | |
1198 | ||
1199 | static SBA_INLINE int | |
1200 | sba_fill_pdir( | |
1201 | struct ioc *ioc, | |
1202 | struct scatterlist *startsg, | |
1203 | int nents) | |
1204 | { | |
1205 | struct scatterlist *dma_sg = startsg; /* pointer to current DMA */ | |
1206 | int n_mappings = 0; | |
1207 | u64 *pdirp = NULL; | |
1208 | unsigned long dma_offset = 0; | |
1209 | ||
1da177e4 LT |
1210 | while (nents-- > 0) { |
1211 | int cnt = startsg->dma_length; | |
1212 | startsg->dma_length = 0; | |
1213 | ||
1214 | #ifdef DEBUG_LARGE_SG_ENTRIES | |
1215 | if (dump_run_sg) | |
1216 | printk(" %2d : %08lx/%05x %p\n", | |
1217 | nents, startsg->dma_address, cnt, | |
1218 | sba_sg_address(startsg)); | |
1219 | #else | |
1220 | DBG_RUN_SG(" %d : %08lx/%05x %p\n", | |
1221 | nents, startsg->dma_address, cnt, | |
1222 | sba_sg_address(startsg)); | |
1223 | #endif | |
1224 | /* | |
1225 | ** Look for the start of a new DMA stream | |
1226 | */ | |
1227 | if (startsg->dma_address & PIDE_FLAG) { | |
1228 | u32 pide = startsg->dma_address & ~PIDE_FLAG; | |
1229 | dma_offset = (unsigned long) pide & ~iovp_mask; | |
1230 | startsg->dma_address = 0; | |
bdb02504 FT |
1231 | if (n_mappings) |
1232 | dma_sg = sg_next(dma_sg); | |
1da177e4 LT |
1233 | dma_sg->dma_address = pide | ioc->ibase; |
1234 | pdirp = &(ioc->pdir_base[pide >> iovp_shift]); | |
1235 | n_mappings++; | |
1236 | } | |
1237 | ||
1238 | /* | |
1239 | ** Look for a VCONTIG chunk | |
1240 | */ | |
1241 | if (cnt) { | |
1242 | unsigned long vaddr = (unsigned long) sba_sg_address(startsg); | |
1243 | ASSERT(pdirp); | |
1244 | ||
1245 | /* Since multiple Vcontig blocks could make up | |
1246 | ** one DMA stream, *add* cnt to dma_len. | |
1247 | */ | |
1248 | dma_sg->dma_length += cnt; | |
1249 | cnt += dma_offset; | |
1250 | dma_offset=0; /* only want offset on first chunk */ | |
1251 | cnt = ROUNDUP(cnt, iovp_size); | |
1252 | do { | |
1253 | sba_io_pdir_entry(pdirp, vaddr); | |
1254 | vaddr += iovp_size; | |
1255 | cnt -= iovp_size; | |
1256 | pdirp++; | |
1257 | } while (cnt > 0); | |
1258 | } | |
9b6eccfc | 1259 | startsg = sg_next(startsg); |
1da177e4 LT |
1260 | } |
1261 | /* force pdir update */ | |
1262 | wmb(); | |
1263 | ||
1264 | #ifdef DEBUG_LARGE_SG_ENTRIES | |
1265 | dump_run_sg = 0; | |
1266 | #endif | |
1267 | return(n_mappings); | |
1268 | } | |
1269 | ||
1270 | ||
1271 | /* | |
1272 | ** Two address ranges are DMA contiguous *iff* "end of prev" and | |
1273 | ** "start of next" are both on an IOV page boundary. | |
1274 | ** | |
1275 | ** (shift left is a quick trick to mask off upper bits) | |
1276 | */ | |
1277 | #define DMA_CONTIG(__X, __Y) \ | |
1278 | (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL) | |
1279 | ||
1280 | ||
1281 | /** | |
1282 | * sba_coalesce_chunks - preprocess the SG list | |
1283 | * @ioc: IO MMU structure which owns the pdir we are interested in. | |
1284 | * @startsg: list of IOVA/size pairs | |
1285 | * @nents: number of entries in startsg list | |
1286 | * | |
1287 | * First pass is to walk the SG list and determine where the breaks are | |
1288 | * in the DMA stream. Allocates PDIR entries but does not fill them. | |
1289 | * Returns the number of DMA chunks. | |
1290 | * | |
1291 | * Doing the fill separate from the coalescing/allocation keeps the | |
1292 | * code simpler. Future enhancement could make one pass through | |
1293 | * the sglist do both. | |
1294 | */ | |
1295 | static SBA_INLINE int | |
a031bbcb | 1296 | sba_coalesce_chunks(struct ioc *ioc, struct device *dev, |
1da177e4 LT |
1297 | struct scatterlist *startsg, |
1298 | int nents) | |
1299 | { | |
1300 | struct scatterlist *vcontig_sg; /* VCONTIG chunk head */ | |
1301 | unsigned long vcontig_len; /* len of VCONTIG chunk */ | |
1302 | unsigned long vcontig_end; | |
1303 | struct scatterlist *dma_sg; /* next DMA stream head */ | |
1304 | unsigned long dma_offset, dma_len; /* start/len of DMA stream */ | |
1305 | int n_mappings = 0; | |
a031bbcb | 1306 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
1da177e4 LT |
1307 | |
1308 | while (nents > 0) { | |
1309 | unsigned long vaddr = (unsigned long) sba_sg_address(startsg); | |
1310 | ||
1311 | /* | |
1312 | ** Prepare for first/next DMA stream | |
1313 | */ | |
1314 | dma_sg = vcontig_sg = startsg; | |
1315 | dma_len = vcontig_len = vcontig_end = startsg->length; | |
1316 | vcontig_end += vaddr; | |
1317 | dma_offset = vaddr & ~iovp_mask; | |
1318 | ||
1319 | /* PARANOID: clear entries */ | |
1320 | startsg->dma_address = startsg->dma_length = 0; | |
1321 | ||
1322 | /* | |
1323 | ** This loop terminates one iteration "early" since | |
1324 | ** it's always looking one "ahead". | |
1325 | */ | |
1326 | while (--nents > 0) { | |
1327 | unsigned long vaddr; /* tmp */ | |
1328 | ||
9b6eccfc | 1329 | startsg = sg_next(startsg); |
1da177e4 LT |
1330 | |
1331 | /* PARANOID */ | |
1332 | startsg->dma_address = startsg->dma_length = 0; | |
1333 | ||
1334 | /* catch brokenness in SCSI layer */ | |
1335 | ASSERT(startsg->length <= DMA_CHUNK_SIZE); | |
1336 | ||
1337 | /* | |
1338 | ** First make sure current dma stream won't | |
1339 | ** exceed DMA_CHUNK_SIZE if we coalesce the | |
1340 | ** next entry. | |
1341 | */ | |
1342 | if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask) | |
1343 | > DMA_CHUNK_SIZE) | |
1344 | break; | |
1345 | ||
a031bbcb FT |
1346 | if (dma_len + startsg->length > max_seg_size) |
1347 | break; | |
1348 | ||
1da177e4 LT |
1349 | /* |
1350 | ** Then look for virtually contiguous blocks. | |
1351 | ** | |
1352 | ** append the next transaction? | |
1353 | */ | |
1354 | vaddr = (unsigned long) sba_sg_address(startsg); | |
1355 | if (vcontig_end == vaddr) | |
1356 | { | |
1357 | vcontig_len += startsg->length; | |
1358 | vcontig_end += startsg->length; | |
1359 | dma_len += startsg->length; | |
1360 | continue; | |
1361 | } | |
1362 | ||
1363 | #ifdef DEBUG_LARGE_SG_ENTRIES | |
1364 | dump_run_sg = (vcontig_len > iovp_size); | |
1365 | #endif | |
1366 | ||
1367 | /* | |
1368 | ** Not virtually contigous. | |
1369 | ** Terminate prev chunk. | |
1370 | ** Start a new chunk. | |
1371 | ** | |
1372 | ** Once we start a new VCONTIG chunk, dma_offset | |
1373 | ** can't change. And we need the offset from the first | |
1374 | ** chunk - not the last one. Ergo Successive chunks | |
1375 | ** must start on page boundaries and dove tail | |
1376 | ** with it's predecessor. | |
1377 | */ | |
1378 | vcontig_sg->dma_length = vcontig_len; | |
1379 | ||
1380 | vcontig_sg = startsg; | |
1381 | vcontig_len = startsg->length; | |
1382 | ||
1383 | /* | |
1384 | ** 3) do the entries end/start on page boundaries? | |
1385 | ** Don't update vcontig_end until we've checked. | |
1386 | */ | |
1387 | if (DMA_CONTIG(vcontig_end, vaddr)) | |
1388 | { | |
1389 | vcontig_end = vcontig_len + vaddr; | |
1390 | dma_len += vcontig_len; | |
1391 | continue; | |
1392 | } else { | |
1393 | break; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | /* | |
1398 | ** End of DMA Stream | |
1399 | ** Terminate last VCONTIG block. | |
1400 | ** Allocate space for DMA stream. | |
1401 | */ | |
1402 | vcontig_sg->dma_length = vcontig_len; | |
1403 | dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask; | |
1404 | ASSERT(dma_len <= DMA_CHUNK_SIZE); | |
1405 | dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG | |
b34eb53c | 1406 | | (sba_alloc_range(ioc, dev, dma_len) << iovp_shift) |
1da177e4 LT |
1407 | | dma_offset); |
1408 | n_mappings++; | |
1409 | } | |
1410 | ||
1411 | return n_mappings; | |
1412 | } | |
1413 | ||
1414 | ||
1415 | /** | |
1416 | * sba_map_sg - map Scatter/Gather list | |
1417 | * @dev: instance of PCI owned by the driver that's asking. | |
1418 | * @sglist: array of buffer/length pairs | |
1419 | * @nents: number of entries in list | |
1420 | * @dir: R/W or both. | |
309df0c5 | 1421 | * @attrs: optional dma attributes |
1da177e4 LT |
1422 | * |
1423 | * See Documentation/DMA-mapping.txt | |
1424 | */ | |
055bcf99 FT |
1425 | static int sba_map_sg_attrs(struct device *dev, struct scatterlist *sglist, |
1426 | int nents, int dir, struct dma_attrs *attrs) | |
1da177e4 LT |
1427 | { |
1428 | struct ioc *ioc; | |
1429 | int coalesced, filled = 0; | |
1430 | #ifdef ASSERT_PDIR_SANITY | |
1431 | unsigned long flags; | |
1432 | #endif | |
1433 | #ifdef ALLOW_IOV_BYPASS_SG | |
1434 | struct scatterlist *sg; | |
1435 | #endif | |
1436 | ||
d4ed8084 | 1437 | DBG_RUN_SG("%s() START %d entries\n", __func__, nents); |
1da177e4 LT |
1438 | ioc = GET_IOC(dev); |
1439 | ASSERT(ioc); | |
1440 | ||
1441 | #ifdef ALLOW_IOV_BYPASS_SG | |
1442 | ASSERT(to_pci_dev(dev)->dma_mask); | |
1443 | if (likely((ioc->dma_mask & ~to_pci_dev(dev)->dma_mask) == 0)) { | |
9b6eccfc | 1444 | for_each_sg(sglist, sg, nents, filled) { |
1da177e4 LT |
1445 | sg->dma_length = sg->length; |
1446 | sg->dma_address = virt_to_phys(sba_sg_address(sg)); | |
1447 | } | |
1448 | return filled; | |
1449 | } | |
1450 | #endif | |
1451 | /* Fast path single entry scatterlists. */ | |
1452 | if (nents == 1) { | |
1453 | sglist->dma_length = sglist->length; | |
309df0c5 | 1454 | sglist->dma_address = sba_map_single_attrs(dev, sba_sg_address(sglist), sglist->length, dir, attrs); |
1da177e4 LT |
1455 | return 1; |
1456 | } | |
1457 | ||
1458 | #ifdef ASSERT_PDIR_SANITY | |
1459 | spin_lock_irqsave(&ioc->res_lock, flags); | |
309df0c5 | 1460 | if (sba_check_pdir(ioc,"Check before sba_map_sg_attrs()")) |
1da177e4 LT |
1461 | { |
1462 | sba_dump_sg(ioc, sglist, nents); | |
309df0c5 | 1463 | panic("Check before sba_map_sg_attrs()"); |
1da177e4 LT |
1464 | } |
1465 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
1466 | #endif | |
1467 | ||
1468 | prefetch(ioc->res_hint); | |
1469 | ||
1470 | /* | |
1471 | ** First coalesce the chunks and allocate I/O pdir space | |
1472 | ** | |
1473 | ** If this is one DMA stream, we can properly map using the | |
1474 | ** correct virtual address associated with each DMA page. | |
1475 | ** w/o this association, we wouldn't have coherent DMA! | |
1476 | ** Access to the virtual address is what forces a two pass algorithm. | |
1477 | */ | |
a031bbcb | 1478 | coalesced = sba_coalesce_chunks(ioc, dev, sglist, nents); |
1da177e4 LT |
1479 | |
1480 | /* | |
1481 | ** Program the I/O Pdir | |
1482 | ** | |
1483 | ** map the virtual addresses to the I/O Pdir | |
1484 | ** o dma_address will contain the pdir index | |
1485 | ** o dma_len will contain the number of bytes to map | |
1486 | ** o address contains the virtual address. | |
1487 | */ | |
1488 | filled = sba_fill_pdir(ioc, sglist, nents); | |
1489 | ||
1490 | #ifdef ASSERT_PDIR_SANITY | |
1491 | spin_lock_irqsave(&ioc->res_lock, flags); | |
309df0c5 | 1492 | if (sba_check_pdir(ioc,"Check after sba_map_sg_attrs()")) |
1da177e4 LT |
1493 | { |
1494 | sba_dump_sg(ioc, sglist, nents); | |
309df0c5 | 1495 | panic("Check after sba_map_sg_attrs()\n"); |
1da177e4 LT |
1496 | } |
1497 | spin_unlock_irqrestore(&ioc->res_lock, flags); | |
1498 | #endif | |
1499 | ||
1500 | ASSERT(coalesced == filled); | |
d4ed8084 | 1501 | DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled); |
1da177e4 LT |
1502 | |
1503 | return filled; | |
1504 | } | |
1da177e4 LT |
1505 | |
1506 | /** | |
309df0c5 | 1507 | * sba_unmap_sg_attrs - unmap Scatter/Gather list |
1da177e4 LT |
1508 | * @dev: instance of PCI owned by the driver that's asking. |
1509 | * @sglist: array of buffer/length pairs | |
1510 | * @nents: number of entries in list | |
1511 | * @dir: R/W or both. | |
309df0c5 | 1512 | * @attrs: optional dma attributes |
1da177e4 LT |
1513 | * |
1514 | * See Documentation/DMA-mapping.txt | |
1515 | */ | |
055bcf99 FT |
1516 | static void sba_unmap_sg_attrs(struct device *dev, struct scatterlist *sglist, |
1517 | int nents, int dir, struct dma_attrs *attrs) | |
1da177e4 LT |
1518 | { |
1519 | #ifdef ASSERT_PDIR_SANITY | |
1520 | struct ioc *ioc; | |
1521 | unsigned long flags; | |
1522 | #endif | |
1523 | ||
1524 | DBG_RUN_SG("%s() START %d entries, %p,%x\n", | |
d4ed8084 | 1525 | __func__, nents, sba_sg_address(sglist), sglist->length); |
1da177e4 LT |
1526 | |
1527 | #ifdef ASSERT_PDIR_SANITY | |
1528 | ioc = GET_IOC(dev); | |
1529 | ASSERT(ioc); | |
1530 | ||
1531 | spin_lock_irqsave(&ioc->res_lock, flags); | |
309df0c5 | 1532 | sba_check_pdir(ioc,"Check before sba_unmap_sg_attrs()"); |
1da177e4 LT |
1533 | spin_unlock_irqrestore(&ioc->res_lock, flags); |
1534 | #endif | |
1535 | ||
1536 | while (nents && sglist->dma_length) { | |
1537 | ||
309df0c5 AK |
1538 | sba_unmap_single_attrs(dev, sglist->dma_address, |
1539 | sglist->dma_length, dir, attrs); | |
9b6eccfc | 1540 | sglist = sg_next(sglist); |
1da177e4 LT |
1541 | nents--; |
1542 | } | |
1543 | ||
d4ed8084 | 1544 | DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents); |
1da177e4 LT |
1545 | |
1546 | #ifdef ASSERT_PDIR_SANITY | |
1547 | spin_lock_irqsave(&ioc->res_lock, flags); | |
309df0c5 | 1548 | sba_check_pdir(ioc,"Check after sba_unmap_sg_attrs()"); |
1da177e4 LT |
1549 | spin_unlock_irqrestore(&ioc->res_lock, flags); |
1550 | #endif | |
1551 | ||
1552 | } | |
1553 | ||
1554 | /************************************************************** | |
1555 | * | |
1556 | * Initialization and claim | |
1557 | * | |
1558 | ***************************************************************/ | |
1559 | ||
1560 | static void __init | |
1561 | ioc_iova_init(struct ioc *ioc) | |
1562 | { | |
1563 | int tcnfg; | |
1564 | int agp_found = 0; | |
1565 | struct pci_dev *device = NULL; | |
1566 | #ifdef FULL_VALID_PDIR | |
1567 | unsigned long index; | |
1568 | #endif | |
1569 | ||
1570 | /* | |
1571 | ** Firmware programs the base and size of a "safe IOVA space" | |
1572 | ** (one that doesn't overlap memory or LMMIO space) in the | |
1573 | ** IBASE and IMASK registers. | |
1574 | */ | |
1575 | ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL; | |
1576 | ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL; | |
1577 | ||
1578 | ioc->iov_size = ~ioc->imask + 1; | |
1579 | ||
1580 | DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n", | |
d4ed8084 | 1581 | __func__, ioc->ioc_hpa, ioc->ibase, ioc->imask, |
1da177e4 LT |
1582 | ioc->iov_size >> 20); |
1583 | ||
1584 | switch (iovp_size) { | |
1585 | case 4*1024: tcnfg = 0; break; | |
1586 | case 8*1024: tcnfg = 1; break; | |
1587 | case 16*1024: tcnfg = 2; break; | |
1588 | case 64*1024: tcnfg = 3; break; | |
1589 | default: | |
1590 | panic(PFX "Unsupported IOTLB page size %ldK", | |
1591 | iovp_size >> 10); | |
1592 | break; | |
1593 | } | |
1594 | WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); | |
1595 | ||
1596 | ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE; | |
1597 | ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, | |
1598 | get_order(ioc->pdir_size)); | |
1599 | if (!ioc->pdir_base) | |
1600 | panic(PFX "Couldn't allocate I/O Page Table\n"); | |
1601 | ||
1602 | memset(ioc->pdir_base, 0, ioc->pdir_size); | |
1603 | ||
d4ed8084 | 1604 | DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __func__, |
1da177e4 LT |
1605 | iovp_size >> 10, ioc->pdir_base, ioc->pdir_size); |
1606 | ||
1607 | ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base); | |
1608 | WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); | |
1609 | ||
1610 | /* | |
1611 | ** If an AGP device is present, only use half of the IOV space | |
1612 | ** for PCI DMA. Unfortunately we can't know ahead of time | |
1613 | ** whether GART support will actually be used, for now we | |
1614 | ** can just key on an AGP device found in the system. | |
1615 | ** We program the next pdir index after we stop w/ a key for | |
1616 | ** the GART code to handshake on. | |
1617 | */ | |
1618 | for_each_pci_dev(device) | |
1619 | agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP); | |
1620 | ||
1621 | if (agp_found && reserve_sba_gart) { | |
1622 | printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n", | |
1623 | ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2); | |
1624 | ioc->pdir_size /= 2; | |
1625 | ((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE; | |
1626 | } | |
1627 | #ifdef FULL_VALID_PDIR | |
1628 | /* | |
1629 | ** Check to see if the spill page has been allocated, we don't need more than | |
1630 | ** one across multiple SBAs. | |
1631 | */ | |
1632 | if (!prefetch_spill_page) { | |
1633 | char *spill_poison = "SBAIOMMU POISON"; | |
1634 | int poison_size = 16; | |
1635 | void *poison_addr, *addr; | |
1636 | ||
1637 | addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size)); | |
1638 | if (!addr) | |
1639 | panic(PFX "Couldn't allocate PDIR spill page\n"); | |
1640 | ||
1641 | poison_addr = addr; | |
1642 | for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size) | |
1643 | memcpy(poison_addr, spill_poison, poison_size); | |
1644 | ||
1645 | prefetch_spill_page = virt_to_phys(addr); | |
1646 | ||
d4ed8084 | 1647 | DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __func__, prefetch_spill_page); |
1da177e4 LT |
1648 | } |
1649 | /* | |
1650 | ** Set all the PDIR entries valid w/ the spill page as the target | |
1651 | */ | |
1652 | for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++) | |
1653 | ((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page); | |
1654 | #endif | |
1655 | ||
1656 | /* Clear I/O TLB of any possible entries */ | |
1657 | WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM); | |
1658 | READ_REG(ioc->ioc_hpa + IOC_PCOM); | |
1659 | ||
1660 | /* Enable IOVA translation */ | |
1661 | WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); | |
1662 | READ_REG(ioc->ioc_hpa + IOC_IBASE); | |
1663 | } | |
1664 | ||
1665 | static void __init | |
1666 | ioc_resource_init(struct ioc *ioc) | |
1667 | { | |
1668 | spin_lock_init(&ioc->res_lock); | |
1669 | #if DELAYED_RESOURCE_CNT > 0 | |
1670 | spin_lock_init(&ioc->saved_lock); | |
1671 | #endif | |
1672 | ||
1673 | /* resource map size dictated by pdir_size */ | |
1674 | ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */ | |
1675 | ioc->res_size >>= 3; /* convert bit count to byte count */ | |
d4ed8084 | 1676 | DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size); |
1da177e4 LT |
1677 | |
1678 | ioc->res_map = (char *) __get_free_pages(GFP_KERNEL, | |
1679 | get_order(ioc->res_size)); | |
1680 | if (!ioc->res_map) | |
1681 | panic(PFX "Couldn't allocate resource map\n"); | |
1682 | ||
1683 | memset(ioc->res_map, 0, ioc->res_size); | |
1684 | /* next available IOVP - circular search */ | |
1685 | ioc->res_hint = (unsigned long *) ioc->res_map; | |
1686 | ||
1687 | #ifdef ASSERT_PDIR_SANITY | |
1688 | /* Mark first bit busy - ie no IOVA 0 */ | |
1689 | ioc->res_map[0] = 0x1; | |
1690 | ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE; | |
1691 | #endif | |
1692 | #ifdef FULL_VALID_PDIR | |
1693 | /* Mark the last resource used so we don't prefetch beyond IOVA space */ | |
1694 | ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */ | |
1695 | ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF | |
1696 | | prefetch_spill_page); | |
1697 | #endif | |
1698 | ||
d4ed8084 | 1699 | DBG_INIT("%s() res_map %x %p\n", __func__, |
1da177e4 LT |
1700 | ioc->res_size, (void *) ioc->res_map); |
1701 | } | |
1702 | ||
1703 | static void __init | |
1704 | ioc_sac_init(struct ioc *ioc) | |
1705 | { | |
1706 | struct pci_dev *sac = NULL; | |
1707 | struct pci_controller *controller = NULL; | |
1708 | ||
1709 | /* | |
1710 | * pci_alloc_coherent() must return a DMA address which is | |
1711 | * SAC (single address cycle) addressable, so allocate a | |
1712 | * pseudo-device to enforce that. | |
1713 | */ | |
52fd9108 | 1714 | sac = kzalloc(sizeof(*sac), GFP_KERNEL); |
1da177e4 LT |
1715 | if (!sac) |
1716 | panic(PFX "Couldn't allocate struct pci_dev"); | |
1da177e4 | 1717 | |
52fd9108 | 1718 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); |
1da177e4 LT |
1719 | if (!controller) |
1720 | panic(PFX "Couldn't allocate struct pci_controller"); | |
1da177e4 LT |
1721 | |
1722 | controller->iommu = ioc; | |
1723 | sac->sysdata = controller; | |
1724 | sac->dma_mask = 0xFFFFFFFFUL; | |
1725 | #ifdef CONFIG_PCI | |
1726 | sac->dev.bus = &pci_bus_type; | |
1727 | #endif | |
1728 | ioc->sac_only_dev = sac; | |
1729 | } | |
1730 | ||
1731 | static void __init | |
1732 | ioc_zx1_init(struct ioc *ioc) | |
1733 | { | |
1734 | unsigned long rope_config; | |
1735 | unsigned int i; | |
1736 | ||
1737 | if (ioc->rev < 0x20) | |
1738 | panic(PFX "IOC 2.0 or later required for IOMMU support\n"); | |
1739 | ||
1740 | /* 38 bit memory controller + extra bit for range displaced by MMIO */ | |
1741 | ioc->dma_mask = (0x1UL << 39) - 1; | |
1742 | ||
1743 | /* | |
1744 | ** Clear ROPE(N)_CONFIG AO bit. | |
1745 | ** Disables "NT Ordering" (~= !"Relaxed Ordering") | |
1746 | ** Overrides bit 1 in DMA Hint Sets. | |
1747 | ** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701. | |
1748 | */ | |
1749 | for (i=0; i<(8*8); i+=8) { | |
1750 | rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i); | |
1751 | rope_config &= ~IOC_ROPE_AO; | |
1752 | WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i); | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | typedef void (initfunc)(struct ioc *); | |
1757 | ||
1758 | struct ioc_iommu { | |
1759 | u32 func_id; | |
1760 | char *name; | |
1761 | initfunc *init; | |
1762 | }; | |
1763 | ||
1764 | static struct ioc_iommu ioc_iommu_info[] __initdata = { | |
1765 | { ZX1_IOC_ID, "zx1", ioc_zx1_init }, | |
1766 | { ZX2_IOC_ID, "zx2", NULL }, | |
1767 | { SX1000_IOC_ID, "sx1000", NULL }, | |
e15da401 | 1768 | { SX2000_IOC_ID, "sx2000", NULL }, |
1da177e4 LT |
1769 | }; |
1770 | ||
1771 | static struct ioc * __init | |
1772 | ioc_init(u64 hpa, void *handle) | |
1773 | { | |
1774 | struct ioc *ioc; | |
1775 | struct ioc_iommu *info; | |
1776 | ||
52fd9108 | 1777 | ioc = kzalloc(sizeof(*ioc), GFP_KERNEL); |
1da177e4 LT |
1778 | if (!ioc) |
1779 | return NULL; | |
1780 | ||
1da177e4 LT |
1781 | ioc->next = ioc_list; |
1782 | ioc_list = ioc; | |
1783 | ||
1784 | ioc->handle = handle; | |
1785 | ioc->ioc_hpa = ioremap(hpa, 0x1000); | |
1786 | ||
1787 | ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID); | |
1788 | ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL; | |
1789 | ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL; /* conservative */ | |
1790 | ||
1791 | for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) { | |
1792 | if (ioc->func_id == info->func_id) { | |
1793 | ioc->name = info->name; | |
1794 | if (info->init) | |
1795 | (info->init)(ioc); | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | iovp_size = (1 << iovp_shift); | |
1800 | iovp_mask = ~(iovp_size - 1); | |
1801 | ||
d4ed8084 | 1802 | DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __func__, |
1da177e4 LT |
1803 | PAGE_SIZE >> 10, iovp_size >> 10); |
1804 | ||
1805 | if (!ioc->name) { | |
1806 | ioc->name = kmalloc(24, GFP_KERNEL); | |
1807 | if (ioc->name) | |
1808 | sprintf((char *) ioc->name, "Unknown (%04x:%04x)", | |
1809 | ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF); | |
1810 | else | |
1811 | ioc->name = "Unknown"; | |
1812 | } | |
1813 | ||
1814 | ioc_iova_init(ioc); | |
1815 | ioc_resource_init(ioc); | |
1816 | ioc_sac_init(ioc); | |
1817 | ||
1818 | if ((long) ~iovp_mask > (long) ia64_max_iommu_merge_mask) | |
1819 | ia64_max_iommu_merge_mask = ~iovp_mask; | |
1820 | ||
1821 | printk(KERN_INFO PFX | |
1822 | "%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n", | |
1823 | ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF, | |
1824 | hpa, ioc->iov_size >> 20, ioc->ibase); | |
1825 | ||
1826 | return ioc; | |
1827 | } | |
1828 | ||
1829 | ||
1830 | ||
1831 | /************************************************************************** | |
1832 | ** | |
1833 | ** SBA initialization code (HW and SW) | |
1834 | ** | |
1835 | ** o identify SBA chip itself | |
1836 | ** o FIXME: initialize DMA hints for reasonable defaults | |
1837 | ** | |
1838 | **************************************************************************/ | |
1839 | ||
1840 | #ifdef CONFIG_PROC_FS | |
1841 | static void * | |
1842 | ioc_start(struct seq_file *s, loff_t *pos) | |
1843 | { | |
1844 | struct ioc *ioc; | |
1845 | loff_t n = *pos; | |
1846 | ||
1847 | for (ioc = ioc_list; ioc; ioc = ioc->next) | |
1848 | if (!n--) | |
1849 | return ioc; | |
1850 | ||
1851 | return NULL; | |
1852 | } | |
1853 | ||
1854 | static void * | |
1855 | ioc_next(struct seq_file *s, void *v, loff_t *pos) | |
1856 | { | |
1857 | struct ioc *ioc = v; | |
1858 | ||
1859 | ++*pos; | |
1860 | return ioc->next; | |
1861 | } | |
1862 | ||
1863 | static void | |
1864 | ioc_stop(struct seq_file *s, void *v) | |
1865 | { | |
1866 | } | |
1867 | ||
1868 | static int | |
1869 | ioc_show(struct seq_file *s, void *v) | |
1870 | { | |
1871 | struct ioc *ioc = v; | |
1872 | unsigned long *res_ptr = (unsigned long *)ioc->res_map; | |
1873 | int i, used = 0; | |
1874 | ||
1875 | seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n", | |
1876 | ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF)); | |
1877 | #ifdef CONFIG_NUMA | |
1878 | if (ioc->node != MAX_NUMNODES) | |
1879 | seq_printf(s, "NUMA node : %d\n", ioc->node); | |
1880 | #endif | |
1881 | seq_printf(s, "IOVA size : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024)); | |
1882 | seq_printf(s, "IOVA page size : %ld kb\n", iovp_size/1024); | |
1883 | ||
1884 | for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr) | |
1885 | used += hweight64(*res_ptr); | |
1886 | ||
1887 | seq_printf(s, "PDIR size : %d entries\n", ioc->pdir_size >> 3); | |
1888 | seq_printf(s, "PDIR used : %d entries\n", used); | |
1889 | ||
1890 | #ifdef PDIR_SEARCH_TIMING | |
1891 | { | |
1892 | unsigned long i = 0, avg = 0, min, max; | |
1893 | min = max = ioc->avg_search[0]; | |
1894 | for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { | |
1895 | avg += ioc->avg_search[i]; | |
1896 | if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; | |
1897 | if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; | |
1898 | } | |
1899 | avg /= SBA_SEARCH_SAMPLE; | |
1900 | seq_printf(s, "Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles/IOVA page)\n", | |
1901 | min, avg, max); | |
1902 | } | |
1903 | #endif | |
1904 | #ifndef ALLOW_IOV_BYPASS | |
1905 | seq_printf(s, "IOVA bypass disabled\n"); | |
1906 | #endif | |
1907 | return 0; | |
1908 | } | |
1909 | ||
a23fe55e | 1910 | static const struct seq_operations ioc_seq_ops = { |
1da177e4 LT |
1911 | .start = ioc_start, |
1912 | .next = ioc_next, | |
1913 | .stop = ioc_stop, | |
1914 | .show = ioc_show | |
1915 | }; | |
1916 | ||
1917 | static int | |
1918 | ioc_open(struct inode *inode, struct file *file) | |
1919 | { | |
1920 | return seq_open(file, &ioc_seq_ops); | |
1921 | } | |
1922 | ||
5dfe4c96 | 1923 | static const struct file_operations ioc_fops = { |
1da177e4 LT |
1924 | .open = ioc_open, |
1925 | .read = seq_read, | |
1926 | .llseek = seq_lseek, | |
1927 | .release = seq_release | |
1928 | }; | |
1929 | ||
1930 | static void __init | |
1931 | ioc_proc_init(void) | |
1932 | { | |
e2363768 | 1933 | struct proc_dir_entry *dir; |
1da177e4 LT |
1934 | |
1935 | dir = proc_mkdir("bus/mckinley", NULL); | |
1936 | if (!dir) | |
1937 | return; | |
1938 | ||
e2363768 | 1939 | proc_create(ioc_list->name, 0, dir, &ioc_fops); |
1da177e4 LT |
1940 | } |
1941 | #endif | |
1942 | ||
1943 | static void | |
1944 | sba_connect_bus(struct pci_bus *bus) | |
1945 | { | |
1946 | acpi_handle handle, parent; | |
1947 | acpi_status status; | |
1948 | struct ioc *ioc; | |
1949 | ||
1950 | if (!PCI_CONTROLLER(bus)) | |
1951 | panic(PFX "no sysdata on bus %d!\n", bus->number); | |
1952 | ||
1953 | if (PCI_CONTROLLER(bus)->iommu) | |
1954 | return; | |
1955 | ||
1956 | handle = PCI_CONTROLLER(bus)->acpi_handle; | |
1957 | if (!handle) | |
1958 | return; | |
1959 | ||
1960 | /* | |
1961 | * The IOC scope encloses PCI root bridges in the ACPI | |
1962 | * namespace, so work our way out until we find an IOC we | |
1963 | * claimed previously. | |
1964 | */ | |
1965 | do { | |
1966 | for (ioc = ioc_list; ioc; ioc = ioc->next) | |
1967 | if (ioc->handle == handle) { | |
1968 | PCI_CONTROLLER(bus)->iommu = ioc; | |
1969 | return; | |
1970 | } | |
1971 | ||
1972 | status = acpi_get_parent(handle, &parent); | |
1973 | handle = parent; | |
1974 | } while (ACPI_SUCCESS(status)); | |
1975 | ||
1976 | printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number); | |
1977 | } | |
1978 | ||
1979 | #ifdef CONFIG_NUMA | |
1980 | static void __init | |
1981 | sba_map_ioc_to_node(struct ioc *ioc, acpi_handle handle) | |
1982 | { | |
1da177e4 | 1983 | unsigned int node; |
bb0fc085 | 1984 | int pxm; |
1da177e4 LT |
1985 | |
1986 | ioc->node = MAX_NUMNODES; | |
1987 | ||
bb0fc085 | 1988 | pxm = acpi_get_pxm(handle); |
1da177e4 | 1989 | |
bb0fc085 | 1990 | if (pxm < 0) |
1da177e4 LT |
1991 | return; |
1992 | ||
762834e8 | 1993 | node = pxm_to_node(pxm); |
1da177e4 LT |
1994 | |
1995 | if (node >= MAX_NUMNODES || !node_online(node)) | |
1996 | return; | |
1997 | ||
1998 | ioc->node = node; | |
1999 | return; | |
2000 | } | |
2001 | #else | |
2002 | #define sba_map_ioc_to_node(ioc, handle) | |
2003 | #endif | |
2004 | ||
2005 | static int __init | |
2006 | acpi_sba_ioc_add(struct acpi_device *device) | |
2007 | { | |
2008 | struct ioc *ioc; | |
2009 | acpi_status status; | |
2010 | u64 hpa, length; | |
2011 | struct acpi_buffer buffer; | |
2012 | struct acpi_device_info *dev_info; | |
2013 | ||
2014 | status = hp_acpi_csr_space(device->handle, &hpa, &length); | |
2015 | if (ACPI_FAILURE(status)) | |
2016 | return 1; | |
2017 | ||
2018 | buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; | |
2019 | status = acpi_get_object_info(device->handle, &buffer); | |
2020 | if (ACPI_FAILURE(status)) | |
2021 | return 1; | |
2022 | dev_info = buffer.pointer; | |
2023 | ||
2024 | /* | |
2025 | * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI | |
2026 | * root bridges, and its CSR space includes the IOC function. | |
2027 | */ | |
2028 | if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0) { | |
2029 | hpa += ZX1_IOC_OFFSET; | |
2030 | /* zx1 based systems default to kernel page size iommu pages */ | |
2031 | if (!iovp_shift) | |
2032 | iovp_shift = min(PAGE_SHIFT, 16); | |
2033 | } | |
144c87b4 | 2034 | kfree(dev_info); |
1da177e4 LT |
2035 | |
2036 | /* | |
2037 | * default anything not caught above or specified on cmdline to 4k | |
2038 | * iommu page size | |
2039 | */ | |
2040 | if (!iovp_shift) | |
2041 | iovp_shift = 12; | |
2042 | ||
2043 | ioc = ioc_init(hpa, device->handle); | |
2044 | if (!ioc) | |
2045 | return 1; | |
2046 | ||
2047 | /* setup NUMA node association */ | |
2048 | sba_map_ioc_to_node(ioc, device->handle); | |
2049 | return 0; | |
2050 | } | |
2051 | ||
7091138f TR |
2052 | static const struct acpi_device_id hp_ioc_iommu_device_ids[] = { |
2053 | {"HWP0001", 0}, | |
2054 | {"HWP0004", 0}, | |
2055 | {"", 0}, | |
2056 | }; | |
1da177e4 LT |
2057 | static struct acpi_driver acpi_sba_ioc_driver = { |
2058 | .name = "IOC IOMMU Driver", | |
7091138f | 2059 | .ids = hp_ioc_iommu_device_ids, |
1da177e4 LT |
2060 | .ops = { |
2061 | .add = acpi_sba_ioc_add, | |
2062 | }, | |
2063 | }; | |
2064 | ||
4d9b977c FT |
2065 | extern struct dma_mapping_ops swiotlb_dma_ops; |
2066 | ||
1da177e4 LT |
2067 | static int __init |
2068 | sba_init(void) | |
2069 | { | |
0b9afede AW |
2070 | if (!ia64_platform_is("hpzx1") && !ia64_platform_is("hpzx1_swiotlb")) |
2071 | return 0; | |
2072 | ||
630bf207 | 2073 | #if defined(CONFIG_IA64_GENERIC) |
51b58e3e TL |
2074 | /* If we are booting a kdump kernel, the sba_iommu will |
2075 | * cause devices that were not shutdown properly to MCA | |
2076 | * as soon as they are turned back on. Our only option for | |
2077 | * a successful kdump kernel boot is to use the swiotlb. | |
2078 | */ | |
630bf207 | 2079 | if (is_kdump_kernel()) { |
4d9b977c | 2080 | dma_ops = &swiotlb_dma_ops; |
51b58e3e TL |
2081 | if (swiotlb_late_init_with_default_size(64 * (1<<20)) != 0) |
2082 | panic("Unable to initialize software I/O TLB:" | |
2083 | " Try machvec=dig boot option"); | |
2084 | machvec_init("dig"); | |
2085 | return 0; | |
2086 | } | |
2087 | #endif | |
2088 | ||
1da177e4 | 2089 | acpi_bus_register_driver(&acpi_sba_ioc_driver); |
0b9afede AW |
2090 | if (!ioc_list) { |
2091 | #ifdef CONFIG_IA64_GENERIC | |
0b9afede AW |
2092 | /* |
2093 | * If we didn't find something sba_iommu can claim, we | |
2094 | * need to setup the swiotlb and switch to the dig machvec. | |
2095 | */ | |
4d9b977c | 2096 | dma_ops = &swiotlb_dma_ops; |
0b9afede AW |
2097 | if (swiotlb_late_init_with_default_size(64 * (1<<20)) != 0) |
2098 | panic("Unable to find SBA IOMMU or initialize " | |
2099 | "software I/O TLB: Try machvec=dig boot option"); | |
2100 | machvec_init("dig"); | |
2101 | #else | |
2102 | panic("Unable to find SBA IOMMU: Try a generic or DIG kernel"); | |
2103 | #endif | |
1da177e4 | 2104 | return 0; |
0b9afede AW |
2105 | } |
2106 | ||
2107 | #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_HP_ZX1_SWIOTLB) | |
2108 | /* | |
2109 | * hpzx1_swiotlb needs to have a fairly small swiotlb bounce | |
2110 | * buffer setup to support devices with smaller DMA masks than | |
2111 | * sba_iommu can handle. | |
2112 | */ | |
2113 | if (ia64_platform_is("hpzx1_swiotlb")) { | |
2114 | extern void hwsw_init(void); | |
2115 | ||
2116 | hwsw_init(); | |
2117 | } | |
2118 | #endif | |
1da177e4 LT |
2119 | |
2120 | #ifdef CONFIG_PCI | |
2121 | { | |
2122 | struct pci_bus *b = NULL; | |
2123 | while ((b = pci_find_next_bus(b)) != NULL) | |
2124 | sba_connect_bus(b); | |
2125 | } | |
2126 | #endif | |
2127 | ||
2128 | #ifdef CONFIG_PROC_FS | |
2129 | ioc_proc_init(); | |
2130 | #endif | |
2131 | return 0; | |
2132 | } | |
2133 | ||
2134 | subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */ | |
2135 | ||
1da177e4 LT |
2136 | static int __init |
2137 | nosbagart(char *str) | |
2138 | { | |
2139 | reserve_sba_gart = 0; | |
2140 | return 1; | |
2141 | } | |
2142 | ||
055bcf99 | 2143 | static int sba_dma_supported (struct device *dev, u64 mask) |
1da177e4 LT |
2144 | { |
2145 | /* make sure it's at least 32bit capable */ | |
2146 | return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL); | |
2147 | } | |
2148 | ||
055bcf99 | 2149 | static int sba_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
1da177e4 LT |
2150 | { |
2151 | return 0; | |
2152 | } | |
2153 | ||
2154 | __setup("nosbagart", nosbagart); | |
2155 | ||
2156 | static int __init | |
2157 | sba_page_override(char *str) | |
2158 | { | |
2159 | unsigned long page_size; | |
2160 | ||
2161 | page_size = memparse(str, &str); | |
2162 | switch (page_size) { | |
2163 | case 4096: | |
2164 | case 8192: | |
2165 | case 16384: | |
2166 | case 65536: | |
2167 | iovp_shift = ffs(page_size) - 1; | |
2168 | break; | |
2169 | default: | |
2170 | printk("%s: unknown/unsupported iommu page size %ld\n", | |
d4ed8084 | 2171 | __func__, page_size); |
1da177e4 LT |
2172 | } |
2173 | ||
2174 | return 1; | |
2175 | } | |
2176 | ||
2177 | __setup("sbapagesize=",sba_page_override); | |
2178 | ||
0e9cbb9b FT |
2179 | struct dma_mapping_ops sba_dma_ops = { |
2180 | .alloc_coherent = sba_alloc_coherent, | |
2181 | .free_coherent = sba_free_coherent, | |
2182 | .map_single_attrs = sba_map_single_attrs, | |
2183 | .unmap_single_attrs = sba_unmap_single_attrs, | |
2184 | .map_sg_attrs = sba_map_sg_attrs, | |
2185 | .unmap_sg_attrs = sba_unmap_sg_attrs, | |
2186 | .sync_single_for_cpu = machvec_dma_sync_single, | |
2187 | .sync_sg_for_cpu = machvec_dma_sync_sg, | |
2188 | .sync_single_for_device = machvec_dma_sync_single, | |
2189 | .sync_sg_for_device = machvec_dma_sync_sg, | |
2190 | .dma_supported_op = sba_dma_supported, | |
2191 | .mapping_error = sba_dma_mapping_error, | |
2192 | }; | |
4d9b977c FT |
2193 | |
2194 | void sba_dma_init(void) | |
2195 | { | |
2196 | dma_ops = &sba_dma_ops; | |
2197 | } |