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1da177e4 LT |
1 | /* |
2 | * File: mca.h | |
3 | * Purpose: Machine check handling specific defines | |
4 | * | |
5 | * Copyright (C) 1999, 2004 Silicon Graphics, Inc. | |
fe77efb8 HS |
6 | * Copyright (C) Vijay Chander <vijay@engr.sgi.com> |
7 | * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com> | |
8 | * Copyright (C) Russ Anderson <rja@sgi.com> | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #ifndef _ASM_IA64_MCA_H | |
12 | #define _ASM_IA64_MCA_H | |
13 | ||
1da177e4 LT |
14 | #if !defined(__ASSEMBLY__) |
15 | ||
16 | #include <linux/interrupt.h> | |
17 | #include <linux/types.h> | |
18 | ||
19 | #include <asm/param.h> | |
20 | #include <asm/sal.h> | |
21 | #include <asm/processor.h> | |
22 | #include <asm/mca_asm.h> | |
23 | ||
24 | #define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */ | |
25 | ||
26 | typedef struct ia64_fptr { | |
27 | unsigned long fp; | |
28 | unsigned long gp; | |
29 | } ia64_fptr_t; | |
30 | ||
31 | typedef union cmcv_reg_u { | |
32 | u64 cmcv_regval; | |
33 | struct { | |
34 | u64 cmcr_vector : 8; | |
35 | u64 cmcr_reserved1 : 4; | |
36 | u64 cmcr_ignored1 : 1; | |
37 | u64 cmcr_reserved2 : 3; | |
38 | u64 cmcr_mask : 1; | |
39 | u64 cmcr_ignored2 : 47; | |
40 | } cmcv_reg_s; | |
41 | ||
42 | } cmcv_reg_t; | |
43 | ||
44 | #define cmcv_mask cmcv_reg_s.cmcr_mask | |
45 | #define cmcv_vector cmcv_reg_s.cmcr_vector | |
46 | ||
47 | enum { | |
48 | IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, | |
7f613c7d KO |
49 | IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1, |
50 | IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2, | |
1612b18c | 51 | IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3, |
1da177e4 LT |
52 | }; |
53 | ||
54 | /* Information maintained by the MC infrastructure */ | |
55 | typedef struct ia64_mc_info_s { | |
56 | u64 imi_mca_handler; | |
57 | size_t imi_mca_handler_size; | |
58 | u64 imi_monarch_init_handler; | |
59 | size_t imi_monarch_init_handler_size; | |
60 | u64 imi_slave_init_handler; | |
61 | size_t imi_slave_init_handler_size; | |
62 | u8 imi_rendez_checkin[NR_CPUS]; | |
63 | ||
64 | } ia64_mc_info_t; | |
65 | ||
7f613c7d KO |
66 | /* Handover state from SAL to OS and vice versa, for both MCA and INIT events. |
67 | * Besides the handover state, it also contains some saved registers from the | |
68 | * time of the event. | |
69 | * Note: mca_asm.S depends on the precise layout of this structure. | |
70 | */ | |
71 | ||
72 | struct ia64_sal_os_state { | |
d270acbc KO |
73 | |
74 | /* SAL to OS */ | |
e088a4ad MW |
75 | unsigned long os_gp; /* GP of the os registered with the SAL, physical */ |
76 | unsigned long pal_proc; /* PAL_PROC entry point, physical */ | |
77 | unsigned long sal_proc; /* SAL_PROC entry point, physical */ | |
78 | unsigned long rv_rc; /* MCA - Rendezvous state, INIT - reason code */ | |
79 | unsigned long proc_state_param; /* from R18 */ | |
80 | unsigned long monarch; /* 1 for a monarch event, 0 for a slave */ | |
d270acbc KO |
81 | |
82 | /* common */ | |
e088a4ad MW |
83 | unsigned long sal_ra; /* Return address in SAL, physical */ |
84 | unsigned long sal_gp; /* GP of the SAL - physical */ | |
7f613c7d | 85 | pal_min_state_area_t *pal_min_state; /* from R17. physical in asm, virtual in C */ |
20bb8685 KO |
86 | /* Previous values of IA64_KR(CURRENT) and IA64_KR(CURRENT_STACK). |
87 | * Note: if the MCA/INIT recovery code wants to resume to a new context | |
88 | * then it must change these values to reflect the new kernel stack. | |
89 | */ | |
e088a4ad MW |
90 | unsigned long prev_IA64_KR_CURRENT; /* previous value of IA64_KR(CURRENT) */ |
91 | unsigned long prev_IA64_KR_CURRENT_STACK; | |
7f613c7d KO |
92 | struct task_struct *prev_task; /* previous task, NULL if it is not useful */ |
93 | /* Some interrupt registers are not saved in minstate, pt_regs or | |
94 | * switch_stack. Because MCA/INIT can occur when interrupts are | |
95 | * disabled, we need to save the additional interrupt registers over | |
96 | * MCA/INIT and resume. | |
97 | */ | |
e088a4ad MW |
98 | unsigned long isr; |
99 | unsigned long ifa; | |
100 | unsigned long itir; | |
101 | unsigned long iipa; | |
102 | unsigned long iim; | |
103 | unsigned long iha; | |
d270acbc KO |
104 | |
105 | /* OS to SAL */ | |
e088a4ad MW |
106 | unsigned long os_status; /* OS status to SAL, enum below */ |
107 | unsigned long context; /* 0 if return to same context | |
7f613c7d | 108 | 1 if return to new context */ |
9ee27c76 TI |
109 | |
110 | /* I-resources */ | |
111 | unsigned long iip; | |
112 | unsigned long ipsr; | |
113 | unsigned long ifs; | |
7f613c7d | 114 | }; |
1da177e4 LT |
115 | |
116 | enum { | |
117 | IA64_MCA_CORRECTED = 0x0, /* Error has been corrected by OS_MCA */ | |
118 | IA64_MCA_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ | |
119 | IA64_MCA_COLD_BOOT = -2, /* Cold boot of the system need from SAL */ | |
120 | IA64_MCA_HALT = -3 /* System to be halted by SAL */ | |
121 | }; | |
122 | ||
7f613c7d KO |
123 | enum { |
124 | IA64_INIT_RESUME = 0x0, /* Resume after return from INIT */ | |
125 | IA64_INIT_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ | |
126 | }; | |
127 | ||
1da177e4 LT |
128 | enum { |
129 | IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */ | |
130 | IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ | |
131 | }; | |
132 | ||
1da177e4 LT |
133 | /* Per-CPU MCA state that is too big for normal per-CPU variables. */ |
134 | ||
135 | struct ia64_mca_cpu { | |
7f613c7d | 136 | u64 mca_stack[KERNEL_STACK_SIZE/8]; |
1da177e4 | 137 | u64 init_stack[KERNEL_STACK_SIZE/8]; |
7f613c7d | 138 | }; |
1da177e4 LT |
139 | |
140 | /* Array of physical addresses of each CPU's MCA area. */ | |
141 | extern unsigned long __per_cpu_mca[NR_CPUS]; | |
142 | ||
ff741906 AR |
143 | extern int cpe_vector; |
144 | extern int ia64_cpe_irq; | |
1da177e4 | 145 | extern void ia64_mca_init(void); |
d303e9e9 | 146 | extern void ia64_mca_irq_init(void); |
1da177e4 LT |
147 | extern void ia64_mca_cpu_init(void *); |
148 | extern void ia64_os_mca_dispatch(void); | |
149 | extern void ia64_os_mca_dispatch_end(void); | |
7f613c7d KO |
150 | extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *); |
151 | extern void ia64_init_handler(struct pt_regs *, | |
152 | struct switch_stack *, | |
153 | struct ia64_sal_os_state *); | |
07a6a4ae | 154 | extern void ia64_os_init_on_kdump(void); |
1da177e4 LT |
155 | extern void ia64_monarch_init_handler(void); |
156 | extern void ia64_slave_init_handler(void); | |
157 | extern void ia64_mca_cmc_vector_setup(void); | |
7f613c7d | 158 | extern int ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)); |
1da177e4 | 159 | extern void ia64_unreg_MCA_extension(void); |
e088a4ad | 160 | extern unsigned long ia64_get_rnat(unsigned long *); |
4295ab34 | 161 | extern void ia64_set_psr_mc(void); |
ac542a51 KK |
162 | extern void ia64_mca_printk(const char * fmt, ...) |
163 | __attribute__ ((format (printf, 1, 2))); | |
7f613c7d | 164 | |
958b166c KO |
165 | struct ia64_mca_notify_die { |
166 | struct ia64_sal_os_state *sos; | |
167 | int *monarch_cpu; | |
4fa2f0e6 | 168 | int *data; |
958b166c KO |
169 | }; |
170 | ||
29763254 SH |
171 | DECLARE_PER_CPU(u64, ia64_mca_pal_base); |
172 | ||
7f613c7d KO |
173 | #else /* __ASSEMBLY__ */ |
174 | ||
175 | #define IA64_MCA_CORRECTED 0x0 /* Error has been corrected by OS_MCA */ | |
176 | #define IA64_MCA_WARM_BOOT -1 /* Warm boot of the system need from SAL */ | |
177 | #define IA64_MCA_COLD_BOOT -2 /* Cold boot of the system need from SAL */ | |
178 | #define IA64_MCA_HALT -3 /* System to be halted by SAL */ | |
179 | ||
180 | #define IA64_INIT_RESUME 0x0 /* Resume after return from INIT */ | |
181 | #define IA64_INIT_WARM_BOOT -1 /* Warm boot of the system need from SAL */ | |
182 | ||
183 | #define IA64_MCA_SAME_CONTEXT 0x0 /* SAL to return to same context */ | |
184 | #define IA64_MCA_NEW_CONTEXT -1 /* SAL to return to new context */ | |
1da177e4 LT |
185 | |
186 | #endif /* !__ASSEMBLY__ */ | |
187 | #endif /* _ASM_IA64_MCA_H */ |