[mirror_ubuntu-artful-kernel.git] / arch / ia64 / include / asm / mmu_context.h

#ifndef _ASM_IA64_MMU_CONTEXT_H
#define _ASM_IA64_MMU_CONTEXT_H

/*
 * Copyright (C) 1998-2002 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 */

/*
 * Routines to manage the allocation of task context numbers.  Task context
 * numbers are used to reduce or eliminate the need to perform TLB flushes
 * due to context switches.  Context numbers are implemented using ia-64
 * region ids.  Since the IA-64 TLB does not consider the region number when
 * performing a TLB lookup, we need to assign a unique region id to each
 * region in a process.  We use the least significant three bits in aregion
 * id for this purpose.
 */

#define IA64_REGION_ID_KERNEL	0 /* the kernel's region id (tlb.c depends on this being 0) */

#define ia64_rid(ctx,addr)	(((ctx) << 3) | (addr >> 61))

# include <asm/page.h>
# ifndef __ASSEMBLY__

#include <linux/compiler.h>
#include <linux/percpu.h>
#include <linux/sched.h>
#include <linux/mm_types.h>
#include <linux/spinlock.h>

#include <asm/processor.h>
#include <asm-generic/mm_hooks.h>

struct ia64_ctx {
	spinlock_t lock;
	unsigned int next;	/* next context number to use */
	unsigned int limit;     /* available free range */
	unsigned int max_ctx;   /* max. context value supported by all CPUs */
				/* call wrap_mmu_context when next >= max */
	unsigned long *bitmap;  /* bitmap size is max_ctx+1 */
	unsigned long *flushmap;/* pending rid to be flushed */
};

extern struct ia64_ctx ia64_ctx;
DECLARE_PER_CPU(u8, ia64_need_tlb_flush);

extern void mmu_context_init (void);
extern void wrap_mmu_context (struct mm_struct *mm);

static inline void
enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk)
{
}

/*
 * When the context counter wraps around all TLBs need to be flushed because
 * an old context number might have been reused. This is signalled by the
 * ia64_need_tlb_flush per-CPU variable, which is checked in the routine
 * below. Called by activate_mm(). <efocht@ess.nec.de>
 */
static inline void
delayed_tlb_flush (void)
{
	extern void local_flush_tlb_all (void);
	unsigned long flags;

	if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
		spin_lock_irqsave(&ia64_ctx.lock, flags);
		if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
			local_flush_tlb_all();
			__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
		}
		spin_unlock_irqrestore(&ia64_ctx.lock, flags);
	}
}

static inline nv_mm_context_t
get_mmu_context (struct mm_struct *mm)
{
	unsigned long flags;
	nv_mm_context_t context = mm->context;

	if (likely(context))
		goto out;

	spin_lock_irqsave(&ia64_ctx.lock, flags);
	/* re-check, now that we've got the lock: */
	context = mm->context;
	if (context == 0) {
		cpumask_clear(mm_cpumask(mm));
		if (ia64_ctx.next >= ia64_ctx.limit) {
			ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
					ia64_ctx.max_ctx, ia64_ctx.next);
			ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
					ia64_ctx.max_ctx, ia64_ctx.next);
			if (ia64_ctx.next >= ia64_ctx.max_ctx)
				wrap_mmu_context(mm);
		}
		mm->context = context = ia64_ctx.next++;
		__set_bit(context, ia64_ctx.bitmap);
	}
	spin_unlock_irqrestore(&ia64_ctx.lock, flags);
out:
	/*
	 * Ensure we're not starting to use "context" before any old
	 * uses of it are gone from our TLB.
	 */
	delayed_tlb_flush();

	return context;
}

/*
 * Initialize context number to some sane value.  MM is guaranteed to be a
 * brand-new address-space, so no TLB flushing is needed, ever.
 */
static inline int
init_new_context (struct task_struct *p, struct mm_struct *mm)
{
	mm->context = 0;
	return 0;
}

static inline void
destroy_context (struct mm_struct *mm)
{
	/* Nothing to do.  */
}

static inline void
reload_context (nv_mm_context_t context)
{
	unsigned long rid;
	unsigned long rid_incr = 0;
	unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;

	old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
	rid = context << 3;	/* make space for encoding the region number */
	rid_incr = 1 << 8;

	/* encode the region id, preferred page size, and VHPT enable bit: */
	rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
	rr1 = rr0 + 1*rid_incr;
	rr2 = rr0 + 2*rid_incr;
	rr3 = rr0 + 3*rid_incr;
	rr4 = rr0 + 4*rid_incr;
#ifdef  CONFIG_HUGETLB_PAGE
	rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);

#  if RGN_HPAGE != 4
#    error "reload_context assumes RGN_HPAGE is 4"
#  endif
#endif

	ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
	ia64_srlz_i();			/* srlz.i implies srlz.d */
}

/*
 * Must be called with preemption off
 */
static inline void
activate_context (struct mm_struct *mm)
{
	nv_mm_context_t context;

	do {
		context = get_mmu_context(mm);
		if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
			cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
		reload_context(context);
		/*
		 * in the unlikely event of a TLB-flush by another thread,
		 * redo the load.
		 */
	} while (unlikely(context != mm->context));
}

#define deactivate_mm(tsk,mm)	do { } while (0)

/*
 * Switch from address space PREV to address space NEXT.
 */
static inline void
activate_mm (struct mm_struct *prev, struct mm_struct *next)
{
	/*
	 * We may get interrupts here, but that's OK because interrupt
	 * handlers cannot touch user-space.
	 */
	ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
	activate_context(next);
}

#define switch_mm(prev_mm,next_mm,next_task)	activate_mm(prev_mm, next_mm)

# endif /* ! __ASSEMBLY__ */
#endif /* _ASM_IA64_MMU_CONTEXT_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_IA64_MMU_CONTEXT_H
	2	#define _ASM_IA64_MMU_CONTEXT_H
	3
	4	/*
	5	* Copyright (C) 1998-2002 Hewlett-Packard Co
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*/
	8
	9	/*
58cd9082 KC	10	* Routines to manage the allocation of task context numbers. Task context
	11	* numbers are used to reduce or eliminate the need to perform TLB flushes
	12	* due to context switches. Context numbers are implemented using ia-64
	13	* region ids. Since the IA-64 TLB does not consider the region number when
	14	* performing a TLB lookup, we need to assign a unique region id to each
	15	* region in a process. We use the least significant three bits in aregion
	16	* id for this purpose.
1da177e4 LT	17	*/
	18
	19	#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
	20
	21	#define ia64_rid(ctx,addr) (((ctx) << 3) \| (addr >> 61))
	22
0a41e250	23	# include <asm/page.h>
1da177e4 LT	24	# ifndef __ASSEMBLY__
	25
	26	#include <linux/compiler.h>
	27	#include <linux/percpu.h>
	28	#include <linux/sched.h>
589ee628	29	#include <linux/mm_types.h>
1da177e4 LT	30	#include <linux/spinlock.h>
	31
	32	#include <asm/processor.h>
d6dd61c8	33	#include <asm-generic/mm_hooks.h>
1da177e4 LT	34
	35	struct ia64_ctx {
	36	spinlock_t lock;
	37	unsigned int next; /* next context number to use */
dcc17d1b PK	38	unsigned int limit; /* available free range */
	39	unsigned int max_ctx; /* max. context value supported by all CPUs */
	40	/* call wrap_mmu_context when next >= max */
	41	unsigned long bitmap; / bitmap size is max_ctx+1 */
	42	unsigned long flushmap;/ pending rid to be flushed */
1da177e4 LT	43	};
	44
	45	extern struct ia64_ctx ia64_ctx;
	46	DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
	47
dcc17d1b	48	extern void mmu_context_init (void);
1da177e4 LT	49	extern void wrap_mmu_context (struct mm_struct *mm);
	50
	51	static inline void
	52	enter_lazy_tlb (struct mm_struct mm, struct task_struct tsk)
	53	{
	54	}
	55
	56	/*
58cd9082 KC	57	* When the context counter wraps around all TLBs need to be flushed because
	58	* an old context number might have been reused. This is signalled by the
	59	* ia64_need_tlb_flush per-CPU variable, which is checked in the routine
	60	* below. Called by activate_mm(). <efocht@ess.nec.de>
1da177e4 LT	61	*/
	62	static inline void
	63	delayed_tlb_flush (void)
	64	{
	65	extern void local_flush_tlb_all (void);
badea125	66	unsigned long flags;
1da177e4 LT	67
1da177e4 LT	68	if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
badea125	69	spin_lock_irqsave(&ia64_ctx.lock, flags);
58cd9082 KC	70	if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
	71	local_flush_tlb_all();
	72	__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
badea125 DMT	73	}
badea125 DMT	74	spin_unlock_irqrestore(&ia64_ctx.lock, flags);
1da177e4 LT	75	}
	76	}
	77
badea125	78	static inline nv_mm_context_t
1da177e4 LT	79	get_mmu_context (struct mm_struct *mm)
	80	{
	81	unsigned long flags;
badea125 DMT	82	nv_mm_context_t context = mm->context;
badea125 DMT	83
58cd9082 KC	84	if (likely(context))
	85	goto out;
	86
	87	spin_lock_irqsave(&ia64_ctx.lock, flags);
	88	/* re-check, now that we've got the lock: */
	89	context = mm->context;
	90	if (context == 0) {
5d8c39f6	91	cpumask_clear(mm_cpumask(mm));
58cd9082 KC	92	if (ia64_ctx.next >= ia64_ctx.limit) {
	93	ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
	94	ia64_ctx.max_ctx, ia64_ctx.next);
	95	ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
	96	ia64_ctx.max_ctx, ia64_ctx.next);
	97	if (ia64_ctx.next >= ia64_ctx.max_ctx)
	98	wrap_mmu_context(mm);
1da177e4	99	}
58cd9082 KC	100	mm->context = context = ia64_ctx.next++;
58cd9082 KC	101	__set_bit(context, ia64_ctx.bitmap);
1da177e4	102	}
58cd9082 KC	103	spin_unlock_irqrestore(&ia64_ctx.lock, flags);
58cd9082 KC	104	out:
badea125 DMT	105	/*
	106	* Ensure we're not starting to use "context" before any old
	107	* uses of it are gone from our TLB.
	108	*/
	109	delayed_tlb_flush();
	110
1da177e4 LT	111	return context;
	112	}
	113
	114	/*
58cd9082 KC	115	* Initialize context number to some sane value. MM is guaranteed to be a
58cd9082 KC	116	* brand-new address-space, so no TLB flushing is needed, ever.
1da177e4 LT	117	*/
	118	static inline int
	119	init_new_context (struct task_struct p, struct mm_struct mm)
	120	{
	121	mm->context = 0;
	122	return 0;
	123	}
	124
	125	static inline void
	126	destroy_context (struct mm_struct *mm)
	127	{
	128	/* Nothing to do. */
	129	}
	130
	131	static inline void
badea125	132	reload_context (nv_mm_context_t context)
1da177e4 LT	133	{
	134	unsigned long rid;
	135	unsigned long rid_incr = 0;
	136	unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
	137
0a41e250	138	old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
1da177e4 LT	139	rid = context << 3; /* make space for encoding the region number */
	140	rid_incr = 1 << 8;
	141
	142	/* encode the region id, preferred page size, and VHPT enable bit: */
	143	rr0 = (rid << 8) \| (PAGE_SHIFT << 2) \| 1;
	144	rr1 = rr0 + 1*rid_incr;
	145	rr2 = rr0 + 2*rid_incr;
	146	rr3 = rr0 + 3*rid_incr;
	147	rr4 = rr0 + 4*rid_incr;
	148	#ifdef CONFIG_HUGETLB_PAGE
	149	rr4 = (rr4 & (~(0xfcUL))) \| (old_rr4 & 0xfc);
0a41e250 PC	150
	151	# if RGN_HPAGE != 4
	152	# error "reload_context assumes RGN_HPAGE is 4"
	153	# endif
1da177e4 LT	154	#endif
1da177e4 LT	155
0e1a77cc	156	ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
1da177e4 LT	157	ia64_srlz_i(); /* srlz.i implies srlz.d */
	158	}
	159
a68db763 PC	160	/*
	161	* Must be called with preemption off
	162	*/
1da177e4 LT	163	static inline void
	164	activate_context (struct mm_struct *mm)
	165	{
badea125	166	nv_mm_context_t context;
1da177e4 LT	167
	168	do {
	169	context = get_mmu_context(mm);
5d8c39f6 RR	170	if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
5d8c39f6 RR	171	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
1da177e4	172	reload_context(context);
58cd9082 KC	173	/*
	174	* in the unlikely event of a TLB-flush by another thread,
	175	* redo the load.
	176	*/
1da177e4 LT	177	} while (unlikely(context != mm->context));
	178	}
	179
	180	#define deactivate_mm(tsk,mm) do { } while (0)
	181
	182	/*
	183	* Switch from address space PREV to address space NEXT.
	184	*/
	185	static inline void
	186	activate_mm (struct mm_struct prev, struct mm_struct next)
	187	{
1da177e4	188	/*
58cd9082 KC	189	* We may get interrupts here, but that's OK because interrupt
58cd9082 KC	190	* handlers cannot touch user-space.
1da177e4 LT	191	*/
	192	ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
	193	activate_context(next);
	194	}
	195
	196	#define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm)
	197
	198	# endif /* ! __ASSEMBLY__ */
	199	#endif /* _ASM_IA64_MMU_CONTEXT_H */