[mirror_ubuntu-artful-kernel.git] / arch / ia64 / include / asm / processor.h

#ifndef _ASM_IA64_PROCESSOR_H
#define _ASM_IA64_PROCESSOR_H

/*
 * Copyright (C) 1998-2004 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *	Stephane Eranian <eranian@hpl.hp.com>
 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
 *
 * 11/24/98	S.Eranian	added ia64_set_iva()
 * 12/03/99	D. Mosberger	implement thread_saved_pc() via kernel unwind API
 * 06/16/00	A. Mallick	added csd/ssd/tssd for ia32 support
 */


#include <asm/intrinsics.h>
#include <asm/kregs.h>
#include <asm/ptrace.h>
#include <asm/ustack.h>

#define __ARCH_WANT_UNLOCKED_CTXSW
#define ARCH_HAS_PREFETCH_SWITCH_STACK

#define IA64_NUM_PHYS_STACK_REG	96
#define IA64_NUM_DBG_REGS	8

#define DEFAULT_MAP_BASE	__IA64_UL_CONST(0x2000000000000000)
#define DEFAULT_TASK_SIZE	__IA64_UL_CONST(0xa000000000000000)

/*
 * TASK_SIZE really is a mis-named.  It really is the maximum user
 * space address (plus one).  On IA-64, there are five regions of 2TB
 * each (assuming 8KB page size), for a total of 8TB of user virtual
 * address space.
 */
#define TASK_SIZE       	DEFAULT_TASK_SIZE

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(current->thread.map_base)

#define IA64_THREAD_FPH_VALID	(__IA64_UL(1) << 0)	/* floating-point high state valid? */
#define IA64_THREAD_DBG_VALID	(__IA64_UL(1) << 1)	/* debug registers valid? */
#define IA64_THREAD_PM_VALID	(__IA64_UL(1) << 2)	/* performance registers valid? */
#define IA64_THREAD_UAC_NOPRINT	(__IA64_UL(1) << 3)	/* don't log unaligned accesses */
#define IA64_THREAD_UAC_SIGBUS	(__IA64_UL(1) << 4)	/* generate SIGBUS on unaligned acc. */
#define IA64_THREAD_MIGRATION	(__IA64_UL(1) << 5)	/* require migration
							   sync at ctx sw */
#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)	/* don't log any fpswa faults */
#define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)	/* send a SIGFPE for fpswa faults */

#define IA64_THREAD_UAC_SHIFT	3
#define IA64_THREAD_UAC_MASK	(IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
#define IA64_THREAD_FPEMU_SHIFT	6
#define IA64_THREAD_FPEMU_MASK	(IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)


/*
 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
 */
#define IA64_NSEC_PER_CYC_SHIFT	30

#ifndef __ASSEMBLY__

#include <linux/cache.h>
#include <linux/compiler.h>
#include <linux/threads.h>
#include <linux/types.h>

#include <asm/fpu.h>
#include <asm/page.h>
#include <asm/percpu.h>
#include <asm/rse.h>
#include <asm/unwind.h>
#include <linux/atomic.h>
#ifdef CONFIG_NUMA
#include <asm/nodedata.h>
#endif

/* like above but expressed as bitfields for more efficient access: */
struct ia64_psr {
	__u64 reserved0 : 1;
	__u64 be : 1;
	__u64 up : 1;
	__u64 ac : 1;
	__u64 mfl : 1;
	__u64 mfh : 1;
	__u64 reserved1 : 7;
	__u64 ic : 1;
	__u64 i : 1;
	__u64 pk : 1;
	__u64 reserved2 : 1;
	__u64 dt : 1;
	__u64 dfl : 1;
	__u64 dfh : 1;
	__u64 sp : 1;
	__u64 pp : 1;
	__u64 di : 1;
	__u64 si : 1;
	__u64 db : 1;
	__u64 lp : 1;
	__u64 tb : 1;
	__u64 rt : 1;
	__u64 reserved3 : 4;
	__u64 cpl : 2;
	__u64 is : 1;
	__u64 mc : 1;
	__u64 it : 1;
	__u64 id : 1;
	__u64 da : 1;
	__u64 dd : 1;
	__u64 ss : 1;
	__u64 ri : 2;
	__u64 ed : 1;
	__u64 bn : 1;
	__u64 reserved4 : 19;
};

union ia64_isr {
	__u64  val;
	struct {
		__u64 code : 16;
		__u64 vector : 8;
		__u64 reserved1 : 8;
		__u64 x : 1;
		__u64 w : 1;
		__u64 r : 1;
		__u64 na : 1;
		__u64 sp : 1;
		__u64 rs : 1;
		__u64 ir : 1;
		__u64 ni : 1;
		__u64 so : 1;
		__u64 ei : 2;
		__u64 ed : 1;
		__u64 reserved2 : 20;
	};
};

union ia64_lid {
	__u64 val;
	struct {
		__u64  rv  : 16;
		__u64  eid : 8;
		__u64  id  : 8;
		__u64  ig  : 32;
	};
};

union ia64_tpr {
	__u64 val;
	struct {
		__u64 ig0 : 4;
		__u64 mic : 4;
		__u64 rsv : 8;
		__u64 mmi : 1;
		__u64 ig1 : 47;
	};
};

union ia64_itir {
	__u64 val;
	struct {
		__u64 rv3  :  2; /* 0-1 */
		__u64 ps   :  6; /* 2-7 */
		__u64 key  : 24; /* 8-31 */
		__u64 rv4  : 32; /* 32-63 */
	};
};

union  ia64_rr {
	__u64 val;
	struct {
		__u64  ve	:  1;  /* enable hw walker */
		__u64  reserved0:  1;  /* reserved */
		__u64  ps	:  6;  /* log page size */
		__u64  rid	: 24;  /* region id */
		__u64  reserved1: 32;  /* reserved */
	};
};

/*
 * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 * state comes earlier:
 */
struct cpuinfo_ia64 {
	unsigned int softirq_pending;
	unsigned long itm_delta;	/* # of clock cycles between clock ticks */
	unsigned long itm_next;		/* interval timer mask value to use for next clock tick */
	unsigned long nsec_per_cyc;	/* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
	unsigned long unimpl_va_mask;	/* mask of unimplemented virtual address bits (from PAL) */
	unsigned long unimpl_pa_mask;	/* mask of unimplemented physical address bits (from PAL) */
	unsigned long itc_freq;		/* frequency of ITC counter */
	unsigned long proc_freq;	/* frequency of processor */
	unsigned long cyc_per_usec;	/* itc_freq/1000000 */
	unsigned long ptce_base;
	unsigned int ptce_count[2];
	unsigned int ptce_stride[2];
	struct task_struct *ksoftirqd;	/* kernel softirq daemon for this CPU */

#ifdef CONFIG_SMP
	unsigned long loops_per_jiffy;
	int cpu;
	unsigned int socket_id;	/* physical processor socket id */
	unsigned short core_id;	/* core id */
	unsigned short thread_id; /* thread id */
	unsigned short num_log;	/* Total number of logical processors on
				 * this socket that were successfully booted */
	unsigned char cores_per_socket;	/* Cores per processor socket */
	unsigned char threads_per_core;	/* Threads per core */
#endif

	/* CPUID-derived information: */
	unsigned long ppn;
	unsigned long features;
	unsigned char number;
	unsigned char revision;
	unsigned char model;
	unsigned char family;
	unsigned char archrev;
	char vendor[16];
	char *model_name;

#ifdef CONFIG_NUMA
	struct ia64_node_data *node_data;
#endif
};

DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);

/*
 * The "local" data variable.  It refers to the per-CPU data of the currently executing
 * CPU, much like "current" points to the per-task data of the currently executing task.
 * Do not use the address of local_cpu_data, since it will be different from
 * cpu_data(smp_processor_id())!
 */
#define local_cpu_data		(&__ia64_per_cpu_var(ia64_cpu_info))
#define cpu_data(cpu)		(&per_cpu(ia64_cpu_info, cpu))

extern void print_cpu_info (struct cpuinfo_ia64 *);

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define SET_UNALIGN_CTL(task,value)								\
({												\
	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)			\
				| (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK));	\
	0;											\
})
#define GET_UNALIGN_CTL(task,addr)								\
({												\
	put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,	\
		 (int __user *) (addr));							\
})

#define SET_FPEMU_CTL(task,value)								\
({												\
	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)		\
			  | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));	\
	0;											\
})
#define GET_FPEMU_CTL(task,addr)								\
({												\
	put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,	\
		 (int __user *) (addr));							\
})

struct thread_struct {
	__u32 flags;			/* various thread flags (see IA64_THREAD_*) */
	/* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
	__u8 on_ustack;			/* executing on user-stacks? */
	__u8 pad[3];
	__u64 ksp;			/* kernel stack pointer */
	__u64 map_base;			/* base address for get_unmapped_area() */
	__u64 rbs_bot;			/* the base address for the RBS */
	int last_fph_cpu;		/* CPU that may hold the contents of f32-f127 */

#ifdef CONFIG_PERFMON
	void *pfm_context;		     /* pointer to detailed PMU context */
	unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
# define INIT_THREAD_PM		.pfm_context =		NULL,     \
				.pfm_needs_checking =	0UL,
#else
# define INIT_THREAD_PM
#endif
	unsigned long dbr[IA64_NUM_DBG_REGS];
	unsigned long ibr[IA64_NUM_DBG_REGS];
	struct ia64_fpreg fph[96];	/* saved/loaded on demand */
};

#define INIT_THREAD {						\
	.flags =	0,					\
	.on_ustack =	0,					\
	.ksp =		0,					\
	.map_base =	DEFAULT_MAP_BASE,			\
	.rbs_bot =	STACK_TOP - DEFAULT_USER_STACK_SIZE,	\
	.last_fph_cpu =  -1,					\
	INIT_THREAD_PM						\
	.dbr =		{0, },					\
	.ibr =		{0, },					\
	.fph =		{{{{0}}}, }				\
}

#define start_thread(regs,new_ip,new_sp) do {							\
	regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))		\
			 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));		\
	regs->cr_iip = new_ip;									\
	regs->ar_rsc = 0xf;		/* eager mode, privilege level 3 */			\
	regs->ar_rnat = 0;									\
	regs->ar_bspstore = current->thread.rbs_bot;						\
	regs->ar_fpsr = FPSR_DEFAULT;								\
	regs->loadrs = 0;									\
	regs->r8 = get_dumpable(current->mm);	/* set "don't zap registers" flag */		\
	regs->r12 = new_sp - 16;	/* allocate 16 byte scratch area */			\
	if (unlikely(!get_dumpable(current->mm))) {							\
		/*										\
		 * Zap scratch regs to avoid leaking bits between processes with different	\
		 * uid/privileges.								\
		 */										\
		regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;					\
		regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;	\
	}											\
} while (0)

/* Forward declarations, a strange C thing... */
struct mm_struct;
struct task_struct;

/*
 * Free all resources held by a thread. This is called after the
 * parent of DEAD_TASK has collected the exit status of the task via
 * wait().
 */
#define release_thread(dead_task)

/* Get wait channel for task P.  */
extern unsigned long get_wchan (struct task_struct *p);

/* Return instruction pointer of blocked task TSK.  */
#define KSTK_EIP(tsk)					\
  ({							\
	struct pt_regs *_regs = task_pt_regs(tsk);	\
	_regs->cr_iip + ia64_psr(_regs)->ri;		\
  })

/* Return stack pointer of blocked task TSK.  */
#define KSTK_ESP(tsk)  ((tsk)->thread.ksp)

extern void ia64_getreg_unknown_kr (void);
extern void ia64_setreg_unknown_kr (void);

#define ia64_get_kr(regnum)					\
({								\
	unsigned long r = 0;					\
								\
	switch (regnum) {					\
	    case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;	\
	    case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;	\
	    case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;	\
	    case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;	\
	    case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;	\
	    case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;	\
	    case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;	\
	    case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;	\
	    default: ia64_getreg_unknown_kr(); break;		\
	}							\
	r;							\
})

#define ia64_set_kr(regnum, r) 					\
({								\
	switch (regnum) {					\
	    case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;	\
	    case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;	\
	    case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;	\
	    case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;	\
	    case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;	\
	    case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;	\
	    case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;	\
	    case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;	\
	    default: ia64_setreg_unknown_kr(); break;		\
	}							\
})

/*
 * The following three macros can't be inline functions because we don't have struct
 * task_struct at this point.
 */

/*
 * Return TRUE if task T owns the fph partition of the CPU we're running on.
 * Must be called from code that has preemption disabled.
 */
#define ia64_is_local_fpu_owner(t)								\
({												\
	struct task_struct *__ia64_islfo_task = (t);						\
	(__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()				\
	 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));	\
})

/*
 * Mark task T as owning the fph partition of the CPU we're running on.
 * Must be called from code that has preemption disabled.
 */
#define ia64_set_local_fpu_owner(t) do {						\
	struct task_struct *__ia64_slfo_task = (t);					\
	__ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();			\
	ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);		\
} while (0)

/* Mark the fph partition of task T as being invalid on all CPUs.  */
#define ia64_drop_fpu(t)	((t)->thread.last_fph_cpu = -1)

extern void __ia64_init_fpu (void);
extern void __ia64_save_fpu (struct ia64_fpreg *fph);
extern void __ia64_load_fpu (struct ia64_fpreg *fph);
extern void ia64_save_debug_regs (unsigned long *save_area);
extern void ia64_load_debug_regs (unsigned long *save_area);

#define ia64_fph_enable()	do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
#define ia64_fph_disable()	do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)

/* load fp 0.0 into fph */
static inline void
ia64_init_fpu (void) {
	ia64_fph_enable();
	__ia64_init_fpu();
	ia64_fph_disable();
}

/* save f32-f127 at FPH */
static inline void
ia64_save_fpu (struct ia64_fpreg *fph) {
	ia64_fph_enable();
	__ia64_save_fpu(fph);
	ia64_fph_disable();
}

/* load f32-f127 from FPH */
static inline void
ia64_load_fpu (struct ia64_fpreg *fph) {
	ia64_fph_enable();
	__ia64_load_fpu(fph);
	ia64_fph_disable();
}

static inline __u64
ia64_clear_ic (void)
{
	__u64 psr;
	psr = ia64_getreg(_IA64_REG_PSR);
	ia64_stop();
	ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
	ia64_srlz_i();
	return psr;
}

/*
 * Restore the psr.
 */
static inline void
ia64_set_psr (__u64 psr)
{
	ia64_stop();
	ia64_setreg(_IA64_REG_PSR_L, psr);
	ia64_srlz_i();
}

/*
 * Insert a translation into an instruction and/or data translation
 * register.
 */
static inline void
ia64_itr (__u64 target_mask, __u64 tr_num,
	  __u64 vmaddr, __u64 pte,
	  __u64 log_page_size)
{
	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	ia64_stop();
	if (target_mask & 0x1)
		ia64_itri(tr_num, pte);
	if (target_mask & 0x2)
		ia64_itrd(tr_num, pte);
}

/*
 * Insert a translation into the instruction and/or data translation
 * cache.
 */
static inline void
ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
	  __u64 log_page_size)
{
	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	ia64_stop();
	/* as per EAS2.6, itc must be the last instruction in an instruction group */
	if (target_mask & 0x1)
		ia64_itci(pte);
	if (target_mask & 0x2)
		ia64_itcd(pte);
}

/*
 * Purge a range of addresses from instruction and/or data translation
 * register(s).
 */
static inline void
ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
{
	if (target_mask & 0x1)
		ia64_ptri(vmaddr, (log_size << 2));
	if (target_mask & 0x2)
		ia64_ptrd(vmaddr, (log_size << 2));
}

/* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
static inline void
ia64_set_iva (void *ivt_addr)
{
	ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
	ia64_srlz_i();
}

/* Set the page table address and control bits.  */
static inline void
ia64_set_pta (__u64 pta)
{
	/* Note: srlz.i implies srlz.d */
	ia64_setreg(_IA64_REG_CR_PTA, pta);
	ia64_srlz_i();
}

static inline void
ia64_eoi (void)
{
	ia64_setreg(_IA64_REG_CR_EOI, 0);
	ia64_srlz_d();
}

#define cpu_relax()	ia64_hint(ia64_hint_pause)

static inline int
ia64_get_irr(unsigned int vector)
{
	unsigned int reg = vector / 64;
	unsigned int bit = vector % 64;
	u64 irr;

	switch (reg) {
	case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
	case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
	case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
	case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
	}

	return test_bit(bit, &irr);
}

static inline void
ia64_set_lrr0 (unsigned long val)
{
	ia64_setreg(_IA64_REG_CR_LRR0, val);
	ia64_srlz_d();
}

static inline void
ia64_set_lrr1 (unsigned long val)
{
	ia64_setreg(_IA64_REG_CR_LRR1, val);
	ia64_srlz_d();
}


/*
 * Given the address to which a spill occurred, return the unat bit
 * number that corresponds to this address.
 */
static inline __u64
ia64_unat_pos (void *spill_addr)
{
	return ((__u64) spill_addr >> 3) & 0x3f;
}

/*
 * Set the NaT bit of an integer register which was spilled at address
 * SPILL_ADDR.  UNAT is the mask to be updated.
 */
static inline void
ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
{
	__u64 bit = ia64_unat_pos(spill_addr);
	__u64 mask = 1UL << bit;

	*unat = (*unat & ~mask) | (nat << bit);
}

/*
 * Return saved PC of a blocked thread.
 * Note that the only way T can block is through a call to schedule() -> switch_to().
 */
static inline unsigned long
thread_saved_pc (struct task_struct *t)
{
	struct unw_frame_info info;
	unsigned long ip;

	unw_init_from_blocked_task(&info, t);
	if (unw_unwind(&info) < 0)
		return 0;
	unw_get_ip(&info, &ip);
	return ip;
}

/*
 * Get the current instruction/program counter value.
 */
#define current_text_addr() \
	({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })

static inline __u64
ia64_get_ivr (void)
{
	__u64 r;
	ia64_srlz_d();
	r = ia64_getreg(_IA64_REG_CR_IVR);
	ia64_srlz_d();
	return r;
}

static inline void
ia64_set_dbr (__u64 regnum, __u64 value)
{
	__ia64_set_dbr(regnum, value);
#ifdef CONFIG_ITANIUM
	ia64_srlz_d();
#endif
}

static inline __u64
ia64_get_dbr (__u64 regnum)
{
	__u64 retval;

	retval = __ia64_get_dbr(regnum);
#ifdef CONFIG_ITANIUM
	ia64_srlz_d();
#endif
	return retval;
}

static inline __u64
ia64_rotr (__u64 w, __u64 n)
{
	return (w >> n) | (w << (64 - n));
}

#define ia64_rotl(w,n)	ia64_rotr((w), (64) - (n))

/*
 * Take a mapped kernel address and return the equivalent address
 * in the region 7 identity mapped virtual area.
 */
static inline void *
ia64_imva (void *addr)
{
	void *result;
	result = (void *) ia64_tpa(addr);
	return __va(result);
}

#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH
#define PREFETCH_STRIDE			L1_CACHE_BYTES

static inline void
prefetch (const void *x)
{
	 ia64_lfetch(ia64_lfhint_none, x);
}

static inline void
prefetchw (const void *x)
{
	ia64_lfetch_excl(ia64_lfhint_none, x);
}

#define spin_lock_prefetch(x)	prefetchw(x)

extern unsigned long boot_option_idle_override;

enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
			 IDLE_NOMWAIT, IDLE_POLL};

void default_idle(void);

#define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_IA64_PROCESSOR_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_IA64_PROCESSOR_H
	2	#define _ASM_IA64_PROCESSOR_H
	3
	4	/*
	5	* Copyright (C) 1998-2004 Hewlett-Packard Co
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	* Stephane Eranian <eranian@hpl.hp.com>
	8	* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
	9	* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
	10	*
	11	* 11/24/98 S.Eranian added ia64_set_iva()
	12	* 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
	13	* 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
	14	*/
	15
1da177e4 LT	16
	17	#include <asm/intrinsics.h>
	18	#include <asm/kregs.h>
	19	#include <asm/ptrace.h>
	20	#include <asm/ustack.h>
	21
c140d879 DH	22	#define __ARCH_WANT_UNLOCKED_CTXSW
	23	#define ARCH_HAS_PREFETCH_SWITCH_STACK
	24
a0776ec8	25	#define IA64_NUM_PHYS_STACK_REG 96
1da177e4	26	#define IA64_NUM_DBG_REGS 8
1da177e4 LT	27
	28	#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
	29	#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
	30
	31	/*
	32	* TASK_SIZE really is a mis-named. It really is the maximum user
	33	* space address (plus one). On IA-64, there are five regions of 2TB
	34	* each (assuming 8KB page size), for a total of 8TB of user virtual
	35	* address space.
	36	*/
c7173271	37	#define TASK_SIZE DEFAULT_TASK_SIZE
1da177e4	38
1da177e4 LT	39	/*
	40	* This decides where the kernel will search for a free chunk of vm
	41	* space during mmap's.
	42	*/
	43	#define TASK_UNMAPPED_BASE (current->thread.map_base)
	44
	45	#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
	46	#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
	47	#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
	48	#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
	49	#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
e08e6c52 BC	50	#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
e08e6c52 BC	51	sync at ctx sw */
1da177e4 LT	52	#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
	53	#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
	54
	55	#define IA64_THREAD_UAC_SHIFT 3
	56	#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT \| IA64_THREAD_UAC_SIGBUS)
	57	#define IA64_THREAD_FPEMU_SHIFT 6
	58	#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT \| IA64_THREAD_FPEMU_SIGFPE)
	59
	60
	61	/*
	62	* This shift should be large enough to be able to represent 1000000000/itc_freq with good
	63	* accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
	64	* (this will give enough slack to represent 10 seconds worth of time as a scaled number).
	65	*/
	66	#define IA64_NSEC_PER_CYC_SHIFT 30
	67
	68	#ifndef __ASSEMBLY__
	69
	70	#include <linux/cache.h>
	71	#include <linux/compiler.h>
	72	#include <linux/threads.h>
	73	#include <linux/types.h>
	74
	75	#include <asm/fpu.h>
	76	#include <asm/page.h>
	77	#include <asm/percpu.h>
	78	#include <asm/rse.h>
	79	#include <asm/unwind.h>
60063497	80	#include <linux/atomic.h>
1da177e4 LT	81	#ifdef CONFIG_NUMA
	82	#include <asm/nodedata.h>
	83	#endif
	84
	85	/* like above but expressed as bitfields for more efficient access: */
	86	struct ia64_psr {
	87	__u64 reserved0 : 1;
	88	__u64 be : 1;
	89	__u64 up : 1;
	90	__u64 ac : 1;
	91	__u64 mfl : 1;
	92	__u64 mfh : 1;
	93	__u64 reserved1 : 7;
	94	__u64 ic : 1;
	95	__u64 i : 1;
	96	__u64 pk : 1;
	97	__u64 reserved2 : 1;
	98	__u64 dt : 1;
	99	__u64 dfl : 1;
	100	__u64 dfh : 1;
	101	__u64 sp : 1;
	102	__u64 pp : 1;
	103	__u64 di : 1;
	104	__u64 si : 1;
	105	__u64 db : 1;
	106	__u64 lp : 1;
	107	__u64 tb : 1;
	108	__u64 rt : 1;
	109	__u64 reserved3 : 4;
	110	__u64 cpl : 2;
	111	__u64 is : 1;
	112	__u64 mc : 1;
	113	__u64 it : 1;
	114	__u64 id : 1;
	115	__u64 da : 1;
	116	__u64 dd : 1;
	117	__u64 ss : 1;
	118	__u64 ri : 2;
	119	__u64 ed : 1;
	120	__u64 bn : 1;
	121	__u64 reserved4 : 19;
	122	};
	123
e235f345 XZ	124	union ia64_isr {
	125	__u64 val;
	126	struct {
	127	__u64 code : 16;
	128	__u64 vector : 8;
	129	__u64 reserved1 : 8;
	130	__u64 x : 1;
	131	__u64 w : 1;
	132	__u64 r : 1;
	133	__u64 na : 1;
	134	__u64 sp : 1;
	135	__u64 rs : 1;
	136	__u64 ir : 1;
	137	__u64 ni : 1;
	138	__u64 so : 1;
	139	__u64 ei : 2;
	140	__u64 ed : 1;
	141	__u64 reserved2 : 20;
	142	};
	143	};
	144
	145	union ia64_lid {
	146	__u64 val;
	147	struct {
	148	__u64 rv : 16;
	149	__u64 eid : 8;
	150	__u64 id : 8;
	151	__u64 ig : 32;
	152	};
	153	};
	154
	155	union ia64_tpr {
	156	__u64 val;
	157	struct {
	158	__u64 ig0 : 4;
	159	__u64 mic : 4;
	160	__u64 rsv : 8;
	161	__u64 mmi : 1;
	162	__u64 ig1 : 47;
	163	};
	164	};
	165
	166	union ia64_itir {
	167	__u64 val;
	168	struct {
	169	__u64 rv3 : 2; /* 0-1 */
	170	__u64 ps : 6; /* 2-7 */
	171	__u64 key : 24; /* 8-31 */
	172	__u64 rv4 : 32; /* 32-63 */
	173	};
	174	};
	175
	176	union ia64_rr {
	177	__u64 val;
	178	struct {
	179	__u64 ve : 1; /* enable hw walker */
	180	__u64 reserved0: 1; /* reserved */
	181	__u64 ps : 6; /* log page size */
	182	__u64 rid : 24; /* region id */
	183	__u64 reserved1: 32; /* reserved */
	184	};
	185	};
	186
1da177e4 LT	187	/*
	188	* CPU type, hardware bug flags, and per-CPU state. Frequently used
	189	* state comes earlier:
	190	*/
	191	struct cpuinfo_ia64 {
e088a4ad MW	192	unsigned int softirq_pending;
	193	unsigned long itm_delta; /* # of clock cycles between clock ticks */
	194	unsigned long itm_next; /* interval timer mask value to use for next clock tick */
	195	unsigned long nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
	196	unsigned long unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
	197	unsigned long unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
	198	unsigned long itc_freq; /* frequency of ITC counter */
	199	unsigned long proc_freq; /* frequency of processor */
	200	unsigned long cyc_per_usec; /* itc_freq/1000000 */
	201	unsigned long ptce_base;
	202	unsigned int ptce_count[2];
	203	unsigned int ptce_stride[2];
1da177e4 LT	204	struct task_struct ksoftirqd; / kernel softirq daemon for this CPU */
	205
	206	#ifdef CONFIG_SMP
e088a4ad	207	unsigned long loops_per_jiffy;
1da177e4	208	int cpu;
e088a4ad MW	209	unsigned int socket_id; /* physical processor socket id */
	210	unsigned short core_id; /* core id */
	211	unsigned short thread_id; /* thread id */
	212	unsigned short num_log; /* Total number of logical processors on
e927ecb0	213	* this socket that were successfully booted */
e088a4ad MW	214	unsigned char cores_per_socket; /* Cores per processor socket */
e088a4ad MW	215	unsigned char threads_per_core; /* Threads per core */
1da177e4 LT	216	#endif
	217
	218	/* CPUID-derived information: */
e088a4ad MW	219	unsigned long ppn;
	220	unsigned long features;
	221	unsigned char number;
	222	unsigned char revision;
	223	unsigned char model;
	224	unsigned char family;
	225	unsigned char archrev;
1da177e4	226	char vendor[16];
76d08bb3	227	char *model_name;
1da177e4 LT	228
	229	#ifdef CONFIG_NUMA
	230	struct ia64_node_data *node_data;
	231	#endif
	232	};
	233
877105cc	234	DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
1da177e4 LT	235
	236	/*
	237	* The "local" data variable. It refers to the per-CPU data of the currently executing
	238	* CPU, much like "current" points to the per-task data of the currently executing task.
	239	* Do not use the address of local_cpu_data, since it will be different from
	240	* cpu_data(smp_processor_id())!
	241	*/
877105cc TH	242	#define local_cpu_data (&__ia64_per_cpu_var(ia64_cpu_info))
877105cc TH	243	#define cpu_data(cpu) (&per_cpu(ia64_cpu_info, cpu))
1da177e4	244
1da177e4 LT	245	extern void print_cpu_info (struct cpuinfo_ia64 *);
	246
	247	typedef struct {
	248	unsigned long seg;
	249	} mm_segment_t;
	250
	251	#define SET_UNALIGN_CTL(task,value) \
	252	({ \
	253	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
	254	\| (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
	255	0; \
	256	})
	257	#define GET_UNALIGN_CTL(task,addr) \
	258	({ \
	259	put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
	260	(int __user *) (addr)); \
	261	})
	262
	263	#define SET_FPEMU_CTL(task,value) \
	264	({ \
	265	(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
	266	\| (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
	267	0; \
	268	})
	269	#define GET_FPEMU_CTL(task,addr) \
	270	({ \
	271	put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
	272	(int __user *) (addr)); \
	273	})
	274
1da177e4 LT	275	struct thread_struct {
	276	__u32 flags; /* various thread flags (see IA64_THREAD_) /
	277	/* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
	278	__u8 on_ustack; /* executing on user-stacks? */
	279	__u8 pad[3];
	280	__u64 ksp; /* kernel stack pointer */
	281	__u64 map_base; /* base address for get_unmapped_area() */
1da177e4 LT	282	__u64 rbs_bot; /* the base address for the RBS */
	283	int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
	284
1da177e4	285	#ifdef CONFIG_PERFMON
1da177e4 LT	286	void pfm_context; / pointer to detailed PMU context */
1da177e4 LT	287	unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
35589a8f	288	# define INIT_THREAD_PM .pfm_context = NULL, \
1da177e4 LT	289	.pfm_needs_checking = 0UL,
	290	#else
	291	# define INIT_THREAD_PM
	292	#endif
e088a4ad MW	293	unsigned long dbr[IA64_NUM_DBG_REGS];
e088a4ad MW	294	unsigned long ibr[IA64_NUM_DBG_REGS];
1da177e4 LT	295	struct ia64_fpreg fph[96]; /* saved/loaded on demand */
	296	};
	297
	298	#define INIT_THREAD { \
	299	.flags = 0, \
	300	.on_ustack = 0, \
	301	.ksp = 0, \
	302	.map_base = DEFAULT_MAP_BASE, \
	303	.rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
1da177e4	304	.last_fph_cpu = -1, \
1da177e4 LT	305	INIT_THREAD_PM \
	306	.dbr = {0, }, \
	307	.ibr = {0, }, \
	308	.fph = {{{{0}}}, } \
	309	}
	310
	311	#define start_thread(regs,new_ip,new_sp) do { \
1da177e4 LT	312	regs->cr_ipsr = ((regs->cr_ipsr \| (IA64_PSR_BITS_TO_SET \| IA64_PSR_CPL)) \
	313	& ~(IA64_PSR_BITS_TO_CLEAR \| IA64_PSR_RI \| IA64_PSR_IS)); \
	314	regs->cr_iip = new_ip; \
	315	regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
	316	regs->ar_rnat = 0; \
	317	regs->ar_bspstore = current->thread.rbs_bot; \
	318	regs->ar_fpsr = FPSR_DEFAULT; \
	319	regs->loadrs = 0; \
6c5d5238	320	regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \
1da177e4	321	regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
6c5d5238	322	if (unlikely(!get_dumpable(current->mm))) { \
1da177e4 LT	323	/* \
	324	* Zap scratch regs to avoid leaking bits between processes with different \
	325	* uid/privileges. \
	326	*/ \
	327	regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
	328	regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
	329	} \
	330	} while (0)
	331
	332	/* Forward declarations, a strange C thing... */
	333	struct mm_struct;
	334	struct task_struct;
	335
	336	/*
	337	* Free all resources held by a thread. This is called after the
	338	* parent of DEAD_TASK has collected the exit status of the task via
	339	* wait().
	340	*/
	341	#define release_thread(dead_task)
	342
1da177e4 LT	343	/* Get wait channel for task P. */
	344	extern unsigned long get_wchan (struct task_struct *p);
	345
	346	/* Return instruction pointer of blocked task TSK. */
	347	#define KSTK_EIP(tsk) \
	348	({ \
6450578f	349	struct pt_regs *_regs = task_pt_regs(tsk); \
1da177e4 LT	350	_regs->cr_iip + ia64_psr(_regs)->ri; \
	351	})
	352
	353	/* Return stack pointer of blocked task TSK. */
	354	#define KSTK_ESP(tsk) ((tsk)->thread.ksp)
	355
	356	extern void ia64_getreg_unknown_kr (void);
	357	extern void ia64_setreg_unknown_kr (void);
	358
	359	#define ia64_get_kr(regnum) \
	360	({ \
	361	unsigned long r = 0; \
	362	\
	363	switch (regnum) { \
	364	case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
	365	case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
	366	case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
	367	case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
	368	case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
	369	case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
	370	case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
	371	case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
	372	default: ia64_getreg_unknown_kr(); break; \
	373	} \
	374	r; \
	375	})
	376
	377	#define ia64_set_kr(regnum, r) \
	378	({ \
	379	switch (regnum) { \
	380	case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
	381	case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
	382	case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
	383	case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
	384	case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
	385	case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
	386	case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
	387	case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
	388	default: ia64_setreg_unknown_kr(); break; \
	389	} \
	390	})
	391
	392	/*
	393	* The following three macros can't be inline functions because we don't have struct
	394	* task_struct at this point.
	395	*/
	396
05062d96 PC	397	/*
	398	* Return TRUE if task T owns the fph partition of the CPU we're running on.
	399	* Must be called from code that has preemption disabled.
	400	*/
1da177e4 LT	401	#define ia64_is_local_fpu_owner(t) \
	402	({ \
	403	struct task_struct *__ia64_islfo_task = (t); \
	404	(__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
	405	&& __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
	406	})
	407
05062d96 PC	408	/*
	409	* Mark task T as owning the fph partition of the CPU we're running on.
	410	* Must be called from code that has preemption disabled.
	411	*/
1da177e4 LT	412	#define ia64_set_local_fpu_owner(t) do { \
	413	struct task_struct *__ia64_slfo_task = (t); \
	414	__ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
	415	ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
	416	} while (0)
	417
	418	/* Mark the fph partition of task T as being invalid on all CPUs. */
	419	#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
	420
	421	extern void __ia64_init_fpu (void);
	422	extern void __ia64_save_fpu (struct ia64_fpreg *fph);
	423	extern void __ia64_load_fpu (struct ia64_fpreg *fph);
	424	extern void ia64_save_debug_regs (unsigned long *save_area);
	425	extern void ia64_load_debug_regs (unsigned long *save_area);
	426
1da177e4 LT	427	#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
	428	#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
	429
	430	/* load fp 0.0 into fph */
	431	static inline void
	432	ia64_init_fpu (void) {
	433	ia64_fph_enable();
	434	__ia64_init_fpu();
	435	ia64_fph_disable();
	436	}
	437
	438	/* save f32-f127 at FPH */
	439	static inline void
	440	ia64_save_fpu (struct ia64_fpreg *fph) {
	441	ia64_fph_enable();
	442	__ia64_save_fpu(fph);
	443	ia64_fph_disable();
	444	}
	445
	446	/* load f32-f127 from FPH */
	447	static inline void
	448	ia64_load_fpu (struct ia64_fpreg *fph) {
	449	ia64_fph_enable();
	450	__ia64_load_fpu(fph);
	451	ia64_fph_disable();
	452	}
	453
	454	static inline __u64
	455	ia64_clear_ic (void)
	456	{
	457	__u64 psr;
	458	psr = ia64_getreg(_IA64_REG_PSR);
	459	ia64_stop();
	460	ia64_rsm(IA64_PSR_I \| IA64_PSR_IC);
	461	ia64_srlz_i();
	462	return psr;
	463	}
	464
	465	/*
	466	* Restore the psr.
	467	*/
	468	static inline void
	469	ia64_set_psr (__u64 psr)
	470	{
	471	ia64_stop();
	472	ia64_setreg(_IA64_REG_PSR_L, psr);
f00c2d36	473	ia64_srlz_i();
1da177e4 LT	474	}
	475
	476	/*
	477	* Insert a translation into an instruction and/or data translation
	478	* register.
	479	*/
	480	static inline void
	481	ia64_itr (__u64 target_mask, __u64 tr_num,
	482	__u64 vmaddr, __u64 pte,
	483	__u64 log_page_size)
	484	{
	485	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	486	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	487	ia64_stop();
	488	if (target_mask & 0x1)
	489	ia64_itri(tr_num, pte);
	490	if (target_mask & 0x2)
	491	ia64_itrd(tr_num, pte);
	492	}
	493
	494	/*
	495	* Insert a translation into the instruction and/or data translation
	496	* cache.
	497	*/
	498	static inline void
	499	ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
	500	__u64 log_page_size)
	501	{
	502	ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
	503	ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
	504	ia64_stop();
	505	/* as per EAS2.6, itc must be the last instruction in an instruction group */
	506	if (target_mask & 0x1)
	507	ia64_itci(pte);
	508	if (target_mask & 0x2)
	509	ia64_itcd(pte);
	510	}
	511
	512	/*
	513	* Purge a range of addresses from instruction and/or data translation
	514	* register(s).
	515	*/
	516	static inline void
	517	ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
	518	{
	519	if (target_mask & 0x1)
	520	ia64_ptri(vmaddr, (log_size << 2));
	521	if (target_mask & 0x2)
	522	ia64_ptrd(vmaddr, (log_size << 2));
	523	}
	524
	525	/* Set the interrupt vector address. The address must be suitably aligned (32KB). */
	526	static inline void
	527	ia64_set_iva (void *ivt_addr)
	528	{
	529	ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
	530	ia64_srlz_i();
	531	}
	532
	533	/* Set the page table address and control bits. */
	534	static inline void
	535	ia64_set_pta (__u64 pta)
	536	{
	537	/* Note: srlz.i implies srlz.d */
538	ia64_setreg(_IA64_REG_CR_PTA, pta);
539	ia64_srlz_i();
540	}
541
542	static inline void
543	ia64_eoi (void)
544	{
545	ia64_setreg(_IA64_REG_CR_EOI, 0);
546	ia64_srlz_d();
547	}
548
549	#define cpu_relax() ia64_hint(ia64_hint_pause)
550
a5878691 BH	551	static inline int
	552	ia64_get_irr(unsigned int vector)
	553	{
	554	unsigned int reg = vector / 64;
	555	unsigned int bit = vector % 64;
	556	u64 irr;
	557
	558	switch (reg) {
	559	case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
	560	case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
	561	case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
	562	case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
	563	}
	564
	565	return test_bit(bit, &irr);
	566	}
	567
1da177e4 LT	568	static inline void
	569	ia64_set_lrr0 (unsigned long val)
	570	{
	571	ia64_setreg(_IA64_REG_CR_LRR0, val);
	572	ia64_srlz_d();
	573	}
	574
	575	static inline void
	576	ia64_set_lrr1 (unsigned long val)
	577	{
	578	ia64_setreg(_IA64_REG_CR_LRR1, val);
	579	ia64_srlz_d();
	580	}
	581
	582
	583	/*
	584	* Given the address to which a spill occurred, return the unat bit
	585	* number that corresponds to this address.
	586	*/
	587	static inline __u64
	588	ia64_unat_pos (void *spill_addr)
	589	{
	590	return ((__u64) spill_addr >> 3) & 0x3f;
	591	}
	592
	593	/*
	594	* Set the NaT bit of an integer register which was spilled at address
	595	* SPILL_ADDR. UNAT is the mask to be updated.
	596	*/
	597	static inline void
	598	ia64_set_unat (__u64 unat, void spill_addr, unsigned long nat)
	599	{
	600	__u64 bit = ia64_unat_pos(spill_addr);
	601	__u64 mask = 1UL << bit;
	602
	603	unat = (unat & ~mask) \| (nat << bit);
	604	}
	605
	606	/*
	607	* Return saved PC of a blocked thread.
	608	* Note that the only way T can block is through a call to schedule() -> switch_to().
	609	*/
	610	static inline unsigned long
	611	thread_saved_pc (struct task_struct *t)
	612	{
	613	struct unw_frame_info info;
	614	unsigned long ip;
	615
	616	unw_init_from_blocked_task(&info, t);
	617	if (unw_unwind(&info) < 0)
	618	return 0;
	619	unw_get_ip(&info, &ip);
	620	return ip;
	621	}
	622
	623	/*
	624	* Get the current instruction/program counter value.
	625	*/
	626	#define current_text_addr() \
	627	({ void _pc; _pc = (void )ia64_getreg(_IA64_REG_IP); _pc; })
	628
	629	static inline __u64
	630	ia64_get_ivr (void)
	631	{
632	__u64 r;
633	ia64_srlz_d();
634	r = ia64_getreg(_IA64_REG_CR_IVR);
635	ia64_srlz_d();
636	return r;
637	}
638
639	static inline void
640	ia64_set_dbr (__u64 regnum, __u64 value)
641	{
642	__ia64_set_dbr(regnum, value);
643	#ifdef CONFIG_ITANIUM
644	ia64_srlz_d();
645	#endif
646	}
647
648	static inline __u64
649	ia64_get_dbr (__u64 regnum)
650	{
651	__u64 retval;
652
653	retval = __ia64_get_dbr(regnum);
654	#ifdef CONFIG_ITANIUM
655	ia64_srlz_d();
656	#endif
657	return retval;
658	}
659
660	static inline __u64
661	ia64_rotr (__u64 w, __u64 n)
662	{
663	return (w >> n) \| (w << (64 - n));
664	}
665
666	#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
667
668	/*
669	* Take a mapped kernel address and return the equivalent address
670	* in the region 7 identity mapped virtual area.
671	*/
672	static inline void *
673	ia64_imva (void *addr)
674	{
675	void *result;
676	result = (void *) ia64_tpa(addr);
677	return __va(result);
678	}
679
680	#define ARCH_HAS_PREFETCH
681	#define ARCH_HAS_PREFETCHW
682	#define ARCH_HAS_SPINLOCK_PREFETCH
683	#define PREFETCH_STRIDE L1_CACHE_BYTES
684
685	static inline void
686	prefetch (const void *x)
687	{
688	ia64_lfetch(ia64_lfhint_none, x);
689	}
690
691	static inline void
692	prefetchw (const void *x)
693	{
694	ia64_lfetch_excl(ia64_lfhint_none, x);
695	}
696
697	#define spin_lock_prefetch(x) prefetchw(x)
698
699	extern unsigned long boot_option_idle_override;
d1896049 TR	700
	701	enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
	702	IDLE_NOMWAIT, IDLE_POLL};
1da177e4	703
c140d879 DH	704	void default_idle(void);
c140d879 DH	705
f9445a38	706	#define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)
c140d879	707
1da177e4 LT	708	#endif /* !__ASSEMBLY__ */
	709
	710	#endif /* _ASM_IA64_PROCESSOR_H */