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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 1998-2004 Hewlett-Packard Co | |
3 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
4 | * Stephane Eranian <eranian@hpl.hp.com> | |
5 | * Copyright (C) 2003 Intel Co | |
6 | * Suresh Siddha <suresh.b.siddha@intel.com> | |
7 | * Fenghua Yu <fenghua.yu@intel.com> | |
8 | * Arun Sharma <arun.sharma@intel.com> | |
9 | * | |
10 | * 12/07/98 S. Eranian added pt_regs & switch_stack | |
11 | * 12/21/98 D. Mosberger updated to match latest code | |
12 | * 6/17/99 D. Mosberger added second unat member to "struct switch_stack" | |
13 | * | |
14 | */ | |
43e40f25 DH |
15 | #ifndef _ASM_IA64_PTRACE_H |
16 | #define _ASM_IA64_PTRACE_H | |
d5759641 | 17 | |
82f1b07b | 18 | #ifndef ASM_OFFSETS_C |
0013a854 | 19 | #include <asm/asm-offsets.h> |
82f1b07b | 20 | #endif |
43e40f25 | 21 | #include <uapi/asm/ptrace.h> |
1da177e4 LT |
22 | |
23 | /* | |
24 | * Base-2 logarithm of number of pages to allocate per task structure | |
25 | * (including register backing store and memory stack): | |
26 | */ | |
27 | #if defined(CONFIG_IA64_PAGE_SIZE_4KB) | |
28 | # define KERNEL_STACK_SIZE_ORDER 3 | |
29 | #elif defined(CONFIG_IA64_PAGE_SIZE_8KB) | |
30 | # define KERNEL_STACK_SIZE_ORDER 2 | |
31 | #elif defined(CONFIG_IA64_PAGE_SIZE_16KB) | |
32 | # define KERNEL_STACK_SIZE_ORDER 1 | |
33 | #else | |
34 | # define KERNEL_STACK_SIZE_ORDER 0 | |
35 | #endif | |
36 | ||
4dcc29e1 | 37 | #define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31) |
1da177e4 LT |
38 | #define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE) |
39 | ||
40 | #define KERNEL_STACK_SIZE IA64_STK_OFFSET | |
41 | ||
d5759641 | 42 | #ifndef __ASSEMBLY__ |
1da177e4 | 43 | |
d5759641 DW |
44 | #include <asm/current.h> |
45 | #include <asm/page.h> | |
46 | ||
1da177e4 LT |
47 | /* |
48 | * We use the ia64_psr(regs)->ri to determine which of the three | |
49 | * instructions in bundle (16 bytes) took the sample. Generate | |
50 | * the canonical representation by adding to instruction pointer. | |
51 | */ | |
52 | # define instruction_pointer(regs) ((regs)->cr_iip + ia64_psr(regs)->ri) | |
b3f827cb | 53 | |
cfb361f1 SL |
54 | static inline unsigned long user_stack_pointer(struct pt_regs *regs) |
55 | { | |
56 | /* FIXME: should this be bspstore + nr_dirty regs? */ | |
57 | return regs->ar_bspstore; | |
58 | } | |
59 | ||
d7e7528b EP |
60 | static inline int is_syscall_success(struct pt_regs *regs) |
61 | { | |
62 | return regs->r10 != -1; | |
63 | } | |
64 | ||
65 | static inline long regs_return_value(struct pt_regs *regs) | |
66 | { | |
67 | if (is_syscall_success(regs)) | |
68 | return regs->r8; | |
69 | else | |
70 | return -regs->r8; | |
71 | } | |
b3f827cb | 72 | |
1da177e4 LT |
73 | /* Conserve space in histogram by encoding slot bits in address |
74 | * bits 2 and 3 rather than bits 0 and 1. | |
75 | */ | |
76 | #define profile_pc(regs) \ | |
77 | ({ \ | |
78 | unsigned long __ip = instruction_pointer(regs); \ | |
79 | (__ip & ~3UL) + ((__ip & 3UL) << 2); \ | |
80 | }) | |
1ca97bb5 AV |
81 | /* |
82 | * Why not default? Because user_stack_pointer() on ia64 gives register | |
83 | * stack backing store instead... | |
84 | */ | |
85 | #define current_user_stack_pointer() (current_pt_regs()->r12) | |
1da177e4 LT |
86 | |
87 | /* given a pointer to a task_struct, return the user's pt_regs */ | |
6450578f | 88 | # define task_pt_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1) |
1da177e4 LT |
89 | # define ia64_psr(regs) ((struct ia64_psr *) &(regs)->cr_ipsr) |
90 | # define user_mode(regs) (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0) | |
91 | # define user_stack(task,regs) ((long) regs - (long) task == IA64_STK_OFFSET - sizeof(*regs)) | |
92 | # define fsys_mode(task,regs) \ | |
93 | ({ \ | |
94 | struct task_struct *_task = (task); \ | |
95 | struct pt_regs *_regs = (regs); \ | |
96 | !user_mode(_regs) && user_stack(_task, _regs); \ | |
97 | }) | |
98 | ||
99 | /* | |
100 | * System call handlers that, upon successful completion, need to return a negative value | |
101 | * should call force_successful_syscall_return() right before returning. On architectures | |
102 | * where the syscall convention provides for a separate error flag (e.g., alpha, ia64, | |
103 | * ppc{,64}, sparc{,64}, possibly others), this macro can be used to ensure that the error | |
104 | * flag will not get set. On architectures which do not support a separate error flag, | |
105 | * the macro is a no-op and the spurious error condition needs to be filtered out by some | |
106 | * other means (e.g., in user-level, by passing an extra argument to the syscall handler, | |
107 | * or something along those lines). | |
108 | * | |
109 | * On ia64, we can clear the user's pt_regs->r8 to force a successful syscall. | |
110 | */ | |
6450578f | 111 | # define force_successful_syscall_return() (task_pt_regs(current)->r8 = 0) |
1da177e4 LT |
112 | |
113 | struct task_struct; /* forward decl */ | |
114 | struct unw_frame_info; /* forward decl */ | |
115 | ||
1da177e4 LT |
116 | extern void ia64_do_show_stack (struct unw_frame_info *, void *); |
117 | extern unsigned long ia64_get_user_rbs_end (struct task_struct *, struct pt_regs *, | |
118 | unsigned long *); | |
119 | extern long ia64_peek (struct task_struct *, struct switch_stack *, unsigned long, | |
120 | unsigned long, long *); | |
121 | extern long ia64_poke (struct task_struct *, struct switch_stack *, unsigned long, | |
122 | unsigned long, long); | |
123 | extern void ia64_flush_fph (struct task_struct *); | |
124 | extern void ia64_sync_fph (struct task_struct *); | |
3b2ce0b1 | 125 | extern void ia64_sync_krbs(void); |
1da177e4 LT |
126 | extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *, |
127 | unsigned long, unsigned long); | |
128 | ||
129 | /* get nat bits for scratch registers such that bit N==1 iff scratch register rN is a NaT */ | |
130 | extern unsigned long ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat); | |
131 | /* put nat bits for scratch registers such that scratch register rN is a NaT iff bit N==1 */ | |
132 | extern unsigned long ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat); | |
133 | ||
134 | extern void ia64_increment_ip (struct pt_regs *pt); | |
135 | extern void ia64_decrement_ip (struct pt_regs *pt); | |
136 | ||
3b2ce0b1 PT |
137 | extern void ia64_ptrace_stop(void); |
138 | #define arch_ptrace_stop(code, info) \ | |
139 | ia64_ptrace_stop() | |
140 | #define arch_ptrace_stop_needed(code, info) \ | |
141 | (!test_thread_flag(TIF_RESTORE_RSE)) | |
142 | ||
aa91a2e9 PT |
143 | extern void ptrace_attach_sync_user_rbs (struct task_struct *); |
144 | #define arch_ptrace_attach(child) \ | |
145 | ptrace_attach_sync_user_rbs(child) | |
146 | ||
8db3f525 | 147 | #define arch_has_single_step() (1) |
8db3f525 | 148 | #define arch_has_block_step() (1) |
8db3f525 | 149 | |
1da177e4 | 150 | #endif /* !__ASSEMBLY__ */ |
1da177e4 | 151 | #endif /* _ASM_IA64_PTRACE_H */ |