]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
7f30491c | 2 | * R/W semaphores for ia64 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com> | |
5 | * Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com> | |
93e205a7 | 6 | * Copyright (C) 2005 Christoph Lameter <cl@linux.com> |
1da177e4 LT |
7 | * |
8 | * Based on asm-i386/rwsem.h and other architecture implementation. | |
9 | * | |
10 | * The MSW of the count is the negated number of active writers and | |
11 | * waiting lockers, and the LSW is the total number of active locks. | |
12 | * | |
13 | * The lock count is initialized to 0 (no active and no waiting lockers). | |
14 | * | |
16592d26 CL |
15 | * When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for |
16 | * the case of an uncontended lock. Readers increment by 1 and see a positive | |
17 | * value when uncontended, negative if there are writers (and maybe) readers | |
1da177e4 LT |
18 | * waiting (in which case it goes to sleep). |
19 | */ | |
20 | ||
21 | #ifndef _ASM_IA64_RWSEM_H | |
22 | #define _ASM_IA64_RWSEM_H | |
23 | ||
bd807f9c RD |
24 | #ifndef _LINUX_RWSEM_H |
25 | #error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead." | |
26 | #endif | |
27 | ||
1da177e4 LT |
28 | #include <asm/intrinsics.h> |
29 | ||
16592d26 | 30 | #define RWSEM_UNLOCKED_VALUE __IA64_UL_CONST(0x0000000000000000) |
b680f097 TL |
31 | #define RWSEM_ACTIVE_BIAS (1L) |
32 | #define RWSEM_ACTIVE_MASK (0xffffffffL) | |
33 | #define RWSEM_WAITING_BIAS (-0x100000000L) | |
1da177e4 LT |
34 | #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS |
35 | #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) | |
36 | ||
1da177e4 LT |
37 | /* |
38 | * lock for reading | |
39 | */ | |
c0905115 KT |
40 | static inline int |
41 | ___down_read (struct rw_semaphore *sem) | |
1da177e4 | 42 | { |
8ee62b18 | 43 | long result = ia64_fetchadd8_acq((unsigned long *)&sem->count.counter, 1); |
1da177e4 | 44 | |
c0905115 KT |
45 | return (result < 0); |
46 | } | |
47 | ||
48 | static inline void | |
49 | __down_read (struct rw_semaphore *sem) | |
50 | { | |
51 | if (___down_read(sem)) | |
1da177e4 LT |
52 | rwsem_down_read_failed(sem); |
53 | } | |
54 | ||
c0905115 KT |
55 | static inline int |
56 | __down_read_killable (struct rw_semaphore *sem) | |
57 | { | |
58 | if (___down_read(sem)) | |
59 | if (IS_ERR(rwsem_down_read_failed_killable(sem))) | |
60 | return -EINTR; | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
1da177e4 LT |
65 | /* |
66 | * lock for writing | |
67 | */ | |
a02137eb MH |
68 | static inline long |
69 | ___down_write (struct rw_semaphore *sem) | |
1da177e4 | 70 | { |
16592d26 | 71 | long old, new; |
1da177e4 LT |
72 | |
73 | do { | |
8ee62b18 | 74 | old = atomic_long_read(&sem->count); |
1da177e4 | 75 | new = old + RWSEM_ACTIVE_WRITE_BIAS; |
8ee62b18 | 76 | } while (atomic_long_cmpxchg_acquire(&sem->count, old, new) != old); |
1da177e4 | 77 | |
a02137eb MH |
78 | return old; |
79 | } | |
80 | ||
81 | static inline void | |
82 | __down_write (struct rw_semaphore *sem) | |
83 | { | |
84 | if (___down_write(sem)) | |
1da177e4 LT |
85 | rwsem_down_write_failed(sem); |
86 | } | |
87 | ||
a02137eb MH |
88 | static inline int |
89 | __down_write_killable (struct rw_semaphore *sem) | |
90 | { | |
c0905115 | 91 | if (___down_write(sem)) { |
a02137eb MH |
92 | if (IS_ERR(rwsem_down_write_failed_killable(sem))) |
93 | return -EINTR; | |
c0905115 | 94 | } |
a02137eb MH |
95 | |
96 | return 0; | |
97 | } | |
98 | ||
1da177e4 LT |
99 | /* |
100 | * unlock after reading | |
101 | */ | |
102 | static inline void | |
103 | __up_read (struct rw_semaphore *sem) | |
104 | { | |
8ee62b18 | 105 | long result = ia64_fetchadd8_rel((unsigned long *)&sem->count.counter, -1); |
1da177e4 LT |
106 | |
107 | if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0) | |
108 | rwsem_wake(sem); | |
109 | } | |
110 | ||
111 | /* | |
112 | * unlock after writing | |
113 | */ | |
114 | static inline void | |
115 | __up_write (struct rw_semaphore *sem) | |
116 | { | |
16592d26 | 117 | long old, new; |
1da177e4 LT |
118 | |
119 | do { | |
8ee62b18 | 120 | old = atomic_long_read(&sem->count); |
1da177e4 | 121 | new = old - RWSEM_ACTIVE_WRITE_BIAS; |
8ee62b18 | 122 | } while (atomic_long_cmpxchg_release(&sem->count, old, new) != old); |
1da177e4 LT |
123 | |
124 | if (new < 0 && (new & RWSEM_ACTIVE_MASK) == 0) | |
125 | rwsem_wake(sem); | |
126 | } | |
127 | ||
128 | /* | |
129 | * trylock for reading -- returns 1 if successful, 0 if contention | |
130 | */ | |
131 | static inline int | |
132 | __down_read_trylock (struct rw_semaphore *sem) | |
133 | { | |
16592d26 | 134 | long tmp; |
8ee62b18 JL |
135 | while ((tmp = atomic_long_read(&sem->count)) >= 0) { |
136 | if (tmp == atomic_long_cmpxchg_acquire(&sem->count, tmp, tmp+1)) { | |
1da177e4 LT |
137 | return 1; |
138 | } | |
139 | } | |
140 | return 0; | |
141 | } | |
142 | ||
143 | /* | |
144 | * trylock for writing -- returns 1 if successful, 0 if contention | |
145 | */ | |
146 | static inline int | |
147 | __down_write_trylock (struct rw_semaphore *sem) | |
148 | { | |
8ee62b18 JL |
149 | long tmp = atomic_long_cmpxchg_acquire(&sem->count, |
150 | RWSEM_UNLOCKED_VALUE, RWSEM_ACTIVE_WRITE_BIAS); | |
1da177e4 LT |
151 | return tmp == RWSEM_UNLOCKED_VALUE; |
152 | } | |
153 | ||
154 | /* | |
155 | * downgrade write lock to read lock | |
156 | */ | |
157 | static inline void | |
158 | __downgrade_write (struct rw_semaphore *sem) | |
159 | { | |
16592d26 | 160 | long old, new; |
1da177e4 LT |
161 | |
162 | do { | |
8ee62b18 | 163 | old = atomic_long_read(&sem->count); |
1da177e4 | 164 | new = old - RWSEM_WAITING_BIAS; |
8ee62b18 | 165 | } while (atomic_long_cmpxchg_release(&sem->count, old, new) != old); |
1da177e4 LT |
166 | |
167 | if (old < 0) | |
168 | rwsem_downgrade_wake(sem); | |
169 | } | |
170 | ||
1da177e4 | 171 | #endif /* _ASM_IA64_RWSEM_H */ |