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numa: ia64: use generic percpu var numa_node_id() implementation
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1da177e4 1/*
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2 * Copyright (C) 2002, Erich Focht, NEC
3 *
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef _ASM_IA64_TOPOLOGY_H
12#define _ASM_IA64_TOPOLOGY_H
13
14#include <asm/acpi.h>
15#include <asm/numa.h>
16#include <asm/smp.h>
17
18#ifdef CONFIG_NUMA
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19
20/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
21#define PENALTY_FOR_NODE_WITH_CPUS 255
22
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23/*
24 * Distance above which we begin to use zone reclaim
25 */
26#define RECLAIM_DISTANCE 15
27
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28/*
29 * Returns a bitmask of CPUs on Node 'node'.
30 */
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31#define cpumask_of_node(node) ((node) == -1 ? \
32 cpu_all_mask : \
33 &node_to_cpu_mask[node])
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34
35/*
36 * Returns the number of the node containing Node 'nid'.
37 * Not implemented here. Multi-level hierarchies detected with
38 * the help of node_distance().
39 */
40#define parent_node(nid) (nid)
41
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42/*
43 * Determines the node for a given pci bus
44 */
45#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
46
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47void build_cpu_to_node_map(void);
48
687f1661 49#define SD_CPU_INIT (struct sched_domain) { \
687f1661 50 .parent = NULL, \
1a848870 51 .child = NULL, \
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52 .groups = NULL, \
53 .min_interval = 1, \
54 .max_interval = 4, \
55 .busy_factor = 64, \
56 .imbalance_pct = 125, \
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57 .cache_nice_tries = 2, \
58 .busy_idx = 2, \
59 .idle_idx = 1, \
0ec9fab3 60 .newidle_idx = 0, \
78e7ed53 61 .wake_idx = 0, \
b8a543ea 62 .forkexec_idx = 0, \
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63 .flags = SD_LOAD_BALANCE \
64 | SD_BALANCE_NEWIDLE \
65 | SD_BALANCE_EXEC \
78e7ed53 66 | SD_BALANCE_FORK \
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67 | SD_WAKE_AFFINE, \
68 .last_balance = jiffies, \
69 .balance_interval = 1, \
70 .nr_balance_failed = 0, \
71}
72
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73/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
74#define SD_NODE_INIT (struct sched_domain) { \
1da177e4 75 .parent = NULL, \
1a848870 76 .child = NULL, \
1da177e4 77 .groups = NULL, \
687f1661 78 .min_interval = 8, \
c99dbbe9 79 .max_interval = 8*(min(num_online_cpus(), 32U)), \
687f1661 80 .busy_factor = 64, \
1da177e4 81 .imbalance_pct = 125, \
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82 .cache_nice_tries = 2, \
83 .busy_idx = 3, \
84 .idle_idx = 2, \
0ec9fab3 85 .newidle_idx = 0, \
78e7ed53 86 .wake_idx = 0, \
b8a543ea 87 .forkexec_idx = 0, \
1da177e4 88 .flags = SD_LOAD_BALANCE \
0ec9fab3 89 | SD_BALANCE_NEWIDLE \
1da177e4 90 | SD_BALANCE_EXEC \
687f1661 91 | SD_BALANCE_FORK \
c88d5910 92 | SD_SERIALIZE, \
1da177e4 93 .last_balance = jiffies, \
687f1661 94 .balance_interval = 64, \
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95 .nr_balance_failed = 0, \
96}
97
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98#endif /* CONFIG_NUMA */
99
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100#ifdef CONFIG_SMP
101#define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
102#define topology_core_id(cpu) (cpu_data(cpu)->core_id)
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103#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
104#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu))
5c45bf27 105#define smt_capable() (smp_num_siblings > 1)
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106#endif
107
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108extern void arch_fix_phys_package_id(int num, u32 slot);
109
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110#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
111 cpu_all_mask : \
36c401a4 112 cpumask_of_node(pcibus_to_node(bus)))
fbb776c3 113
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114#include <asm-generic/topology.h>
115
116#endif /* _ASM_IA64_TOPOLOGY_H */