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CRED: Use RCU to access another task's creds and to release a task's own creds
[mirror_ubuntu-zesty-kernel.git] / arch / ia64 / kernel / entry.S
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1da177e4 1/*
f30c2269 2 * arch/ia64/kernel/entry.S
1da177e4
LT		 3 *
4 * Kernel entry points.
5 *
6 * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Copyright (C) 1999, 2002-2003
9 * Asit Mallick <Asit.K.Mallick@intel.com>
10 * Don Dugger <Don.Dugger@intel.com>
11 * Suresh Siddha <suresh.b.siddha@intel.com>
12 * Fenghua Yu <fenghua.yu@intel.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 */
16/*
17 * ia64_switch_to now places correct virtual mapping in in TR2 for
18 * kernel stack. This allows us to handle interrupts without changing
19 * to physical mode.
20 *
21 * Jonathan Nicklin <nicklin@missioncriticallinux.com>
22 * Patrick O'Rourke <orourke@missioncriticallinux.com>
23 * 11/07/2000
24 */
4df8d22b
IY		 25/*
26 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
27 * VA Linux Systems Japan K.K.
28 * pv_ops.
29 */
1da177e4
LT		 30/*
31 * Global (preserved) predicate usage on syscall entry/exit path:
32 *
33 * pKStk: See entry.h.
34 * pUStk: See entry.h.
35 * pSys: See entry.h.
36 * pNonSys: !pSys
37 */
38
1da177e4
LT		 39
40#include <asm/asmmacro.h>
41#include <asm/cache.h>
42#include <asm/errno.h>
43#include <asm/kregs.h>
39e01cb8 44#include <asm/asm-offsets.h>
1da177e4
LT		 45#include <asm/pgtable.h>
46#include <asm/percpu.h>
47#include <asm/processor.h>
48#include <asm/thread_info.h>
49#include <asm/unistd.h>
50
51#include "minstate.h"
52
4df8d22b 53#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 54 /*
55 * execve() is special because in case of success, we need to
56 * setup a null register window frame.
57 */
58ENTRY(ia64_execve)
59 /*
60 * Allocate 8 input registers since ptrace() may clobber them
61 */
62 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
63 alloc loc1=ar.pfs,8,2,4,0
64 mov loc0=rp
65 .body
66 mov out0=in0 // filename
67 ;; // stop bit between alloc and call
68 mov out1=in1 // argv
69 mov out2=in2 // envp
70 add out3=16,sp // regs
71 br.call.sptk.many rp=sys_execve
72.ret0:
73#ifdef CONFIG_IA32_SUPPORT
74 /*
75 * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers
76 * from pt_regs.
77 */
78 adds r16=PT(CR_IPSR)+16,sp
79 ;;
80 ld8 r16=[r16]
81#endif
82 cmp4.ge p6,p7=r8,r0
83 mov ar.pfs=loc1 // restore ar.pfs
84 sxt4 r8=r8 // return 64-bit result
85 ;;
86 stf.spill [sp]=f0
87(p6) cmp.ne pKStk,pUStk=r0,r0 // a successful execve() lands us in user-mode...
88 mov rp=loc0
89(p6) mov ar.pfs=r0 // clear ar.pfs on success
90(p7) br.ret.sptk.many rp
91
92 /*
93 * In theory, we'd have to zap this state only to prevent leaking of
94 * security sensitive state (e.g., if current->mm->dumpable is zero). However,
95 * this executes in less than 20 cycles even on Itanium, so it's not worth
96 * optimizing for...).
97 */
98 mov ar.unat=0; mov ar.lc=0
99 mov r4=0; mov f2=f0; mov b1=r0
100 mov r5=0; mov f3=f0; mov b2=r0
101 mov r6=0; mov f4=f0; mov b3=r0
102 mov r7=0; mov f5=f0; mov b4=r0
103 ldf.fill f12=[sp]; mov f13=f0; mov b5=r0
104 ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
105 ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0
106 ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0
107 ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
108 ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0
109 ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0
110#ifdef CONFIG_IA32_SUPPORT
111 tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
112 movl loc0=ia64_ret_from_ia32_execve
113 ;;
114(p6) mov rp=loc0
115#endif
116 br.ret.sptk.many rp
117END(ia64_execve)
118
119/*
120 * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
121 * u64 tls)
122 */
123GLOBAL_ENTRY(sys_clone2)
124 /*
125 * Allocate 8 input registers since ptrace() may clobber them
126 */
127 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
128 alloc r16=ar.pfs,8,2,6,0
129 DO_SAVE_SWITCH_STACK
130 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
131 mov loc0=rp
132 mov loc1=r16 // save ar.pfs across do_fork
133 .body
134 mov out1=in1
135 mov out3=in2
136 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
137 mov out4=in3 // parent_tidptr: valid only w/CLONE_PARENT_SETTID
138 ;;
139(p6) st8 [r2]=in5 // store TLS in r16 for copy_thread()
140 mov out5=in4 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
141 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = &regs
142 mov out0=in0 // out0 = clone_flags
143 br.call.sptk.many rp=do_fork
144.ret1: .restore sp
145 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
146 mov ar.pfs=loc1
147 mov rp=loc0
148 br.ret.sptk.many rp
149END(sys_clone2)
150
151/*
152 * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
153 * Deprecated. Use sys_clone2() instead.
154 */
155GLOBAL_ENTRY(sys_clone)
156 /*
157 * Allocate 8 input registers since ptrace() may clobber them
158 */
159 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
160 alloc r16=ar.pfs,8,2,6,0
161 DO_SAVE_SWITCH_STACK
162 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
163 mov loc0=rp
164 mov loc1=r16 // save ar.pfs across do_fork
165 .body
166 mov out1=in1
167 mov out3=16 // stacksize (compensates for 16-byte scratch area)
168 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
169 mov out4=in2 // parent_tidptr: valid only w/CLONE_PARENT_SETTID
170 ;;
171(p6) st8 [r2]=in4 // store TLS in r13 (tp)
172 mov out5=in3 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
173 adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = &regs
174 mov out0=in0 // out0 = clone_flags
175 br.call.sptk.many rp=do_fork
176.ret2: .restore sp
177 adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
178 mov ar.pfs=loc1
179 mov rp=loc0
180 br.ret.sptk.many rp
181END(sys_clone)
4df8d22b 182#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
1da177e4
LT		 183
184/*
185 * prev_task <- ia64_switch_to(struct task_struct *next)
186 * With Ingo's new scheduler, interrupts are disabled when this routine gets
187 * called. The code starting at .map relies on this. The rest of the code
188 * doesn't care about the interrupt masking status.
189 */
4df8d22b 190GLOBAL_ENTRY(__paravirt_switch_to)
1da177e4
LT		 191 .prologue
192 alloc r16=ar.pfs,1,0,0,0
193 DO_SAVE_SWITCH_STACK
194 .body
195
196 adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
197 movl r25=init_task
198 mov r27=IA64_KR(CURRENT_STACK)
199 adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
200 dep r20=0,in0,61,3 // physical address of "next"
201 ;;
202 st8 [r22]=sp // save kernel stack pointer of old task
203 shr.u r26=r20,IA64_GRANULE_SHIFT
204 cmp.eq p7,p6=r25,in0
205 ;;
206 /*
207 * If we've already mapped this task's page, we can skip doing it again.
208 */
209(p6) cmp.eq p7,p6=r26,r27
210(p6) br.cond.dpnt .map
211 ;;
212.done:
1da177e4 213 ld8 sp=[r21] // load kernel stack pointer of new task
4df8d22b 214 MOV_TO_KR(CURRENT, in0, r8, r9) // update "current" application register
1da177e4
LT		 215 mov r8=r13 // return pointer to previously running task
216 mov r13=in0 // set "current" pointer
217 ;;
218 DO_LOAD_SWITCH_STACK
219
220#ifdef CONFIG_SMP
221 sync.i // ensure "fc"s done by this CPU are visible on other CPUs
222#endif
223 br.ret.sptk.many rp // boogie on out in new context
224
225.map:
4df8d22b 226 RSM_PSR_IC(r25) // interrupts (psr.i) are already disabled here
1da177e4
LT		 227 movl r25=PAGE_KERNEL
228 ;;
229 srlz.d
230 or r23=r25,r20 // construct PA | page properties
231 mov r25=IA64_GRANULE_SHIFT<<2
232 ;;
4df8d22b
IY		 233 MOV_TO_ITIR(p0, r25, r8)
234 MOV_TO_IFA(in0, r8) // VA of next task...
1da177e4
LT		 235 ;;
236 mov r25=IA64_TR_CURRENT_STACK
4df8d22b 237 MOV_TO_KR(CURRENT_STACK, r26, r8, r9) // remember last page we mapped...
1da177e4
LT		 238 ;;
239 itr.d dtr[r25]=r23 // wire in new mapping...
4df8d22b 240 SSM_PSR_IC_AND_SRLZ_D(r8, r9) // reenable the psr.ic bit
1da177e4 241 br.cond.sptk .done
4df8d22b 242END(__paravirt_switch_to)
1da177e4 243
4df8d22b 244#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 245/*
246 * Note that interrupts are enabled during save_switch_stack and load_switch_stack. This
247 * means that we may get an interrupt with "sp" pointing to the new kernel stack while
248 * ar.bspstore is still pointing to the old kernel backing store area. Since ar.rsc,
249 * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
250 * problem. Also, we don't need to specify unwind information for preserved registers
251 * that are not modified in save_switch_stack as the right unwind information is already
252 * specified at the call-site of save_switch_stack.
253 */
254
255/*
256 * save_switch_stack:
257 * - r16 holds ar.pfs
258 * - b7 holds address to return to
259 * - rp (b0) holds return address to save
260 */
261GLOBAL_ENTRY(save_switch_stack)
262 .prologue
263 .altrp b7
264 flushrs // flush dirty regs to backing store (must be first in insn group)
265 .save @priunat,r17
266 mov r17=ar.unat // preserve caller's
267 .body
268#ifdef CONFIG_ITANIUM
269 adds r2=16+128,sp
270 adds r3=16+64,sp
271 adds r14=SW(R4)+16,sp
272 ;;
273 st8.spill [r14]=r4,16 // spill r4
274 lfetch.fault.excl.nt1 [r3],128
275 ;;
276 lfetch.fault.excl.nt1 [r2],128
277 lfetch.fault.excl.nt1 [r3],128
278 ;;
279 lfetch.fault.excl [r2]
280 lfetch.fault.excl [r3]
281 adds r15=SW(R5)+16,sp
282#else
283 add r2=16+3*128,sp
284 add r3=16,sp
285 add r14=SW(R4)+16,sp
286 ;;
287 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
288 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
289 ;;
290 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
291 lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
292 ;;
293 lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
294 lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
295 adds r15=SW(R5)+16,sp
296#endif
297 ;;
298 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
299 mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0
300 add r2=SW(F2)+16,sp // r2 = &sw->f2
301 ;;
302 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
303 mov.m r18=ar.fpsr // preserve fpsr
304 add r3=SW(F3)+16,sp // r3 = &sw->f3
305 ;;
306 stf.spill [r2]=f2,32
307 mov.m r19=ar.rnat
308 mov r21=b0
309
310 stf.spill [r3]=f3,32
311 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
312 mov r22=b1
313 ;;
314 // since we're done with the spills, read and save ar.unat:
315 mov.m r29=ar.unat
316 mov.m r20=ar.bspstore
317 mov r23=b2
318 stf.spill [r2]=f4,32
319 stf.spill [r3]=f5,32
320 mov r24=b3
321 ;;
322 st8 [r14]=r21,SW(B1)-SW(B0) // save b0
323 st8 [r15]=r23,SW(B3)-SW(B2) // save b2
324 mov r25=b4
325 mov r26=b5
326 ;;
327 st8 [r14]=r22,SW(B4)-SW(B1) // save b1
328 st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3
329 mov r21=ar.lc // I-unit
330 stf.spill [r2]=f12,32
331 stf.spill [r3]=f13,32
332 ;;
333 st8 [r14]=r25,SW(B5)-SW(B4) // save b4
334 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
335 stf.spill [r2]=f14,32
336 stf.spill [r3]=f15,32
337 ;;
338 st8 [r14]=r26 // save b5
339 st8 [r15]=r21 // save ar.lc
340 stf.spill [r2]=f16,32
341 stf.spill [r3]=f17,32
342 ;;
343 stf.spill [r2]=f18,32
344 stf.spill [r3]=f19,32
345 ;;
346 stf.spill [r2]=f20,32
347 stf.spill [r3]=f21,32
348 ;;
349 stf.spill [r2]=f22,32
350 stf.spill [r3]=f23,32
351 ;;
352 stf.spill [r2]=f24,32
353 stf.spill [r3]=f25,32
354 ;;
355 stf.spill [r2]=f26,32
356 stf.spill [r3]=f27,32
357 ;;
358 stf.spill [r2]=f28,32
359 stf.spill [r3]=f29,32
360 ;;
361 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
362 stf.spill [r3]=f31,SW(PR)-SW(F31)
363 add r14=SW(CALLER_UNAT)+16,sp
364 ;;
365 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
366 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
367 mov r21=pr
368 ;;
369 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
370 st8 [r3]=r21 // save predicate registers
371 ;;
372 st8 [r2]=r20 // save ar.bspstore
373 st8 [r14]=r18 // save fpsr
374 mov ar.rsc=3 // put RSE back into eager mode, pl 0
375 br.cond.sptk.many b7
376END(save_switch_stack)
377
378/*
379 * load_switch_stack:
380 * - "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
381 * - b7 holds address to return to
382 * - must not touch r8-r11
383 */
4df8d22b 384GLOBAL_ENTRY(load_switch_stack)
1da177e4
LT		 385 .prologue
386 .altrp b7
387
388 .body
389 lfetch.fault.nt1 [sp]
390 adds r2=SW(AR_BSPSTORE)+16,sp
391 adds r3=SW(AR_UNAT)+16,sp
392 mov ar.rsc=0 // put RSE into enforced lazy mode
393 adds r14=SW(CALLER_UNAT)+16,sp
394 adds r15=SW(AR_FPSR)+16,sp
395 ;;
396 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
397 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
398 ;;
399 ld8 r21=[r2],16 // restore b0
400 ld8 r22=[r3],16 // restore b1
401 ;;
402 ld8 r23=[r2],16 // restore b2
403 ld8 r24=[r3],16 // restore b3
404 ;;
405 ld8 r25=[r2],16 // restore b4
406 ld8 r26=[r3],16 // restore b5
407 ;;
408 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
409 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
410 ;;
411 ld8 r28=[r2] // restore pr
412 ld8 r30=[r3] // restore rnat
413 ;;
414 ld8 r18=[r14],16 // restore caller's unat
415 ld8 r19=[r15],24 // restore fpsr
416 ;;
417 ldf.fill f2=[r14],32
418 ldf.fill f3=[r15],32
419 ;;
420 ldf.fill f4=[r14],32
421 ldf.fill f5=[r15],32
422 ;;
423 ldf.fill f12=[r14],32
424 ldf.fill f13=[r15],32
425 ;;
426 ldf.fill f14=[r14],32
427 ldf.fill f15=[r15],32
428 ;;
429 ldf.fill f16=[r14],32
430 ldf.fill f17=[r15],32
431 ;;
432 ldf.fill f18=[r14],32
433 ldf.fill f19=[r15],32
434 mov b0=r21
435 ;;
436 ldf.fill f20=[r14],32
437 ldf.fill f21=[r15],32
438 mov b1=r22
439 ;;
440 ldf.fill f22=[r14],32
441 ldf.fill f23=[r15],32
442 mov b2=r23
443 ;;
444 mov ar.bspstore=r27
445 mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7
446 mov b3=r24
447 ;;
448 ldf.fill f24=[r14],32
449 ldf.fill f25=[r15],32
450 mov b4=r25
451 ;;
452 ldf.fill f26=[r14],32
453 ldf.fill f27=[r15],32
454 mov b5=r26
455 ;;
456 ldf.fill f28=[r14],32
457 ldf.fill f29=[r15],32
458 mov ar.pfs=r16
459 ;;
460 ldf.fill f30=[r14],32
461 ldf.fill f31=[r15],24
462 mov ar.lc=r17
463 ;;
464 ld8.fill r4=[r14],16
465 ld8.fill r5=[r15],16
466 mov pr=r28,-1
467 ;;
468 ld8.fill r6=[r14],16
469 ld8.fill r7=[r15],16
470
471 mov ar.unat=r18 // restore caller's unat
472 mov ar.rnat=r30 // must restore after bspstore but before rsc!
473 mov ar.fpsr=r19 // restore fpsr
474 mov ar.rsc=3 // put RSE back into eager mode, pl 0
475 br.cond.sptk.many b7
476END(load_switch_stack)
477
383f2835
KC		 478GLOBAL_ENTRY(prefetch_stack)
479 add r14 = -IA64_SWITCH_STACK_SIZE, sp
480 add r15 = IA64_TASK_THREAD_KSP_OFFSET, in0
481 ;;
482 ld8 r16 = [r15] // load next's stack pointer
483 lfetch.fault.excl [r14], 128
484 ;;
485 lfetch.fault.excl [r14], 128
486 lfetch.fault [r16], 128
487 ;;
488 lfetch.fault.excl [r14], 128
489 lfetch.fault [r16], 128
490 ;;
491 lfetch.fault.excl [r14], 128
492 lfetch.fault [r16], 128
493 ;;
494 lfetch.fault.excl [r14], 128
495 lfetch.fault [r16], 128
496 ;;
497 lfetch.fault [r16], 128
498 br.ret.sptk.many rp
24b8e0cc 499END(prefetch_stack)
383f2835 500
3db03b4a 501GLOBAL_ENTRY(kernel_execve)
1da177e4
LT		 502 mov r15=__NR_execve // put syscall number in place
503 break __BREAK_SYSCALL
504 br.ret.sptk.many rp
3db03b4a 505END(kernel_execve)
1da177e4
LT		 506
507GLOBAL_ENTRY(clone)
508 mov r15=__NR_clone // put syscall number in place
509 break __BREAK_SYSCALL
510 br.ret.sptk.many rp
511END(clone)
512
513 /*
514 * Invoke a system call, but do some tracing before and after the call.
515 * We MUST preserve the current register frame throughout this routine
516 * because some system calls (such as ia64_execve) directly
517 * manipulate ar.pfs.
518 */
519GLOBAL_ENTRY(ia64_trace_syscall)
520 PT_REGS_UNWIND_INFO(0)
521 /*
522 * We need to preserve the scratch registers f6-f11 in case the system
523 * call is sigreturn.
524 */
525 adds r16=PT(F6)+16,sp
526 adds r17=PT(F7)+16,sp
527 ;;
528 stf.spill [r16]=f6,32
529 stf.spill [r17]=f7,32
530 ;;
531 stf.spill [r16]=f8,32
532 stf.spill [r17]=f9,32
533 ;;
534 stf.spill [r16]=f10
535 stf.spill [r17]=f11
536 br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
f14488cc
SL		 537 cmp.lt p6,p0=r8,r0 // check tracehook
538 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
539 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
540 mov r10=0
541(p6) br.cond.sptk strace_error // syscall failed ->
1da177e4
LT		 542 adds r16=PT(F6)+16,sp
543 adds r17=PT(F7)+16,sp
544 ;;
545 ldf.fill f6=[r16],32
546 ldf.fill f7=[r17],32
547 ;;
548 ldf.fill f8=[r16],32
549 ldf.fill f9=[r17],32
550 ;;
551 ldf.fill f10=[r16]
552 ldf.fill f11=[r17]
553 // the syscall number may have changed, so re-load it and re-calculate the
554 // syscall entry-point:
555 adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #)
556 ;;
557 ld8 r15=[r15]
558 mov r3=NR_syscalls - 1
559 ;;
560 adds r15=-1024,r15
561 movl r16=sys_call_table
562 ;;
563 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
564 cmp.leu p6,p7=r15,r3
565 ;;
566(p6) ld8 r20=[r20] // load address of syscall entry point
567(p7) movl r20=sys_ni_syscall
568 ;;
569 mov b6=r20
570 br.call.sptk.many rp=b6 // do the syscall
571.strace_check_retval:
572 cmp.lt p6,p0=r8,r0 // syscall failed?
573 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
574 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
575 mov r10=0
576(p6) br.cond.sptk strace_error // syscall failed ->
577 ;; // avoid RAW on r10
578.strace_save_retval:
579.mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
580.mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
581 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
6f6d7582
JS		 582.ret3:
583(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
38477ad7 584(pUStk) rsm psr.i // disable interrupts
4df8d22b 585 br.cond.sptk ia64_work_pending_syscall_end
1da177e4
LT		 586
587strace_error:
588 ld8 r3=[r2] // load pt_regs.r8
589 sub r9=0,r8 // negate return value to get errno value
590 ;;
591 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
592 adds r3=16,r2 // r3=&pt_regs.r10
593 ;;
594(p6) mov r10=-1
595(p6) mov r8=r9
596 br.cond.sptk .strace_save_retval
597END(ia64_trace_syscall)
598
599 /*
600 * When traced and returning from sigreturn, we invoke syscall_trace but then
601 * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
602 */
603GLOBAL_ENTRY(ia64_strace_leave_kernel)
604 PT_REGS_UNWIND_INFO(0)
605{ /*
606 * Some versions of gas generate bad unwind info if the first instruction of a
607 * procedure doesn't go into the first slot of a bundle. This is a workaround.
608 */
609 nop.m 0
610 nop.i 0
611 br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
612}
613.ret4: br.cond.sptk ia64_leave_kernel
614END(ia64_strace_leave_kernel)
615
616GLOBAL_ENTRY(ia64_ret_from_clone)
617 PT_REGS_UNWIND_INFO(0)
618{ /*
619 * Some versions of gas generate bad unwind info if the first instruction of a
620 * procedure doesn't go into the first slot of a bundle. This is a workaround.
621 */
622 nop.m 0
623 nop.i 0
624 /*
625 * We need to call schedule_tail() to complete the scheduling process.
626 * Called by ia64_switch_to() after do_fork()->copy_thread(). r8 contains the
627 * address of the previously executing task.
628 */
629 br.call.sptk.many rp=ia64_invoke_schedule_tail
630}
631.ret8:
632 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
633 ;;
634 ld4 r2=[r2]
635 ;;
636 mov r8=0
637 and r2=_TIF_SYSCALL_TRACEAUDIT,r2
638 ;;
639 cmp.ne p6,p0=r2,r0
640(p6) br.cond.spnt .strace_check_retval
641 ;; // added stop bits to prevent r8 dependency
642END(ia64_ret_from_clone)
643 // fall through
644GLOBAL_ENTRY(ia64_ret_from_syscall)
645 PT_REGS_UNWIND_INFO(0)
646 cmp.ge p6,p7=r8,r0 // syscall executed successfully?
647 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
648 mov r10=r0 // clear error indication in r10
649(p7) br.cond.spnt handle_syscall_error // handle potential syscall failure
4df8d22b
IY		 650#ifdef CONFIG_PARAVIRT
651 ;;
652 br.cond.sptk.few ia64_leave_syscall
653 ;;
654#endif /* CONFIG_PARAVIRT */
1da177e4 655END(ia64_ret_from_syscall)
4df8d22b 656#ifndef CONFIG_PARAVIRT
1da177e4 657 // fall through
4df8d22b
IY		 658#endif
659#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
660
1da177e4
LT		 661/*
662 * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
663 * need to switch to bank 0 and doesn't restore the scratch registers.
664 * To avoid leaking kernel bits, the scratch registers are set to
665 * the following known-to-be-safe values:
666 *
667 * r1: restored (global pointer)
668 * r2: cleared
669 * r3: 1 (when returning to user-level)
670 * r8-r11: restored (syscall return value(s))
671 * r12: restored (user-level stack pointer)
672 * r13: restored (user-level thread pointer)
c03f058f 673 * r14: set to __kernel_syscall_via_epc
1da177e4
LT		 674 * r15: restored (syscall #)
675 * r16-r17: cleared
676 * r18: user-level b6
677 * r19: cleared
678 * r20: user-level ar.fpsr
679 * r21: user-level b0
680 * r22: cleared
681 * r23: user-level ar.bspstore
682 * r24: user-level ar.rnat
683 * r25: user-level ar.unat
684 * r26: user-level ar.pfs
685 * r27: user-level ar.rsc
686 * r28: user-level ip
687 * r29: user-level psr
688 * r30: user-level cfm
689 * r31: user-level pr
690 * f6-f11: cleared
691 * pr: restored (user-level pr)
692 * b0: restored (user-level rp)
693 * b6: restored
c03f058f 694 * b7: set to __kernel_syscall_via_epc
1da177e4
LT		 695 * ar.unat: restored (user-level ar.unat)
696 * ar.pfs: restored (user-level ar.pfs)
697 * ar.rsc: restored (user-level ar.rsc)
698 * ar.rnat: restored (user-level ar.rnat)
699 * ar.bspstore: restored (user-level ar.bspstore)
700 * ar.fpsr: restored (user-level ar.fpsr)
701 * ar.ccv: cleared
702 * ar.csd: cleared
703 * ar.ssd: cleared
704 */
4df8d22b 705GLOBAL_ENTRY(__paravirt_leave_syscall)
1da177e4
LT		 706 PT_REGS_UNWIND_INFO(0)
707 /*
708 * work.need_resched etc. mustn't get changed by this CPU before it returns to
709 * user- or fsys-mode, hence we disable interrupts early on.
710 *
711 * p6 controls whether current_thread_info()->flags needs to be check for
712 * extra work. We always check for extra work when returning to user-level.
713 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
714 * is 0. After extra work processing has been completed, execution
4df8d22b 715 * resumes at ia64_work_processed_syscall with p6 set to 1 if the extra-work-check
1da177e4
LT		 716 * needs to be redone.
717 */
718#ifdef CONFIG_PREEMPT
4df8d22b 719 RSM_PSR_I(p0, r2, r18) // disable interrupts
1da177e4
LT		 720 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
721(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
722 ;;
723 .pred.rel.mutex pUStk,pKStk
724(pKStk) ld4 r21=[r20] // r21 <- preempt_count
725(pUStk) mov r21=0 // r21 <- 0
726 ;;
727 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
728#else /* !CONFIG_PREEMPT */
4df8d22b 729 RSM_PSR_I(pUStk, r2, r18)
1da177e4
LT		 730 cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
731(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
732#endif
4df8d22b
IY		 733.global __paravirt_work_processed_syscall;
734__paravirt_work_processed_syscall:
b64f34cd
HS		 735#ifdef CONFIG_VIRT_CPU_ACCOUNTING
736 adds r2=PT(LOADRS)+16,r12
737(pUStk) mov.m r22=ar.itc // fetch time at leave
738 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
739 ;;
740(p6) ld4 r31=[r18] // load current_thread_info()->flags
741 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
742 adds r3=PT(AR_BSPSTORE)+16,r12 // deferred
743 ;;
744#else
1da177e4
LT		 745 adds r2=PT(LOADRS)+16,r12
746 adds r3=PT(AR_BSPSTORE)+16,r12
747 adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
748 ;;
749(p6) ld4 r31=[r18] // load current_thread_info()->flags
750 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
96e01749 751 nop.i 0
1da177e4 752 ;;
b64f34cd 753#endif
87e522a0 754 mov r16=ar.bsp // M2 get existing backing store pointer
1da177e4
LT		 755 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
756(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
757 ;;
87e522a0 758 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
1da177e4
LT		 759(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
760(p6) br.cond.spnt .work_pending_syscall
761 ;;
762 // start restoring the state saved on the kernel stack (struct pt_regs):
763 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
764 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
87e522a0 765(pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
1da177e4
LT		 766 ;;
767 invala // M0|1 invalidate ALAT
4df8d22b 768 RSM_PSR_I_IC(r28, r29, r30) // M2 turn off interrupts and interruption collection
c03f058f 769 cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
1da177e4 770
c03f058f
DMT		 771 ld8 r29=[r2],16 // M0|1 load cr.ipsr
772 ld8 r28=[r3],16 // M0|1 load cr.iip
b64f34cd
HS		 773#ifdef CONFIG_VIRT_CPU_ACCOUNTING
774(pUStk) add r14=TI_AC_LEAVE+IA64_TASK_SIZE,r13
775 ;;
776 ld8 r30=[r2],16 // M0|1 load cr.ifs
777 ld8 r25=[r3],16 // M0|1 load ar.unat
778(pUStk) add r15=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
779 ;;
780#else
c03f058f 781 mov r22=r0 // A clear r22
1da177e4
LT		 782 ;;
783 ld8 r30=[r2],16 // M0|1 load cr.ifs
1da177e4 784 ld8 r25=[r3],16 // M0|1 load ar.unat
87e522a0 785(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
1da177e4 786 ;;
b64f34cd 787#endif
1da177e4 788 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
4df8d22b 789 MOV_FROM_PSR(pKStk, r22, r21) // M2 read PSR now that interrupts are disabled
87e522a0 790 nop 0
1da177e4 791 ;;
c03f058f
DMT		 792 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
793 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
794 mov f6=f0 // F clear f6
1da177e4 795 ;;
c03f058f
DMT		 796 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
797 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
798 mov f7=f0 // F clear f7
1da177e4 799 ;;
c03f058f
DMT		 800 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
801 ld8.fill r1=[r3],16 // M0|1 load r1
802(pUStk) mov r17=1 // A
1da177e4 803 ;;
b64f34cd
HS		 804#ifdef CONFIG_VIRT_CPU_ACCOUNTING
805(pUStk) st1 [r15]=r17 // M2|3
806#else
c03f058f 807(pUStk) st1 [r14]=r17 // M2|3
b64f34cd 808#endif
c03f058f
DMT		 809 ld8.fill r13=[r3],16 // M0|1
810 mov f8=f0 // F clear f8
1da177e4 811 ;;
c03f058f
DMT		 812 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
813 ld8.fill r15=[r3] // M0|1 restore r15
814 mov b6=r18 // I0 restore b6
30325d17 815
a0776ec8 816 LOAD_PHYS_STACK_REG_SIZE(r17)
c03f058f
DMT		 817 mov f9=f0 // F clear f9
818(pKStk) br.cond.dpnt.many skip_rbs_switch // B
87e522a0 819
c03f058f
DMT		 820 srlz.d // M0 ensure interruption collection is off (for cover)
821 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
4df8d22b 822 COVER // B add current frame into dirty partition & set cr.ifs
1da177e4 823 ;;
b64f34cd
HS		 824#ifdef CONFIG_VIRT_CPU_ACCOUNTING
825 mov r19=ar.bsp // M2 get new backing store pointer
826 st8 [r14]=r22 // M save time at leave
827 mov f10=f0 // F clear f10
828
829 mov r22=r0 // A clear r22
830 movl r14=__kernel_syscall_via_epc // X
831 ;;
832#else
c03f058f
DMT		 833 mov r19=ar.bsp // M2 get new backing store pointer
834 mov f10=f0 // F clear f10
96e01749
DMT		 835
836 nop.m 0
c03f058f 837 movl r14=__kernel_syscall_via_epc // X
1da177e4 838 ;;
b64f34cd 839#endif
c03f058f
DMT		 840 mov.m ar.csd=r0 // M2 clear ar.csd
841 mov.m ar.ccv=r0 // M2 clear ar.ccv
842 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
1da177e4 843
c03f058f
DMT		 844 mov.m ar.ssd=r0 // M2 clear ar.ssd
845 mov f11=f0 // F clear f11
846 br.cond.sptk.many rbs_switch // B
4df8d22b 847END(__paravirt_leave_syscall)
1da177e4 848
4df8d22b 849#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 850#ifdef CONFIG_IA32_SUPPORT
851GLOBAL_ENTRY(ia64_ret_from_ia32_execve)
852 PT_REGS_UNWIND_INFO(0)
853 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
854 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
855 ;;
856 .mem.offset 0,0
857 st8.spill [r2]=r8 // store return value in slot for r8 and set unat bit
858 .mem.offset 8,0
859 st8.spill [r3]=r0 // clear error indication in slot for r10 and set unat bit
4df8d22b
IY		 860#ifdef CONFIG_PARAVIRT
861 ;;
862 // don't fall through, ia64_leave_kernel may be #define'd
863 br.cond.sptk.few ia64_leave_kernel
864 ;;
865#endif /* CONFIG_PARAVIRT */
9df6f705 866END(ia64_ret_from_ia32_execve)
4df8d22b 867#ifndef CONFIG_PARAVIRT
1da177e4 868 // fall through
4df8d22b 869#endif
1da177e4 870#endif /* CONFIG_IA32_SUPPORT */
4df8d22b
IY		 871#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
872
873GLOBAL_ENTRY(__paravirt_leave_kernel)
1da177e4
LT		 874 PT_REGS_UNWIND_INFO(0)
875 /*
876 * work.need_resched etc. mustn't get changed by this CPU before it returns to
877 * user- or fsys-mode, hence we disable interrupts early on.
878 *
879 * p6 controls whether current_thread_info()->flags needs to be check for
880 * extra work. We always check for extra work when returning to user-level.
881 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
882 * is 0. After extra work processing has been completed, execution
883 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
884 * needs to be redone.
885 */
886#ifdef CONFIG_PREEMPT
4df8d22b 887 RSM_PSR_I(p0, r17, r31) // disable interrupts
1da177e4
LT		 888 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
889(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
890 ;;
891 .pred.rel.mutex pUStk,pKStk
892(pKStk) ld4 r21=[r20] // r21 <- preempt_count
893(pUStk) mov r21=0 // r21 <- 0
894 ;;
895 cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
896#else
4df8d22b 897 RSM_PSR_I(pUStk, r17, r31)
1da177e4
LT		 898 cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
899(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
900#endif
901.work_processed_kernel:
902 adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
903 ;;
904(p6) ld4 r31=[r17] // load current_thread_info()->flags
905 adds r21=PT(PR)+16,r12
906 ;;
907
908 lfetch [r21],PT(CR_IPSR)-PT(PR)
909 adds r2=PT(B6)+16,r12
910 adds r3=PT(R16)+16,r12
911 ;;
912 lfetch [r21]
913 ld8 r28=[r2],8 // load b6
914 adds r29=PT(R24)+16,r12
915
916 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
917 adds r30=PT(AR_CCV)+16,r12
918(p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
919 ;;
920 ld8.fill r24=[r29]
921 ld8 r15=[r30] // load ar.ccv
922(p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending?
923 ;;
924 ld8 r29=[r2],16 // load b7
925 ld8 r30=[r3],16 // load ar.csd
926(p6) br.cond.spnt .work_pending
927 ;;
928 ld8 r31=[r2],16 // load ar.ssd
929 ld8.fill r8=[r3],16
930 ;;
931 ld8.fill r9=[r2],16
932 ld8.fill r10=[r3],PT(R17)-PT(R10)
933 ;;
934 ld8.fill r11=[r2],PT(R18)-PT(R11)
935 ld8.fill r17=[r3],16
936 ;;
937 ld8.fill r18=[r2],16
938 ld8.fill r19=[r3],16
939 ;;
940 ld8.fill r20=[r2],16
941 ld8.fill r21=[r3],16
942 mov ar.csd=r30
943 mov ar.ssd=r31
944 ;;
4df8d22b 945 RSM_PSR_I_IC(r23, r22, r25) // initiate turning off of interrupt and interruption collection
1da177e4
LT		 946 invala // invalidate ALAT
947 ;;
948 ld8.fill r22=[r2],24
949 ld8.fill r23=[r3],24
950 mov b6=r28
951 ;;
952 ld8.fill r25=[r2],16
953 ld8.fill r26=[r3],16
954 mov b7=r29
955 ;;
956 ld8.fill r27=[r2],16
957 ld8.fill r28=[r3],16
958 ;;
959 ld8.fill r29=[r2],16
960 ld8.fill r30=[r3],24
961 ;;
962 ld8.fill r31=[r2],PT(F9)-PT(R31)
963 adds r3=PT(F10)-PT(F6),r3
964 ;;
965 ldf.fill f9=[r2],PT(F6)-PT(F9)
966 ldf.fill f10=[r3],PT(F8)-PT(F10)
967 ;;
968 ldf.fill f6=[r2],PT(F7)-PT(F6)
969 ;;
970 ldf.fill f7=[r2],PT(F11)-PT(F7)
971 ldf.fill f8=[r3],32
972 ;;
e7e965fa 973 srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
1da177e4
LT		 974 mov ar.ccv=r15
975 ;;
976 ldf.fill f11=[r2]
4df8d22b 977 BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
1da177e4
LT		 978 ;;
979(pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency)
980 adds r16=PT(CR_IPSR)+16,r12
981 adds r17=PT(CR_IIP)+16,r12
982
b64f34cd
HS		 983#ifdef CONFIG_VIRT_CPU_ACCOUNTING
984 .pred.rel.mutex pUStk,pKStk
4df8d22b 985 MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
b64f34cd
HS		 986(pUStk) mov.m r22=ar.itc // M fetch time at leave
987 nop.i 0
988 ;;
989#else
4df8d22b 990 MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
1da177e4
LT		 991 nop.i 0
992 nop.i 0
993 ;;
b64f34cd 994#endif
1da177e4
LT		 995 ld8 r29=[r16],16 // load cr.ipsr
996 ld8 r28=[r17],16 // load cr.iip
997 ;;
998 ld8 r30=[r16],16 // load cr.ifs
999 ld8 r25=[r17],16 // load ar.unat
1000 ;;
1001 ld8 r26=[r16],16 // load ar.pfs
1002 ld8 r27=[r17],16 // load ar.rsc
1003 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
1004 ;;
1005 ld8 r24=[r16],16 // load ar.rnat (may be garbage)
1006 ld8 r23=[r17],16 // load ar.bspstore (may be garbage)
1007 ;;
1008 ld8 r31=[r16],16 // load predicates
1009 ld8 r21=[r17],16 // load b0
1010 ;;
1011 ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
1012 ld8.fill r1=[r17],16 // load r1
1013 ;;
1014 ld8.fill r12=[r16],16
1015 ld8.fill r13=[r17],16
b64f34cd
HS		 1016#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1017(pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
1018#else
1da177e4 1019(pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
b64f34cd 1020#endif
1da177e4
LT		 1021 ;;
1022 ld8 r20=[r16],16 // ar.fpsr
1023 ld8.fill r15=[r17],16
b64f34cd
HS		 1024#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1025(pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18 // deferred
1026#endif
1da177e4
LT		 1027 ;;
1028 ld8.fill r14=[r16],16
1029 ld8.fill r2=[r17]
1030(pUStk) mov r17=1
1031 ;;
b64f34cd
HS		 1032#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1033 // mmi_ : ld8 st1 shr;; mmi_ : st8 st1 shr;;
1034 // mib : mov add br -> mib : ld8 add br
1035 // bbb_ : br nop cover;; mbb_ : mov br cover;;
1036 //
1037 // no one require bsp in r16 if (pKStk) branch is selected.
1038(pUStk) st8 [r3]=r22 // save time at leave
1039(pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
1040 shr.u r18=r19,16 // get byte size of existing "dirty" partition
1041 ;;
1042 ld8.fill r3=[r16] // deferred
1043 LOAD_PHYS_STACK_REG_SIZE(r17)
1044(pKStk) br.cond.dpnt skip_rbs_switch
1045 mov r16=ar.bsp // get existing backing store pointer
1046#else
1da177e4
LT		 1047 ld8.fill r3=[r16]
1048(pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
1049 shr.u r18=r19,16 // get byte size of existing "dirty" partition
1050 ;;
1051 mov r16=ar.bsp // get existing backing store pointer
a0776ec8 1052 LOAD_PHYS_STACK_REG_SIZE(r17)
1da177e4 1053(pKStk) br.cond.dpnt skip_rbs_switch
b64f34cd 1054#endif
1da177e4
LT		 1055
1056 /*
1057 * Restore user backing store.
1058 *
1059 * NOTE: alloc, loadrs, and cover can't be predicated.
1060 */
1061(pNonSys) br.cond.dpnt dont_preserve_current_frame
4df8d22b 1062 COVER // add current frame into dirty partition and set cr.ifs
1da177e4
LT		 1063 ;;
1064 mov r19=ar.bsp // get new backing store pointer
87e522a0 1065rbs_switch:
1da177e4
LT		 1066 sub r16=r16,r18 // krbs = old bsp - size of dirty partition
1067 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
1068 ;;
1069 sub r19=r19,r16 // calculate total byte size of dirty partition
1070 add r18=64,r18 // don't force in0-in7 into memory...
1071 ;;
1072 shl r19=r19,16 // shift size of dirty partition into loadrs position
1073 ;;
1074dont_preserve_current_frame:
1075 /*
1076 * To prevent leaking bits between the kernel and user-space,
1077 * we must clear the stacked registers in the "invalid" partition here.
1078 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
1079 * 5 registers/cycle on McKinley).
1080 */
1081# define pRecurse p6
1082# define pReturn p7
1083#ifdef CONFIG_ITANIUM
1084# define Nregs 10
1085#else
1086# define Nregs 14
1087#endif
1088 alloc loc0=ar.pfs,2,Nregs-2,2,0
1089 shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
1090 sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
1091 ;;
1092 mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
1093 shladd in0=loc1,3,r17
1094 mov in1=0
1095 ;;
1096 TEXT_ALIGN(32)
1097rse_clear_invalid:
1098#ifdef CONFIG_ITANIUM
1099 // cycle 0
1100 { .mii
1101 alloc loc0=ar.pfs,2,Nregs-2,2,0
1102 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
1103 add out0=-Nregs*8,in0
1104}{ .mfb
1105 add out1=1,in1 // increment recursion count
1106 nop.f 0
1107 nop.b 0 // can't do br.call here because of alloc (WAW on CFM)
1108 ;;
1109}{ .mfi // cycle 1
1110 mov loc1=0
1111 nop.f 0
1112 mov loc2=0
1113}{ .mib
1114 mov loc3=0
1115 mov loc4=0
1116(pRecurse) br.call.sptk.many b0=rse_clear_invalid
1117
1118}{ .mfi // cycle 2
1119 mov loc5=0
1120 nop.f 0
1121 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1122}{ .mib
1123 mov loc6=0
1124 mov loc7=0
1125(pReturn) br.ret.sptk.many b0
1126}
1127#else /* !CONFIG_ITANIUM */
1128 alloc loc0=ar.pfs,2,Nregs-2,2,0
1129 cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
1130 add out0=-Nregs*8,in0
1131 add out1=1,in1 // increment recursion count
1132 mov loc1=0
1133 mov loc2=0
1134 ;;
1135 mov loc3=0
1136 mov loc4=0
1137 mov loc5=0
1138 mov loc6=0
1139 mov loc7=0
9ec1a7ad 1140(pRecurse) br.call.dptk.few b0=rse_clear_invalid
1da177e4
LT		 1141 ;;
1142 mov loc8=0
1143 mov loc9=0
1144 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1145 mov loc10=0
1146 mov loc11=0
9ec1a7ad 1147(pReturn) br.ret.dptk.many b0
1da177e4
LT		 1148#endif /* !CONFIG_ITANIUM */
1149# undef pRecurse
1150# undef pReturn
1151 ;;
1152 alloc r17=ar.pfs,0,0,0,0 // drop current register frame
1153 ;;
1154 loadrs
1155 ;;
1156skip_rbs_switch:
1157 mov ar.unat=r25 // M2
1158(pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22
1159(pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise
1160 ;;
1161(pUStk) mov ar.bspstore=r23 // M2
1162(pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp
1163(pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise
1164 ;;
4df8d22b 1165 MOV_TO_IPSR(p0, r29, r25) // M2
1da177e4
LT		 1166 mov ar.pfs=r26 // I0
1167(pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise
1168
4df8d22b 1169 MOV_TO_IFS(p9, r30, r25)// M2
1da177e4
LT		 1170 mov b0=r21 // I0
1171(pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise
1172
1173 mov ar.fpsr=r20 // M2
4df8d22b 1174 MOV_TO_IIP(r28, r25) // M2
1da177e4
LT		 1175 nop 0
1176 ;;
1177(pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode
1178 nop 0
1179(pLvSys)mov r2=r0
1180
1181 mov ar.rsc=r27 // M2
1182 mov pr=r31,-1 // I0
4df8d22b 1183 RFI // B
1da177e4
LT		 1184
1185 /*
1186 * On entry:
1187 * r20 = &current->thread_info->pre_count (if CONFIG_PREEMPT)
1188 * r31 = current->thread_info->flags
1189 * On exit:
1190 * p6 = TRUE if work-pending-check needs to be redone
3633c730
HS		 1191 *
1192 * Interrupts are disabled on entry, reenabled depend on work, and
1193 * disabled on exit.
1da177e4
LT		 1194 */
1195.work_pending_syscall:
1196 add r2=-8,r2
1197 add r3=-8,r3
1198 ;;
1199 st8 [r2]=r8
1200 st8 [r3]=r10
1201.work_pending:
2e513fe4 1202 tbit.z p6,p0=r31,TIF_NEED_RESCHED // is resched not needed?
1da177e4
LT		 1203(p6) br.cond.sptk.few .notify
1204#ifdef CONFIG_PREEMPT
1205(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
1206 ;;
1207(pKStk) st4 [r20]=r21
1da177e4 1208#endif
4df8d22b 1209 SSM_PSR_I(p0, p6, r2) // enable interrupts
1da177e4 1210 br.call.spnt.many rp=schedule
2e513fe4 1211.ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 (re-check)
4df8d22b 1212 RSM_PSR_I(p0, r2, r20) // disable interrupts
1da177e4
LT		 1213 ;;
1214#ifdef CONFIG_PREEMPT
1215(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
1216 ;;
1217(pKStk) st4 [r20]=r0 // preempt_count() <- 0
1218#endif
4df8d22b 1219(pLvSys)br.cond.sptk.few __paravirt_pending_syscall_end
2e513fe4 1220 br.cond.sptk.many .work_processed_kernel
1da177e4
LT		 1221
1222.notify:
1223(pUStk) br.call.spnt.many rp=notify_resume_user
2e513fe4 1224.ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 (don't re-check)
4df8d22b 1225(pLvSys)br.cond.sptk.few __paravirt_pending_syscall_end
2e513fe4 1226 br.cond.sptk.many .work_processed_kernel
1da177e4 1227
4df8d22b
IY		 1228.global __paravirt_pending_syscall_end;
1229__paravirt_pending_syscall_end:
1da177e4
LT		 1230 adds r2=PT(R8)+16,r12
1231 adds r3=PT(R10)+16,r12
1232 ;;
1233 ld8 r8=[r2]
1234 ld8 r10=[r3]
4df8d22b
IY		 1235 br.cond.sptk.many __paravirt_work_processed_syscall_target
1236END(__paravirt_leave_kernel)
1da177e4 1237
4df8d22b 1238#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
1da177e4
LT		 1239ENTRY(handle_syscall_error)
1240 /*
1241 * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
1242 * lead us to mistake a negative return value as a failed syscall. Those syscall
1243 * must deposit a non-zero value in pt_regs.r8 to indicate an error. If
1244 * pt_regs.r8 is zero, we assume that the call completed successfully.
1245 */
1246 PT_REGS_UNWIND_INFO(0)
1247 ld8 r3=[r2] // load pt_regs.r8
1248 ;;
1249 cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
1250 ;;
1251(p7) mov r10=-1
1252(p7) sub r8=0,r8 // negate return value to get errno
1253 br.cond.sptk ia64_leave_syscall
1254END(handle_syscall_error)
1255
1256 /*
1257 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
1258 * in case a system call gets restarted.
1259 */
1260GLOBAL_ENTRY(ia64_invoke_schedule_tail)
1261 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1262 alloc loc1=ar.pfs,8,2,1,0
1263 mov loc0=rp
1264 mov out0=r8 // Address of previous task
1265 ;;
1266 br.call.sptk.many rp=schedule_tail
1267.ret11: mov ar.pfs=loc1
1268 mov rp=loc0
1269 br.ret.sptk.many rp
1270END(ia64_invoke_schedule_tail)
1271
1272 /*
3633c730
HS		 1273 * Setup stack and call do_notify_resume_user(), keeping interrupts
1274 * disabled.
1275 *
1276 * Note that pSys and pNonSys need to be set up by the caller.
1277 * We declare 8 input registers so the system call args get preserved,
1278 * in case we need to restart a system call.
1da177e4 1279 */
4df8d22b 1280GLOBAL_ENTRY(notify_resume_user)
1da177e4
LT		 1281 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
1282 alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
1283 mov r9=ar.unat
1284 mov loc0=rp // save return address
1285 mov out0=0 // there is no "oldset"
1286 adds out1=8,sp // out1=&sigscratch->ar_pfs
1287(pSys) mov out2=1 // out2==1 => we're in a syscall
1288 ;;
1289(pNonSys) mov out2=0 // out2==0 => not a syscall
1290 .fframe 16
bfd68594 1291 .spillsp ar.unat, 16
1da177e4
LT		 1292 st8 [sp]=r9,-16 // allocate space for ar.unat and save it
1293 st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch
1294 .body
1295 br.call.sptk.many rp=do_notify_resume_user
1296.ret15: .restore sp
1297 adds sp=16,sp // pop scratch stack space
1298 ;;
1299 ld8 r9=[sp] // load new unat from sigscratch->scratch_unat
1300 mov rp=loc0
1301 ;;
1302 mov ar.unat=r9
1303 mov ar.pfs=loc1
1304 br.ret.sptk.many rp
1305END(notify_resume_user)
1306
1da177e4
LT		 1307ENTRY(sys_rt_sigreturn)
1308 PT_REGS_UNWIND_INFO(0)
1309 /*
1310 * Allocate 8 input registers since ptrace() may clobber them
1311 */
1312 alloc r2=ar.pfs,8,0,1,0
1313 .prologue
1314 PT_REGS_SAVES(16)
1315 adds sp=-16,sp
1316 .body
1317 cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall...
1318 ;;
1319 /*
1320 * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
1321 * syscall-entry path does not save them we save them here instead. Note: we
1322 * don't need to save any other registers that are not saved by the stream-lined
1323 * syscall path, because restore_sigcontext() restores them.
1324 */
1325 adds r16=PT(F6)+32,sp
1326 adds r17=PT(F7)+32,sp
1327 ;;
1328 stf.spill [r16]=f6,32
1329 stf.spill [r17]=f7,32
1330 ;;
1331 stf.spill [r16]=f8,32
1332 stf.spill [r17]=f9,32
1333 ;;
1334 stf.spill [r16]=f10
1335 stf.spill [r17]=f11
1336 adds out0=16,sp // out0 = &sigscratch
1337 br.call.sptk.many rp=ia64_rt_sigreturn
763b3917 1338.ret19: .restore sp,0
1da177e4
LT		 1339 adds sp=16,sp
1340 ;;
1341 ld8 r9=[sp] // load new ar.unat
4df8d22b 1342 mov.sptk b7=r8,ia64_native_leave_kernel
1da177e4
LT		 1343 ;;
1344 mov ar.unat=r9
1345 br.many b7
1346END(sys_rt_sigreturn)
1347
1348GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
1349 .prologue
1350 /*
1351 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
1352 */
1353 mov r16=r0
1354 DO_SAVE_SWITCH_STACK
1355 br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt
1356.ret21: .body
1357 DO_LOAD_SWITCH_STACK
1358 br.cond.sptk.many rp // goes to ia64_leave_kernel
1359END(ia64_prepare_handle_unaligned)
1360
1361 //
1362 // unw_init_running(void (*callback)(info, arg), void *arg)
1363 //
1364# define EXTRA_FRAME_SIZE ((UNW_FRAME_INFO_SIZE+15)&~15)
1365
1366GLOBAL_ENTRY(unw_init_running)
1367 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
1368 alloc loc1=ar.pfs,2,3,3,0
1369 ;;
1370 ld8 loc2=[in0],8
1371 mov loc0=rp
1372 mov r16=loc1
1373 DO_SAVE_SWITCH_STACK
1374 .body
1375
1376 .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
1377 .fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
1378 SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
1379 adds sp=-EXTRA_FRAME_SIZE,sp
1380 .body
1381 ;;
1382 adds out0=16,sp // &info
1383 mov out1=r13 // current
1384 adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack
1385 br.call.sptk.many rp=unw_init_frame_info
13861: adds out0=16,sp // &info
1387 mov b6=loc2
1388 mov loc2=gp // save gp across indirect function call
1389 ;;
1390 ld8 gp=[in0]
1391 mov out1=in1 // arg
1392 br.call.sptk.many rp=b6 // invoke the callback function
13931: mov gp=loc2 // restore gp
1394
1395 // For now, we don't allow changing registers from within
1396 // unw_init_running; if we ever want to allow that, we'd
1397 // have to do a load_switch_stack here:
1398 .restore sp
1399 adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
1400
1401 mov ar.pfs=loc1
1402 mov rp=loc0
1403 br.ret.sptk.many rp
1404END(unw_init_running)
1405
1406 .rodata
1407 .align 8
1408 .globl sys_call_table
1409sys_call_table:
1410 data8 sys_ni_syscall // This must be sys_ni_syscall! See ivt.S.
1411 data8 sys_exit // 1025
1412 data8 sys_read
1413 data8 sys_write
1414 data8 sys_open
1415 data8 sys_close
1416 data8 sys_creat // 1030
1417 data8 sys_link
1418 data8 sys_unlink
1419 data8 ia64_execve
1420 data8 sys_chdir
1421 data8 sys_fchdir // 1035
1422 data8 sys_utimes
1423 data8 sys_mknod
1424 data8 sys_chmod
1425 data8 sys_chown
1426 data8 sys_lseek // 1040
1427 data8 sys_getpid
1428 data8 sys_getppid
1429 data8 sys_mount
1430 data8 sys_umount
1431 data8 sys_setuid // 1045
1432 data8 sys_getuid
1433 data8 sys_geteuid
1434 data8 sys_ptrace
1435 data8 sys_access
1436 data8 sys_sync // 1050
1437 data8 sys_fsync
1438 data8 sys_fdatasync
1439 data8 sys_kill
1440 data8 sys_rename
1441 data8 sys_mkdir // 1055
1442 data8 sys_rmdir
1443 data8 sys_dup
1444 data8 sys_pipe
1445 data8 sys_times
1446 data8 ia64_brk // 1060
1447 data8 sys_setgid
1448 data8 sys_getgid
1449 data8 sys_getegid
1450 data8 sys_acct
1451 data8 sys_ioctl // 1065
1452 data8 sys_fcntl
1453 data8 sys_umask
1454 data8 sys_chroot
1455 data8 sys_ustat
1456 data8 sys_dup2 // 1070
1457 data8 sys_setreuid
1458 data8 sys_setregid
1459 data8 sys_getresuid
1460 data8 sys_setresuid
1461 data8 sys_getresgid // 1075
1462 data8 sys_setresgid
1463 data8 sys_getgroups
1464 data8 sys_setgroups
1465 data8 sys_getpgid
1466 data8 sys_setpgid // 1080
1467 data8 sys_setsid
1468 data8 sys_getsid
1469 data8 sys_sethostname
1470 data8 sys_setrlimit
1471 data8 sys_getrlimit // 1085
1472 data8 sys_getrusage
1473 data8 sys_gettimeofday
1474 data8 sys_settimeofday
1475 data8 sys_select
1476 data8 sys_poll // 1090
1477 data8 sys_symlink
1478 data8 sys_readlink
1479 data8 sys_uselib
1480 data8 sys_swapon
1481 data8 sys_swapoff // 1095
1482 data8 sys_reboot
1483 data8 sys_truncate
1484 data8 sys_ftruncate
1485 data8 sys_fchmod
1486 data8 sys_fchown // 1100
1487 data8 ia64_getpriority
1488 data8 sys_setpriority
1489 data8 sys_statfs
1490 data8 sys_fstatfs
1491 data8 sys_gettid // 1105
1492 data8 sys_semget
1493 data8 sys_semop
1494 data8 sys_semctl
1495 data8 sys_msgget
1496 data8 sys_msgsnd // 1110
1497 data8 sys_msgrcv
1498 data8 sys_msgctl
1499 data8 sys_shmget
7d87e14c 1500 data8 sys_shmat
1da177e4
LT		 1501 data8 sys_shmdt // 1115
1502 data8 sys_shmctl
1503 data8 sys_syslog
1504 data8 sys_setitimer
1505 data8 sys_getitimer
1506 data8 sys_ni_syscall // 1120 /* was: ia64_oldstat */
1507 data8 sys_ni_syscall /* was: ia64_oldlstat */
1508 data8 sys_ni_syscall /* was: ia64_oldfstat */
1509 data8 sys_vhangup
1510 data8 sys_lchown
1511 data8 sys_remap_file_pages // 1125
1512 data8 sys_wait4
1513 data8 sys_sysinfo
1514 data8 sys_clone
1515 data8 sys_setdomainname
1516 data8 sys_newuname // 1130
1517 data8 sys_adjtimex
1518 data8 sys_ni_syscall /* was: ia64_create_module */
1519 data8 sys_init_module
1520 data8 sys_delete_module
1521 data8 sys_ni_syscall // 1135 /* was: sys_get_kernel_syms */
1522 data8 sys_ni_syscall /* was: sys_query_module */
1523 data8 sys_quotactl
1524 data8 sys_bdflush
1525 data8 sys_sysfs
1526 data8 sys_personality // 1140
1527 data8 sys_ni_syscall // sys_afs_syscall
1528 data8 sys_setfsuid
1529 data8 sys_setfsgid
1530 data8 sys_getdents
1531 data8 sys_flock // 1145
1532 data8 sys_readv
1533 data8 sys_writev
1534 data8 sys_pread64
1535 data8 sys_pwrite64
1536 data8 sys_sysctl // 1150
1537 data8 sys_mmap
1538 data8 sys_munmap
1539 data8 sys_mlock
1540 data8 sys_mlockall
1541 data8 sys_mprotect // 1155
1542 data8 ia64_mremap
1543 data8 sys_msync
1544 data8 sys_munlock
1545 data8 sys_munlockall
1546 data8 sys_sched_getparam // 1160
1547 data8 sys_sched_setparam
1548 data8 sys_sched_getscheduler
1549 data8 sys_sched_setscheduler
1550 data8 sys_sched_yield
1551 data8 sys_sched_get_priority_max // 1165
1552 data8 sys_sched_get_priority_min
1553 data8 sys_sched_rr_get_interval
1554 data8 sys_nanosleep
1555 data8 sys_nfsservctl
1556 data8 sys_prctl // 1170
1557 data8 sys_getpagesize
1558 data8 sys_mmap2
1559 data8 sys_pciconfig_read
1560 data8 sys_pciconfig_write
1561 data8 sys_perfmonctl // 1175
1562 data8 sys_sigaltstack
1563 data8 sys_rt_sigaction
1564 data8 sys_rt_sigpending
1565 data8 sys_rt_sigprocmask
1566 data8 sys_rt_sigqueueinfo // 1180
1567 data8 sys_rt_sigreturn
1568 data8 sys_rt_sigsuspend
1569 data8 sys_rt_sigtimedwait
1570 data8 sys_getcwd
1571 data8 sys_capget // 1185
1572 data8 sys_capset
1573 data8 sys_sendfile64
1574 data8 sys_ni_syscall // sys_getpmsg (STREAMS)
1575 data8 sys_ni_syscall // sys_putpmsg (STREAMS)
1576 data8 sys_socket // 1190
1577 data8 sys_bind
1578 data8 sys_connect
1579 data8 sys_listen
1580 data8 sys_accept
1581 data8 sys_getsockname // 1195
1582 data8 sys_getpeername
1583 data8 sys_socketpair
1584 data8 sys_send
1585 data8 sys_sendto
1586 data8 sys_recv // 1200
1587 data8 sys_recvfrom
1588 data8 sys_shutdown
1589 data8 sys_setsockopt
1590 data8 sys_getsockopt
1591 data8 sys_sendmsg // 1205
1592 data8 sys_recvmsg
1593 data8 sys_pivot_root
1594 data8 sys_mincore
1595 data8 sys_madvise
1596 data8 sys_newstat // 1210
1597 data8 sys_newlstat
1598 data8 sys_newfstat
1599 data8 sys_clone2
1600 data8 sys_getdents64
1601 data8 sys_getunwind // 1215
1602 data8 sys_readahead
1603 data8 sys_setxattr
1604 data8 sys_lsetxattr
1605 data8 sys_fsetxattr
1606 data8 sys_getxattr // 1220
1607 data8 sys_lgetxattr
1608 data8 sys_fgetxattr
1609 data8 sys_listxattr
1610 data8 sys_llistxattr
1611 data8 sys_flistxattr // 1225
1612 data8 sys_removexattr
1613 data8 sys_lremovexattr
1614 data8 sys_fremovexattr
1615 data8 sys_tkill
1616 data8 sys_futex // 1230
1617 data8 sys_sched_setaffinity
1618 data8 sys_sched_getaffinity
1619 data8 sys_set_tid_address
1620 data8 sys_fadvise64_64
1621 data8 sys_tgkill // 1235
1622 data8 sys_exit_group
1623 data8 sys_lookup_dcookie
1624 data8 sys_io_setup
1625 data8 sys_io_destroy
1626 data8 sys_io_getevents // 1240
1627 data8 sys_io_submit
1628 data8 sys_io_cancel
1629 data8 sys_epoll_create
1630 data8 sys_epoll_ctl
1631 data8 sys_epoll_wait // 1245
1632 data8 sys_restart_syscall
1633 data8 sys_semtimedop
1634 data8 sys_timer_create
1635 data8 sys_timer_settime
1636 data8 sys_timer_gettime // 1250
1637 data8 sys_timer_getoverrun
1638 data8 sys_timer_delete
1639 data8 sys_clock_settime
1640 data8 sys_clock_gettime
1641 data8 sys_clock_getres // 1255
1642 data8 sys_clock_nanosleep
1643 data8 sys_fstatfs64
1644 data8 sys_statfs64
1645 data8 sys_mbind
1646 data8 sys_get_mempolicy // 1260
1647 data8 sys_set_mempolicy
1648 data8 sys_mq_open
1649 data8 sys_mq_unlink
1650 data8 sys_mq_timedsend
1651 data8 sys_mq_timedreceive // 1265
1652 data8 sys_mq_notify
1653 data8 sys_mq_getsetattr
a7956113 1654 data8 sys_kexec_load
1da177e4
LT		 1655 data8 sys_ni_syscall // reserved for vserver
1656 data8 sys_waitid // 1270
1657 data8 sys_add_key
1658 data8 sys_request_key
1659 data8 sys_keyctl
22e2c507
JA		 1660 data8 sys_ioprio_set
1661 data8 sys_ioprio_get // 1275
742755a1 1662 data8 sys_move_pages
d108919b
RL		 1663 data8 sys_inotify_init
1664 data8 sys_inotify_add_watch
1665 data8 sys_inotify_rm_watch
39743889 1666 data8 sys_migrate_pages // 1280
9ed2ad86
KC		 1667 data8 sys_openat
1668 data8 sys_mkdirat
1669 data8 sys_mknodat
1670 data8 sys_fchownat
1671 data8 sys_futimesat // 1285
1672 data8 sys_newfstatat
1673 data8 sys_unlinkat
1674 data8 sys_renameat
1675 data8 sys_linkat
1676 data8 sys_symlinkat // 1290
1677 data8 sys_readlinkat
1678 data8 sys_fchmodat
1679 data8 sys_faccessat
e180583b 1680 data8 sys_pselect6
ad9e39c7 1681 data8 sys_ppoll // 1295
9621a4ef 1682 data8 sys_unshare
5274f052 1683 data8 sys_splice
5c55cd63
TL		 1684 data8 sys_set_robust_list
1685 data8 sys_get_robust_list
d905b00b 1686 data8 sys_sync_file_range // 1300
70524490 1687 data8 sys_tee
912d35f8 1688 data8 sys_vmsplice
3d7559e6 1689 data8 sys_fallocate
86afa9eb 1690 data8 sys_getcpu
472118e6
TL		 1691 data8 sys_epoll_pwait // 1305
1692 data8 sys_utimensat
ae67e498 1693 data8 sys_signalfd
4d672e7a 1694 data8 sys_ni_syscall
ae67e498 1695 data8 sys_eventfd
ad9e39c7
TL		 1696 data8 sys_timerfd_create // 1310
1697 data8 sys_timerfd_settime
1698 data8 sys_timerfd_gettime
3e4d0cab
TL		 1699 data8 sys_signalfd4
1700 data8 sys_eventfd2
1701 data8 sys_epoll_create1 // 1315
1702 data8 sys_dup3
1703 data8 sys_pipe2
1704 data8 sys_inotify_init1
1da177e4
LT		 1705
1706 .org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
4df8d22b 1707#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
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