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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
46cba3dc ST |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
13 | * APIC code. In particular, we now have separate | |
14 | * handlers for edge and level triggered | |
15 | * interrupts. | |
16 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
17 | * allocation PCI to vector mapping, shared PCI | |
18 | * interrupts. | |
19 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
20 | * understandable. Clean up much of the old | |
21 | * IOSAPIC cruft. | |
22 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
23 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 24 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
25 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
26 | * vectors in iosapic_set_affinity(), | |
27 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
28 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
29 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
30 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
31 | * IOSAPIC mapping error | |
1da177e4 | 32 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
33 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
34 | * interrupt, vector, etc.) | |
35 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
36 | * pci_irq code. | |
1da177e4 | 37 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
38 | * Remove iosapic_address & gsi_base from |
39 | * external interfaces. Rationalize | |
40 | * __init/__devinit attributes. | |
1da177e4 | 41 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
42 | * Updated to work with irq migration necessary |
43 | * for CPU Hotplug | |
1da177e4 LT |
44 | */ |
45 | /* | |
46cba3dc ST |
46 | * Here is what the interrupt logic between a PCI device and the kernel looks |
47 | * like: | |
1da177e4 | 48 | * |
46cba3dc ST |
49 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
50 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
51 | * (the function number does not matter here because all functions share | |
52 | * the same interrupt lines). | |
1da177e4 | 53 | * |
46cba3dc ST |
54 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
55 | * controller. Multiple interrupt lines may have to share the same | |
56 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
57 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
58 | * which can be calculated as the sum of the controller's base GSI number | |
59 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 60 | * |
46cba3dc ST |
61 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
62 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
63 | * sent to the CPU. | |
1da177e4 | 64 | * |
46cba3dc ST |
65 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
66 | * used as architecture-independent interrupt handling mechanism in Linux. | |
67 | * As an IRQ is a number, we have to have | |
68 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
69 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
70 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 | 71 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
7f30491c | 72 | * Please see also arch/ia64/include/asm/hw_irq.h for those APIs. |
1da177e4 LT |
73 | * |
74 | * To sum up, there are three levels of mappings involved: | |
75 | * | |
76 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
77 | * | |
46cba3dc | 78 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
c74edea3 | 79 | * describe interrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ |
46cba3dc | 80 | * (isa_irq) is the only exception in this source code. |
1da177e4 | 81 | */ |
1da177e4 LT |
82 | |
83 | #include <linux/acpi.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/irq.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/list.h> | |
88 | #include <linux/pci.h> | |
5a0e3ad6 | 89 | #include <linux/slab.h> |
1da177e4 | 90 | #include <linux/smp.h> |
1da177e4 | 91 | #include <linux/string.h> |
24eeb568 | 92 | #include <linux/bootmem.h> |
1da177e4 LT |
93 | |
94 | #include <asm/delay.h> | |
95 | #include <asm/hw_irq.h> | |
96 | #include <asm/io.h> | |
97 | #include <asm/iosapic.h> | |
98 | #include <asm/machvec.h> | |
99 | #include <asm/processor.h> | |
100 | #include <asm/ptrace.h> | |
1da177e4 | 101 | |
1da177e4 LT |
102 | #undef DEBUG_INTERRUPT_ROUTING |
103 | ||
104 | #ifdef DEBUG_INTERRUPT_ROUTING | |
105 | #define DBG(fmt...) printk(fmt) | |
106 | #else | |
107 | #define DBG(fmt...) | |
108 | #endif | |
109 | ||
110 | static DEFINE_SPINLOCK(iosapic_lock); | |
111 | ||
46cba3dc ST |
112 | /* |
113 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
114 | * vector. | |
115 | */ | |
e1b30a39 YI |
116 | |
117 | #define NO_REF_RTE 0 | |
118 | ||
c5e3f9e5 YI |
119 | static struct iosapic { |
120 | char __iomem *addr; /* base address of IOSAPIC */ | |
121 | unsigned int gsi_base; /* GSI base */ | |
122 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
123 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ | |
124 | #ifdef CONFIG_NUMA | |
125 | unsigned short node; /* numa node association via pxm */ | |
126 | #endif | |
c1726d6f | 127 | spinlock_t lock; /* lock for indirect reg access */ |
c5e3f9e5 | 128 | } iosapic_lists[NR_IOSAPICS]; |
1da177e4 | 129 | |
24eeb568 | 130 | struct iosapic_rte_info { |
c5e3f9e5 | 131 | struct list_head rte_list; /* RTEs sharing the same vector */ |
24eeb568 KK |
132 | char rte_index; /* IOSAPIC RTE index */ |
133 | int refcnt; /* reference counter */ | |
c5e3f9e5 | 134 | struct iosapic *iosapic; |
24eeb568 KK |
135 | } ____cacheline_aligned; |
136 | ||
137 | static struct iosapic_intr_info { | |
46cba3dc ST |
138 | struct list_head rtes; /* RTEs using this vector (empty => |
139 | * not an IOSAPIC interrupt) */ | |
c4c376f7 | 140 | int count; /* # of registered RTEs */ |
46cba3dc ST |
141 | u32 low32; /* current value of low word of |
142 | * Redirection table entry */ | |
24eeb568 | 143 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 144 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
145 | unsigned char polarity: 1; /* interrupt polarity |
146 | * (see iosapic.h) */ | |
1da177e4 | 147 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
4bbdec7a | 148 | } iosapic_intr_info[NR_IRQS]; |
1da177e4 | 149 | |
5b5e76e9 | 150 | static unsigned char pcat_compat; /* 8259 compatibility flag */ |
1da177e4 | 151 | |
c1726d6f YI |
152 | static inline void |
153 | iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) | |
154 | { | |
155 | unsigned long flags; | |
156 | ||
157 | spin_lock_irqsave(&iosapic->lock, flags); | |
158 | __iosapic_write(iosapic->addr, reg, val); | |
159 | spin_unlock_irqrestore(&iosapic->lock, flags); | |
160 | } | |
161 | ||
1da177e4 LT |
162 | /* |
163 | * Find an IOSAPIC associated with a GSI | |
164 | */ | |
165 | static inline int | |
166 | find_iosapic (unsigned int gsi) | |
167 | { | |
168 | int i; | |
169 | ||
0e888adc | 170 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
171 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
172 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
173 | return i; |
174 | } | |
175 | ||
176 | return -1; | |
177 | } | |
178 | ||
4bbdec7a | 179 | static inline int __gsi_to_irq(unsigned int gsi) |
1da177e4 | 180 | { |
4bbdec7a | 181 | int irq; |
1da177e4 | 182 | struct iosapic_intr_info *info; |
24eeb568 | 183 | struct iosapic_rte_info *rte; |
1da177e4 | 184 | |
4bbdec7a YI |
185 | for (irq = 0; irq < NR_IRQS; irq++) { |
186 | info = &iosapic_intr_info[irq]; | |
24eeb568 | 187 | list_for_each_entry(rte, &info->rtes, rte_list) |
c5e3f9e5 | 188 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
4bbdec7a YI |
189 | return irq; |
190 | } | |
1da177e4 LT |
191 | return -1; |
192 | } | |
193 | ||
1da177e4 LT |
194 | int |
195 | gsi_to_irq (unsigned int gsi) | |
196 | { | |
24eeb568 KK |
197 | unsigned long flags; |
198 | int irq; | |
4bbdec7a | 199 | |
24eeb568 | 200 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 201 | irq = __gsi_to_irq(gsi); |
24eeb568 | 202 | spin_unlock_irqrestore(&iosapic_lock, flags); |
24eeb568 KK |
203 | return irq; |
204 | } | |
205 | ||
4bbdec7a | 206 | static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi) |
24eeb568 KK |
207 | { |
208 | struct iosapic_rte_info *rte; | |
209 | ||
4bbdec7a | 210 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 211 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 KK |
212 | return rte; |
213 | return NULL; | |
1da177e4 LT |
214 | } |
215 | ||
216 | static void | |
4bbdec7a | 217 | set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) |
1da177e4 LT |
218 | { |
219 | unsigned long pol, trigger, dmode; | |
220 | u32 low32, high32; | |
1da177e4 LT |
221 | int rte_index; |
222 | char redir; | |
24eeb568 | 223 | struct iosapic_rte_info *rte; |
4bbdec7a | 224 | ia64_vector vector = irq_to_vector(irq); |
1da177e4 LT |
225 | |
226 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
227 | ||
4bbdec7a | 228 | rte = find_rte(irq, gsi); |
24eeb568 | 229 | if (!rte) |
1da177e4 LT |
230 | return; /* not an IOSAPIC interrupt */ |
231 | ||
24eeb568 | 232 | rte_index = rte->rte_index; |
4bbdec7a YI |
233 | pol = iosapic_intr_info[irq].polarity; |
234 | trigger = iosapic_intr_info[irq].trigger; | |
235 | dmode = iosapic_intr_info[irq].dmode; | |
1da177e4 LT |
236 | |
237 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
238 | ||
239 | #ifdef CONFIG_SMP | |
4bbdec7a | 240 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); |
1da177e4 LT |
241 | #endif |
242 | ||
243 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
244 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
245 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
246 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
247 | vector); | |
248 | ||
249 | /* dest contains both id and eid */ | |
250 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
251 | ||
c1726d6f YI |
252 | iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
253 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
4bbdec7a YI |
254 | iosapic_intr_info[irq].low32 = low32; |
255 | iosapic_intr_info[irq].dest = dest; | |
1da177e4 LT |
256 | } |
257 | ||
258 | static void | |
9505ec08 | 259 | iosapic_nop (struct irq_data *data) |
1da177e4 LT |
260 | { |
261 | /* do nothing... */ | |
262 | } | |
263 | ||
a7956113 ZN |
264 | |
265 | #ifdef CONFIG_KEXEC | |
266 | void | |
267 | kexec_disable_iosapic(void) | |
268 | { | |
269 | struct iosapic_intr_info *info; | |
270 | struct iosapic_rte_info *rte; | |
4bbdec7a YI |
271 | ia64_vector vec; |
272 | int irq; | |
273 | ||
274 | for (irq = 0; irq < NR_IRQS; irq++) { | |
275 | info = &iosapic_intr_info[irq]; | |
276 | vec = irq_to_vector(irq); | |
a7956113 ZN |
277 | list_for_each_entry(rte, &info->rtes, |
278 | rte_list) { | |
c1726d6f | 279 | iosapic_write(rte->iosapic, |
a7956113 ZN |
280 | IOSAPIC_RTE_LOW(rte->rte_index), |
281 | IOSAPIC_MASK|vec); | |
c5e3f9e5 | 282 | iosapic_eoi(rte->iosapic->addr, vec); |
a7956113 ZN |
283 | } |
284 | } | |
285 | } | |
286 | #endif | |
287 | ||
1da177e4 | 288 | static void |
8fac171f | 289 | mask_irq (struct irq_data *data) |
1da177e4 | 290 | { |
8fac171f | 291 | unsigned int irq = data->irq; |
1da177e4 LT |
292 | u32 low32; |
293 | int rte_index; | |
24eeb568 | 294 | struct iosapic_rte_info *rte; |
1da177e4 | 295 | |
c4c376f7 | 296 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
297 | return; /* not an IOSAPIC interrupt! */ |
298 | ||
e3a8f7b8 | 299 | /* set only the mask bit */ |
4bbdec7a YI |
300 | low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
301 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 302 | rte_index = rte->rte_index; |
c1726d6f | 303 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 304 | } |
1da177e4 LT |
305 | } |
306 | ||
307 | static void | |
8fac171f | 308 | unmask_irq (struct irq_data *data) |
1da177e4 | 309 | { |
8fac171f | 310 | unsigned int irq = data->irq; |
1da177e4 LT |
311 | u32 low32; |
312 | int rte_index; | |
24eeb568 | 313 | struct iosapic_rte_info *rte; |
1da177e4 | 314 | |
c4c376f7 | 315 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
316 | return; /* not an IOSAPIC interrupt! */ |
317 | ||
4bbdec7a YI |
318 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; |
319 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 320 | rte_index = rte->rte_index; |
c1726d6f | 321 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 322 | } |
1da177e4 LT |
323 | } |
324 | ||
325 | ||
d5dedd45 | 326 | static int |
8fac171f TG |
327 | iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
328 | bool force) | |
1da177e4 LT |
329 | { |
330 | #ifdef CONFIG_SMP | |
8fac171f | 331 | unsigned int irq = data->irq; |
1da177e4 | 332 | u32 high32, low32; |
0de26520 | 333 | int cpu, dest, rte_index; |
1da177e4 | 334 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
24eeb568 | 335 | struct iosapic_rte_info *rte; |
c1726d6f | 336 | struct iosapic *iosapic; |
1da177e4 LT |
337 | |
338 | irq &= (~IA64_IRQ_REDIRECTED); | |
1da177e4 | 339 | |
0de26520 RR |
340 | cpu = cpumask_first_and(cpu_online_mask, mask); |
341 | if (cpu >= nr_cpu_ids) | |
d5dedd45 | 342 | return -1; |
1da177e4 | 343 | |
0de26520 | 344 | if (irq_prepare_move(irq, cpu)) |
d5dedd45 | 345 | return -1; |
cd378f18 | 346 | |
0de26520 | 347 | dest = cpu_physical_id(cpu); |
1da177e4 | 348 | |
c4c376f7 | 349 | if (!iosapic_intr_info[irq].count) |
d5dedd45 | 350 | return -1; /* not an IOSAPIC interrupt */ |
1da177e4 LT |
351 | |
352 | set_irq_affinity_info(irq, dest, redir); | |
353 | ||
354 | /* dest contains both id and eid */ | |
355 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
356 | ||
4bbdec7a | 357 | low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
e3a8f7b8 YI |
358 | if (redir) |
359 | /* change delivery mode to lowest priority */ | |
360 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
361 | else | |
362 | /* change delivery mode to fixed */ | |
363 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
cd378f18 YI |
364 | low32 &= IOSAPIC_VECTOR_MASK; |
365 | low32 |= irq_to_vector(irq); | |
e3a8f7b8 | 366 | |
4bbdec7a YI |
367 | iosapic_intr_info[irq].low32 = low32; |
368 | iosapic_intr_info[irq].dest = dest; | |
369 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
c1726d6f | 370 | iosapic = rte->iosapic; |
e3a8f7b8 | 371 | rte_index = rte->rte_index; |
c1726d6f YI |
372 | iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
373 | iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 374 | } |
d5dedd45 | 375 | |
1da177e4 | 376 | #endif |
d5dedd45 | 377 | return 0; |
1da177e4 LT |
378 | } |
379 | ||
380 | /* | |
381 | * Handlers for level-triggered interrupts. | |
382 | */ | |
383 | ||
384 | static unsigned int | |
8fac171f | 385 | iosapic_startup_level_irq (struct irq_data *data) |
1da177e4 | 386 | { |
8fac171f | 387 | unmask_irq(data); |
1da177e4 LT |
388 | return 0; |
389 | } | |
390 | ||
391 | static void | |
8fac171f | 392 | iosapic_unmask_level_irq (struct irq_data *data) |
1da177e4 | 393 | { |
8fac171f | 394 | unsigned int irq = data->irq; |
1da177e4 | 395 | ia64_vector vec = irq_to_vector(irq); |
24eeb568 | 396 | struct iosapic_rte_info *rte; |
cd378f18 YI |
397 | int do_unmask_irq = 0; |
398 | ||
a6cd6322 | 399 | irq_complete_move(irq); |
91ce72e0 | 400 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
cd378f18 | 401 | do_unmask_irq = 1; |
8fac171f | 402 | mask_irq(data); |
5d4bff94 | 403 | } else |
8fac171f | 404 | unmask_irq(data); |
1da177e4 | 405 | |
4bbdec7a | 406 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 407 | iosapic_eoi(rte->iosapic->addr, vec); |
cd378f18 YI |
408 | |
409 | if (unlikely(do_unmask_irq)) { | |
91ce72e0 | 410 | irq_move_masked_irq(data); |
8fac171f | 411 | unmask_irq(data); |
cd378f18 | 412 | } |
1da177e4 LT |
413 | } |
414 | ||
415 | #define iosapic_shutdown_level_irq mask_irq | |
416 | #define iosapic_enable_level_irq unmask_irq | |
417 | #define iosapic_disable_level_irq mask_irq | |
9505ec08 | 418 | #define iosapic_ack_level_irq iosapic_nop |
1da177e4 | 419 | |
9e004ebd | 420 | static struct irq_chip irq_type_iosapic_level = { |
8fac171f TG |
421 | .name = "IO-SAPIC-level", |
422 | .irq_startup = iosapic_startup_level_irq, | |
423 | .irq_shutdown = iosapic_shutdown_level_irq, | |
424 | .irq_enable = iosapic_enable_level_irq, | |
425 | .irq_disable = iosapic_disable_level_irq, | |
426 | .irq_ack = iosapic_ack_level_irq, | |
427 | .irq_mask = mask_irq, | |
428 | .irq_unmask = iosapic_unmask_level_irq, | |
429 | .irq_set_affinity = iosapic_set_affinity | |
1da177e4 LT |
430 | }; |
431 | ||
432 | /* | |
433 | * Handlers for edge-triggered interrupts. | |
434 | */ | |
435 | ||
436 | static unsigned int | |
8fac171f | 437 | iosapic_startup_edge_irq (struct irq_data *data) |
1da177e4 | 438 | { |
8fac171f | 439 | unmask_irq(data); |
1da177e4 LT |
440 | /* |
441 | * IOSAPIC simply drops interrupts pended while the | |
442 | * corresponding pin was masked, so we can't know if an | |
443 | * interrupt is pending already. Let's hope not... | |
444 | */ | |
445 | return 0; | |
446 | } | |
447 | ||
448 | static void | |
8fac171f | 449 | iosapic_ack_edge_irq (struct irq_data *data) |
1da177e4 | 450 | { |
91ce72e0 TG |
451 | irq_complete_move(data->irq); |
452 | irq_move_irq(data); | |
1da177e4 LT |
453 | } |
454 | ||
455 | #define iosapic_enable_edge_irq unmask_irq | |
9505ec08 | 456 | #define iosapic_disable_edge_irq iosapic_nop |
1da177e4 | 457 | |
9e004ebd | 458 | static struct irq_chip irq_type_iosapic_edge = { |
8fac171f TG |
459 | .name = "IO-SAPIC-edge", |
460 | .irq_startup = iosapic_startup_edge_irq, | |
461 | .irq_shutdown = iosapic_disable_edge_irq, | |
462 | .irq_enable = iosapic_enable_edge_irq, | |
463 | .irq_disable = iosapic_disable_edge_irq, | |
464 | .irq_ack = iosapic_ack_edge_irq, | |
465 | .irq_mask = mask_irq, | |
466 | .irq_unmask = unmask_irq, | |
467 | .irq_set_affinity = iosapic_set_affinity | |
1da177e4 LT |
468 | }; |
469 | ||
9e004ebd | 470 | static unsigned int |
1da177e4 LT |
471 | iosapic_version (char __iomem *addr) |
472 | { | |
473 | /* | |
474 | * IOSAPIC Version Register return 32 bit structure like: | |
475 | * { | |
476 | * unsigned int version : 8; | |
477 | * unsigned int reserved1 : 8; | |
478 | * unsigned int max_redir : 8; | |
479 | * unsigned int reserved2 : 8; | |
480 | * } | |
481 | */ | |
c1726d6f | 482 | return __iosapic_read(addr, IOSAPIC_VERSION); |
1da177e4 LT |
483 | } |
484 | ||
4bbdec7a | 485 | static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol) |
24eeb568 | 486 | { |
4bbdec7a | 487 | int i, irq = -ENOSPC, min_count = -1; |
24eeb568 KK |
488 | struct iosapic_intr_info *info; |
489 | ||
490 | /* | |
491 | * shared vectors for edge-triggered interrupts are not | |
492 | * supported yet | |
493 | */ | |
494 | if (trigger == IOSAPIC_EDGE) | |
40598cbe | 495 | return -EINVAL; |
24eeb568 | 496 | |
5b592397 | 497 | for (i = 0; i < NR_IRQS; i++) { |
24eeb568 KK |
498 | info = &iosapic_intr_info[i]; |
499 | if (info->trigger == trigger && info->polarity == pol && | |
f8c087f3 YI |
500 | (info->dmode == IOSAPIC_FIXED || |
501 | info->dmode == IOSAPIC_LOWEST_PRIORITY) && | |
502 | can_request_irq(i, IRQF_SHARED)) { | |
24eeb568 | 503 | if (min_count == -1 || info->count < min_count) { |
4bbdec7a | 504 | irq = i; |
24eeb568 KK |
505 | min_count = info->count; |
506 | } | |
507 | } | |
508 | } | |
4bbdec7a | 509 | return irq; |
24eeb568 KK |
510 | } |
511 | ||
1da177e4 LT |
512 | /* |
513 | * if the given vector is already owned by other, | |
514 | * assign a new vector for the other and make the vector available | |
515 | */ | |
516 | static void __init | |
4bbdec7a | 517 | iosapic_reassign_vector (int irq) |
1da177e4 | 518 | { |
4bbdec7a | 519 | int new_irq; |
1da177e4 | 520 | |
c4c376f7 | 521 | if (iosapic_intr_info[irq].count) { |
4bbdec7a YI |
522 | new_irq = create_irq(); |
523 | if (new_irq < 0) | |
d4ed8084 | 524 | panic("%s: out of interrupt vectors!\n", __func__); |
46cba3dc | 525 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
4bbdec7a YI |
526 | irq_to_vector(irq), irq_to_vector(new_irq)); |
527 | memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq], | |
1da177e4 | 528 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
529 | INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes); |
530 | list_move(iosapic_intr_info[irq].rtes.next, | |
531 | &iosapic_intr_info[new_irq].rtes); | |
532 | memset(&iosapic_intr_info[irq], 0, | |
46cba3dc | 533 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
534 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; |
535 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); | |
1da177e4 LT |
536 | } |
537 | } | |
538 | ||
4bbdec7a | 539 | static inline int irq_is_shared (int irq) |
24eeb568 | 540 | { |
4bbdec7a | 541 | return (iosapic_intr_info[irq].count > 1); |
24eeb568 KK |
542 | } |
543 | ||
33b39e84 IY |
544 | struct irq_chip* |
545 | ia64_native_iosapic_get_irq_chip(unsigned long trigger) | |
546 | { | |
547 | if (trigger == IOSAPIC_EDGE) | |
548 | return &irq_type_iosapic_edge; | |
549 | else | |
550 | return &irq_type_iosapic_level; | |
551 | } | |
552 | ||
14454a1b | 553 | static int |
4bbdec7a | 554 | register_intr (unsigned int gsi, int irq, unsigned char delivery, |
1da177e4 LT |
555 | unsigned long polarity, unsigned long trigger) |
556 | { | |
dea1078e | 557 | struct irq_chip *chip, *irq_type; |
1da177e4 | 558 | int index; |
24eeb568 | 559 | struct iosapic_rte_info *rte; |
1da177e4 LT |
560 | |
561 | index = find_iosapic(gsi); | |
562 | if (index < 0) { | |
46cba3dc | 563 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
d4ed8084 | 564 | __func__, gsi); |
14454a1b | 565 | return -ENODEV; |
1da177e4 LT |
566 | } |
567 | ||
4bbdec7a | 568 | rte = find_rte(irq, gsi); |
24eeb568 | 569 | if (!rte) { |
4de0a759 | 570 | rte = kzalloc(sizeof (*rte), GFP_ATOMIC); |
24eeb568 | 571 | if (!rte) { |
46cba3dc | 572 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
d4ed8084 | 573 | __func__); |
14454a1b | 574 | return -ENOMEM; |
24eeb568 KK |
575 | } |
576 | ||
c5e3f9e5 YI |
577 | rte->iosapic = &iosapic_lists[index]; |
578 | rte->rte_index = gsi - rte->iosapic->gsi_base; | |
24eeb568 | 579 | rte->refcnt++; |
4bbdec7a YI |
580 | list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes); |
581 | iosapic_intr_info[irq].count++; | |
0e888adc | 582 | iosapic_lists[index].rtes_inuse++; |
24eeb568 | 583 | } |
e1b30a39 | 584 | else if (rte->refcnt == NO_REF_RTE) { |
4bbdec7a | 585 | struct iosapic_intr_info *info = &iosapic_intr_info[irq]; |
e1b30a39 YI |
586 | if (info->count > 0 && |
587 | (info->trigger != trigger || info->polarity != polarity)){ | |
46cba3dc ST |
588 | printk (KERN_WARNING |
589 | "%s: cannot override the interrupt\n", | |
d4ed8084 | 590 | __func__); |
14454a1b | 591 | return -EINVAL; |
24eeb568 | 592 | } |
e1b30a39 YI |
593 | rte->refcnt++; |
594 | iosapic_intr_info[irq].count++; | |
595 | iosapic_lists[index].rtes_inuse++; | |
24eeb568 KK |
596 | } |
597 | ||
4bbdec7a YI |
598 | iosapic_intr_info[irq].polarity = polarity; |
599 | iosapic_intr_info[irq].dmode = delivery; | |
600 | iosapic_intr_info[irq].trigger = trigger; | |
1da177e4 | 601 | |
33b39e84 | 602 | irq_type = iosapic_get_irq_chip(trigger); |
1da177e4 | 603 | |
dea1078e TG |
604 | chip = irq_get_chip(irq); |
605 | if (irq_type != NULL && chip != irq_type) { | |
606 | if (chip != &no_irq_chip) | |
46cba3dc ST |
607 | printk(KERN_WARNING |
608 | "%s: changing vector %d from %s to %s\n", | |
d4ed8084 | 609 | __func__, irq_to_vector(irq), |
dea1078e TG |
610 | chip->name, irq_type->name); |
611 | chip = irq_type; | |
1da177e4 | 612 | } |
59fb3d58 TG |
613 | irq_set_chip_handler_name_locked(irq_get_irq_data(irq), chip, |
614 | trigger == IOSAPIC_EDGE ? handle_edge_irq : handle_level_irq, | |
615 | NULL); | |
14454a1b | 616 | return 0; |
1da177e4 LT |
617 | } |
618 | ||
619 | static unsigned int | |
4bbdec7a | 620 | get_target_cpu (unsigned int gsi, int irq) |
1da177e4 LT |
621 | { |
622 | #ifdef CONFIG_SMP | |
623 | static int cpu = -1; | |
ff741906 | 624 | extern int cpe_vector; |
4994be1b | 625 | cpumask_t domain = irq_to_domain(irq); |
1da177e4 | 626 | |
24eeb568 KK |
627 | /* |
628 | * In case of vector shared by multiple RTEs, all RTEs that | |
629 | * share the vector need to use the same destination CPU. | |
630 | */ | |
c4c376f7 | 631 | if (iosapic_intr_info[irq].count) |
4bbdec7a | 632 | return iosapic_intr_info[irq].dest; |
24eeb568 | 633 | |
1da177e4 LT |
634 | /* |
635 | * If the platform supports redirection via XTP, let it | |
636 | * distribute interrupts. | |
637 | */ | |
638 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
639 | return cpu_physical_id(smp_processor_id()); | |
640 | ||
641 | /* | |
642 | * Some interrupts (ACPI SCI, for instance) are registered | |
643 | * before the BSP is marked as online. | |
644 | */ | |
645 | if (!cpu_online(smp_processor_id())) | |
646 | return cpu_physical_id(smp_processor_id()); | |
647 | ||
ff741906 | 648 | #ifdef CONFIG_ACPI |
4bbdec7a | 649 | if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR) |
b88e9265 | 650 | return get_cpei_target_cpu(); |
ff741906 AR |
651 | #endif |
652 | ||
1da177e4 LT |
653 | #ifdef CONFIG_NUMA |
654 | { | |
655 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
fbb776c3 | 656 | const struct cpumask *cpu_mask; |
1da177e4 LT |
657 | |
658 | iosapic_index = find_iosapic(gsi); | |
659 | if (iosapic_index < 0 || | |
660 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
661 | goto skip_numa_setup; | |
662 | ||
fbb776c3 RR |
663 | cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node); |
664 | num_cpus = 0; | |
665 | for_each_cpu_and(numa_cpu, cpu_mask, &domain) { | |
666 | if (cpu_online(numa_cpu)) | |
667 | num_cpus++; | |
1da177e4 LT |
668 | } |
669 | ||
1da177e4 LT |
670 | if (!num_cpus) |
671 | goto skip_numa_setup; | |
672 | ||
4bbdec7a YI |
673 | /* Use irq assignment to distribute across cpus in node */ |
674 | cpu_index = irq % num_cpus; | |
1da177e4 | 675 | |
fbb776c3 RR |
676 | for_each_cpu_and(numa_cpu, cpu_mask, &domain) |
677 | if (cpu_online(numa_cpu) && i++ >= cpu_index) | |
678 | break; | |
1da177e4 | 679 | |
fbb776c3 | 680 | if (numa_cpu < nr_cpu_ids) |
1da177e4 LT |
681 | return cpu_physical_id(numa_cpu); |
682 | } | |
683 | skip_numa_setup: | |
684 | #endif | |
685 | /* | |
686 | * Otherwise, round-robin interrupt vectors across all the | |
687 | * processors. (It'd be nice if we could be smarter in the | |
688 | * case of NUMA.) | |
689 | */ | |
690 | do { | |
fbb776c3 | 691 | if (++cpu >= nr_cpu_ids) |
1da177e4 | 692 | cpu = 0; |
5d2068da | 693 | } while (!cpu_online(cpu) || !cpumask_test_cpu(cpu, &domain)); |
1da177e4 LT |
694 | |
695 | return cpu_physical_id(cpu); | |
46cba3dc | 696 | #else /* CONFIG_SMP */ |
1da177e4 LT |
697 | return cpu_physical_id(smp_processor_id()); |
698 | #endif | |
699 | } | |
700 | ||
c9d059de KK |
701 | static inline unsigned char choose_dmode(void) |
702 | { | |
703 | #ifdef CONFIG_SMP | |
704 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
705 | return IOSAPIC_LOWEST_PRIORITY; | |
706 | #endif | |
707 | return IOSAPIC_FIXED; | |
708 | } | |
709 | ||
1da177e4 LT |
710 | /* |
711 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
712 | * methods. This provides an interface to register those interrupts and | |
713 | * program the IOSAPIC RTE. | |
714 | */ | |
715 | int | |
716 | iosapic_register_intr (unsigned int gsi, | |
717 | unsigned long polarity, unsigned long trigger) | |
718 | { | |
4bbdec7a | 719 | int irq, mask = 1, err; |
1da177e4 LT |
720 | unsigned int dest; |
721 | unsigned long flags; | |
24eeb568 KK |
722 | struct iosapic_rte_info *rte; |
723 | u32 low32; | |
c9d059de | 724 | unsigned char dmode; |
dea1078e | 725 | struct irq_desc *desc; |
40598cbe | 726 | |
1da177e4 LT |
727 | /* |
728 | * If this GSI has already been registered (i.e., it's a | |
729 | * shared interrupt, or we lost a race to register it), | |
730 | * don't touch the RTE. | |
731 | */ | |
732 | spin_lock_irqsave(&iosapic_lock, flags); | |
4bbdec7a YI |
733 | irq = __gsi_to_irq(gsi); |
734 | if (irq > 0) { | |
735 | rte = find_rte(irq, gsi); | |
e1b30a39 YI |
736 | if(iosapic_intr_info[irq].count == 0) { |
737 | assign_irq_vector(irq); | |
4debd723 | 738 | irq_init_desc(irq); |
e1b30a39 YI |
739 | } else if (rte->refcnt != NO_REF_RTE) { |
740 | rte->refcnt++; | |
741 | goto unlock_iosapic_lock; | |
742 | } | |
743 | } else | |
744 | irq = create_irq(); | |
24eeb568 KK |
745 | |
746 | /* If vector is running out, we try to find a sharable vector */ | |
eb21ab24 | 747 | if (irq < 0) { |
4bbdec7a YI |
748 | irq = iosapic_find_sharable_irq(trigger, polarity); |
749 | if (irq < 0) | |
40598cbe | 750 | goto unlock_iosapic_lock; |
4bbdec7a | 751 | } |
1da177e4 | 752 | |
dea1078e TG |
753 | desc = irq_to_desc(irq); |
754 | raw_spin_lock(&desc->lock); | |
4bbdec7a | 755 | dest = get_target_cpu(gsi, irq); |
c9d059de KK |
756 | dmode = choose_dmode(); |
757 | err = register_intr(gsi, irq, dmode, polarity, trigger); | |
e3a8f7b8 | 758 | if (err < 0) { |
dea1078e | 759 | raw_spin_unlock(&desc->lock); |
4bbdec7a | 760 | irq = err; |
224685c0 | 761 | goto unlock_iosapic_lock; |
1da177e4 | 762 | } |
e3a8f7b8 YI |
763 | |
764 | /* | |
765 | * If the vector is shared and already unmasked for other | |
766 | * interrupt sources, don't mask it. | |
767 | */ | |
4bbdec7a YI |
768 | low32 = iosapic_intr_info[irq].low32; |
769 | if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK)) | |
e3a8f7b8 | 770 | mask = 0; |
4bbdec7a | 771 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
772 | |
773 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
774 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
775 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 776 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
224685c0 | 777 | |
dea1078e | 778 | raw_spin_unlock(&desc->lock); |
40598cbe YI |
779 | unlock_iosapic_lock: |
780 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
4bbdec7a | 781 | return irq; |
1da177e4 LT |
782 | } |
783 | ||
1da177e4 LT |
784 | void |
785 | iosapic_unregister_intr (unsigned int gsi) | |
786 | { | |
787 | unsigned long flags; | |
4bbdec7a | 788 | int irq, index; |
24eeb568 | 789 | u32 low32; |
1da177e4 | 790 | unsigned long trigger, polarity; |
24eeb568 KK |
791 | unsigned int dest; |
792 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
793 | |
794 | /* | |
795 | * If the irq associated with the gsi is not found, | |
796 | * iosapic_unregister_intr() is unbalanced. We need to check | |
797 | * this again after getting locks. | |
798 | */ | |
799 | irq = gsi_to_irq(gsi); | |
800 | if (irq < 0) { | |
46cba3dc ST |
801 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
802 | gsi); | |
1da177e4 LT |
803 | WARN_ON(1); |
804 | return; | |
805 | } | |
1da177e4 | 806 | |
40598cbe | 807 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 808 | if ((rte = find_rte(irq, gsi)) == NULL) { |
e3a8f7b8 YI |
809 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
810 | gsi); | |
811 | WARN_ON(1); | |
812 | goto out; | |
813 | } | |
1da177e4 | 814 | |
e3a8f7b8 YI |
815 | if (--rte->refcnt > 0) |
816 | goto out; | |
1da177e4 | 817 | |
e1b30a39 | 818 | rte->refcnt = NO_REF_RTE; |
40598cbe | 819 | |
e3a8f7b8 | 820 | /* Mask the interrupt */ |
4bbdec7a | 821 | low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK; |
c1726d6f | 822 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32); |
1da177e4 | 823 | |
4bbdec7a | 824 | iosapic_intr_info[irq].count--; |
e3a8f7b8 YI |
825 | index = find_iosapic(gsi); |
826 | iosapic_lists[index].rtes_inuse--; | |
827 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
24eeb568 | 828 | |
4bbdec7a YI |
829 | trigger = iosapic_intr_info[irq].trigger; |
830 | polarity = iosapic_intr_info[irq].polarity; | |
831 | dest = iosapic_intr_info[irq].dest; | |
e3a8f7b8 YI |
832 | printk(KERN_INFO |
833 | "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
834 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
835 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 836 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
24eeb568 | 837 | |
e1b30a39 | 838 | if (iosapic_intr_info[irq].count == 0) { |
451fe00c | 839 | #ifdef CONFIG_SMP |
e3a8f7b8 | 840 | /* Clear affinity */ |
c42574ed | 841 | cpumask_setall(irq_get_affinity_mask(irq)); |
451fe00c | 842 | #endif |
e3a8f7b8 | 843 | /* Clear the interrupt information */ |
e1b30a39 YI |
844 | iosapic_intr_info[irq].dest = 0; |
845 | iosapic_intr_info[irq].dmode = 0; | |
846 | iosapic_intr_info[irq].polarity = 0; | |
847 | iosapic_intr_info[irq].trigger = 0; | |
4bbdec7a | 848 | iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
1da177e4 | 849 | |
e1b30a39 YI |
850 | /* Destroy and reserve IRQ */ |
851 | destroy_and_reserve_irq(irq); | |
1da177e4 | 852 | } |
24eeb568 | 853 | out: |
40598cbe | 854 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 | 855 | } |
1da177e4 LT |
856 | |
857 | /* | |
858 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
859 | */ |
860 | int __init | |
861 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
862 | int iosapic_vector, u16 eid, u16 id, | |
863 | unsigned long polarity, unsigned long trigger) | |
864 | { | |
865 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
866 | unsigned char delivery; | |
eb21ab24 | 867 | int irq, vector, mask = 0; |
1da177e4 LT |
868 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
869 | ||
870 | switch (int_type) { | |
871 | case ACPI_INTERRUPT_PMI: | |
e1b30a39 | 872 | irq = vector = iosapic_vector; |
4994be1b | 873 | bind_irq_vector(irq, vector, CPU_MASK_ALL); |
1da177e4 LT |
874 | /* |
875 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
876 | * we need to make sure the vector is available | |
877 | */ | |
4bbdec7a | 878 | iosapic_reassign_vector(irq); |
1da177e4 LT |
879 | delivery = IOSAPIC_PMI; |
880 | break; | |
881 | case ACPI_INTERRUPT_INIT: | |
eb21ab24 YI |
882 | irq = create_irq(); |
883 | if (irq < 0) | |
d4ed8084 | 884 | panic("%s: out of interrupt vectors!\n", __func__); |
eb21ab24 | 885 | vector = irq_to_vector(irq); |
1da177e4 LT |
886 | delivery = IOSAPIC_INIT; |
887 | break; | |
888 | case ACPI_INTERRUPT_CPEI: | |
e1b30a39 | 889 | irq = vector = IA64_CPE_VECTOR; |
4994be1b | 890 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
aa0ebec9 | 891 | delivery = IOSAPIC_FIXED; |
1da177e4 LT |
892 | mask = 1; |
893 | break; | |
894 | default: | |
d4ed8084 | 895 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__, |
46cba3dc | 896 | int_type); |
1da177e4 LT |
897 | return -1; |
898 | } | |
899 | ||
4bbdec7a | 900 | register_intr(gsi, irq, delivery, polarity, trigger); |
1da177e4 | 901 | |
46cba3dc ST |
902 | printk(KERN_INFO |
903 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
904 | " vector %d\n", | |
1da177e4 LT |
905 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
906 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
907 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
908 | cpu_logical_id(dest), dest, vector); | |
909 | ||
4bbdec7a | 910 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
911 | return vector; |
912 | } | |
913 | ||
1da177e4 LT |
914 | /* |
915 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 | 916 | */ |
5b5e76e9 GKH |
917 | void iosapic_override_isa_irq(unsigned int isa_irq, unsigned int gsi, |
918 | unsigned long polarity, unsigned long trigger) | |
1da177e4 | 919 | { |
4bbdec7a | 920 | int vector, irq; |
1da177e4 | 921 | unsigned int dest = cpu_physical_id(smp_processor_id()); |
c9d059de | 922 | unsigned char dmode; |
1da177e4 | 923 | |
e1b30a39 | 924 | irq = vector = isa_irq_to_vector(isa_irq); |
4994be1b | 925 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
c9d059de KK |
926 | dmode = choose_dmode(); |
927 | register_intr(gsi, irq, dmode, polarity, trigger); | |
1da177e4 LT |
928 | |
929 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
930 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
931 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
932 | cpu_logical_id(dest), dest, vector); | |
933 | ||
4bbdec7a | 934 | set_rte(gsi, irq, dest, 1); |
1da177e4 LT |
935 | } |
936 | ||
33b39e84 IY |
937 | void __init |
938 | ia64_native_iosapic_pcat_compat_init(void) | |
939 | { | |
940 | if (pcat_compat) { | |
941 | /* | |
942 | * Disable the compatibility mode interrupts (8259 style), | |
943 | * needs IN/OUT support enabled. | |
944 | */ | |
945 | printk(KERN_INFO | |
946 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
947 | __func__); | |
948 | outb(0xff, 0xA1); | |
949 | outb(0xff, 0x21); | |
950 | } | |
951 | } | |
952 | ||
1da177e4 LT |
953 | void __init |
954 | iosapic_system_init (int system_pcat_compat) | |
955 | { | |
4bbdec7a | 956 | int irq; |
1da177e4 | 957 | |
4bbdec7a YI |
958 | for (irq = 0; irq < NR_IRQS; ++irq) { |
959 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; | |
46cba3dc | 960 | /* mark as unused */ |
4bbdec7a | 961 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); |
e1b30a39 YI |
962 | |
963 | iosapic_intr_info[irq].count = 0; | |
24eeb568 | 964 | } |
1da177e4 LT |
965 | |
966 | pcat_compat = system_pcat_compat; | |
33b39e84 IY |
967 | if (pcat_compat) |
968 | iosapic_pcat_compat_init(); | |
1da177e4 LT |
969 | } |
970 | ||
0e888adc KK |
971 | static inline int |
972 | iosapic_alloc (void) | |
973 | { | |
974 | int index; | |
975 | ||
976 | for (index = 0; index < NR_IOSAPICS; index++) | |
977 | if (!iosapic_lists[index].addr) | |
978 | return index; | |
979 | ||
d4ed8084 | 980 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__); |
0e888adc KK |
981 | return -1; |
982 | } | |
983 | ||
984 | static inline void | |
985 | iosapic_free (int index) | |
986 | { | |
987 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
988 | } | |
989 | ||
990 | static inline int | |
991 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
992 | { | |
993 | int index; | |
994 | unsigned int gsi_end, base, end; | |
995 | ||
996 | /* check gsi range */ | |
997 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
998 | for (index = 0; index < NR_IOSAPICS; index++) { | |
999 | if (!iosapic_lists[index].addr) | |
1000 | continue; | |
1001 | ||
1002 | base = iosapic_lists[index].gsi_base; | |
1003 | end = base + iosapic_lists[index].num_rte - 1; | |
1004 | ||
e6d1ba5c | 1005 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1006 | continue; /* OK */ |
1007 | ||
1008 | return -EBUSY; | |
1009 | } | |
1010 | return 0; | |
1011 | } | |
1012 | ||
ffa90955 HG |
1013 | static int |
1014 | iosapic_delete_rte(unsigned int irq, unsigned int gsi) | |
1015 | { | |
1016 | struct iosapic_rte_info *rte, *temp; | |
1017 | ||
1018 | list_for_each_entry_safe(rte, temp, &iosapic_intr_info[irq].rtes, | |
1019 | rte_list) { | |
1020 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) { | |
1021 | if (rte->refcnt) | |
1022 | return -EBUSY; | |
1023 | ||
1024 | list_del(&rte->rte_list); | |
1025 | kfree(rte); | |
1026 | return 0; | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | return -EINVAL; | |
1031 | } | |
1032 | ||
5b5e76e9 | 1033 | int iosapic_init(unsigned long phys_addr, unsigned int gsi_base) |
1da177e4 | 1034 | { |
0e888adc | 1035 | int num_rte, err, index; |
1da177e4 LT |
1036 | unsigned int isa_irq, ver; |
1037 | char __iomem *addr; | |
0e888adc KK |
1038 | unsigned long flags; |
1039 | ||
1040 | spin_lock_irqsave(&iosapic_lock, flags); | |
c1726d6f YI |
1041 | index = find_iosapic(gsi_base); |
1042 | if (index >= 0) { | |
1043 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1044 | return -EBUSY; | |
1045 | } | |
1046 | ||
e3a8f7b8 | 1047 | addr = ioremap(phys_addr, 0); |
e7369e01 RK |
1048 | if (addr == NULL) { |
1049 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1050 | return -ENOMEM; | |
1051 | } | |
e3a8f7b8 | 1052 | ver = iosapic_version(addr); |
e3a8f7b8 YI |
1053 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1054 | iounmap(addr); | |
1055 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1056 | return err; | |
1057 | } | |
1da177e4 | 1058 | |
e3a8f7b8 YI |
1059 | /* |
1060 | * The MAX_REDIR register holds the highest input pin number | |
1061 | * (starting from 0). We add 1 so that we can use it for | |
1062 | * number of pins (= RTEs) | |
1063 | */ | |
1064 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1065 | |
e3a8f7b8 YI |
1066 | index = iosapic_alloc(); |
1067 | iosapic_lists[index].addr = addr; | |
1068 | iosapic_lists[index].gsi_base = gsi_base; | |
1069 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1070 | #ifdef CONFIG_NUMA |
e3a8f7b8 | 1071 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1072 | #endif |
c1726d6f | 1073 | spin_lock_init(&iosapic_lists[index].lock); |
0e888adc | 1074 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 LT |
1075 | |
1076 | if ((gsi_base == 0) && pcat_compat) { | |
1077 | /* | |
46cba3dc ST |
1078 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1079 | * these may get reprogrammed later on with data from the ACPI | |
1080 | * Interrupt Source Override table. | |
1da177e4 LT |
1081 | */ |
1082 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1083 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1084 | IOSAPIC_POL_HIGH, | |
1085 | IOSAPIC_EDGE); | |
1da177e4 | 1086 | } |
0e888adc KK |
1087 | return 0; |
1088 | } | |
1089 | ||
5b5e76e9 | 1090 | int iosapic_remove(unsigned int gsi_base) |
0e888adc | 1091 | { |
ffa90955 | 1092 | int i, irq, index, err = 0; |
0e888adc KK |
1093 | unsigned long flags; |
1094 | ||
1095 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
1096 | index = find_iosapic(gsi_base); |
1097 | if (index < 0) { | |
1098 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
d4ed8084 | 1099 | __func__, gsi_base); |
e3a8f7b8 YI |
1100 | goto out; |
1101 | } | |
0e888adc | 1102 | |
e3a8f7b8 YI |
1103 | if (iosapic_lists[index].rtes_inuse) { |
1104 | err = -EBUSY; | |
1105 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
d4ed8084 | 1106 | __func__, gsi_base); |
e3a8f7b8 | 1107 | goto out; |
0e888adc | 1108 | } |
e3a8f7b8 | 1109 | |
ffa90955 HG |
1110 | for (i = gsi_base; i < gsi_base + iosapic_lists[index].num_rte; i++) { |
1111 | irq = __gsi_to_irq(i); | |
1112 | if (irq < 0) | |
1113 | continue; | |
1114 | ||
1115 | err = iosapic_delete_rte(irq, i); | |
1116 | if (err) | |
1117 | goto out; | |
1118 | } | |
1119 | ||
e3a8f7b8 YI |
1120 | iounmap(iosapic_lists[index].addr); |
1121 | iosapic_free(index); | |
0e888adc KK |
1122 | out: |
1123 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1124 | return err; | |
1da177e4 LT |
1125 | } |
1126 | ||
1127 | #ifdef CONFIG_NUMA | |
5b5e76e9 | 1128 | void map_iosapic_to_node(unsigned int gsi_base, int node) |
1da177e4 LT |
1129 | { |
1130 | int index; | |
1131 | ||
1132 | index = find_iosapic(gsi_base); | |
1133 | if (index < 0) { | |
1134 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
d4ed8084 | 1135 | __func__, gsi_base); |
1da177e4 LT |
1136 | return; |
1137 | } | |
1138 | iosapic_lists[index].node = node; | |
1139 | return; | |
1140 | } | |
1141 | #endif |