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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * I/O SAPIC support. | |
4 | * | |
5 | * Copyright (C) 1999 Intel Corp. | |
6 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
7 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
8 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * Copyright (C) 1999 VA Linux Systems | |
11 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
12 | * | |
46cba3dc ST |
13 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
14 | * APIC code. In particular, we now have separate | |
15 | * handlers for edge and level triggered | |
16 | * interrupts. | |
17 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
18 | * allocation PCI to vector mapping, shared PCI | |
19 | * interrupts. | |
20 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
21 | * understandable. Clean up much of the old | |
22 | * IOSAPIC cruft. | |
23 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
24 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 25 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
26 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
27 | * vectors in iosapic_set_affinity(), | |
28 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
29 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
30 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
31 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
32 | * IOSAPIC mapping error | |
1da177e4 | 33 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
34 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
35 | * interrupt, vector, etc.) | |
36 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
37 | * pci_irq code. | |
1da177e4 | 38 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
39 | * Remove iosapic_address & gsi_base from |
40 | * external interfaces. Rationalize | |
41 | * __init/__devinit attributes. | |
1da177e4 | 42 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
43 | * Updated to work with irq migration necessary |
44 | * for CPU Hotplug | |
1da177e4 LT |
45 | */ |
46 | /* | |
46cba3dc ST |
47 | * Here is what the interrupt logic between a PCI device and the kernel looks |
48 | * like: | |
1da177e4 | 49 | * |
46cba3dc ST |
50 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
51 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
52 | * (the function number does not matter here because all functions share | |
53 | * the same interrupt lines). | |
1da177e4 | 54 | * |
46cba3dc ST |
55 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
56 | * controller. Multiple interrupt lines may have to share the same | |
57 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
58 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
59 | * which can be calculated as the sum of the controller's base GSI number | |
60 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 61 | * |
46cba3dc ST |
62 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
63 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
64 | * sent to the CPU. | |
1da177e4 | 65 | * |
46cba3dc ST |
66 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
67 | * used as architecture-independent interrupt handling mechanism in Linux. | |
68 | * As an IRQ is a number, we have to have | |
69 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
70 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
71 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 | 72 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
7f30491c | 73 | * Please see also arch/ia64/include/asm/hw_irq.h for those APIs. |
1da177e4 LT |
74 | * |
75 | * To sum up, there are three levels of mappings involved: | |
76 | * | |
77 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
78 | * | |
46cba3dc | 79 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
c74edea3 | 80 | * describe interrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ |
46cba3dc | 81 | * (isa_irq) is the only exception in this source code. |
1da177e4 | 82 | */ |
1da177e4 LT |
83 | |
84 | #include <linux/acpi.h> | |
85 | #include <linux/init.h> | |
86 | #include <linux/irq.h> | |
87 | #include <linux/kernel.h> | |
88 | #include <linux/list.h> | |
89 | #include <linux/pci.h> | |
5a0e3ad6 | 90 | #include <linux/slab.h> |
1da177e4 | 91 | #include <linux/smp.h> |
1da177e4 | 92 | #include <linux/string.h> |
24eeb568 | 93 | #include <linux/bootmem.h> |
1da177e4 LT |
94 | |
95 | #include <asm/delay.h> | |
96 | #include <asm/hw_irq.h> | |
97 | #include <asm/io.h> | |
98 | #include <asm/iosapic.h> | |
99 | #include <asm/machvec.h> | |
100 | #include <asm/processor.h> | |
101 | #include <asm/ptrace.h> | |
1da177e4 | 102 | |
1da177e4 LT |
103 | #undef DEBUG_INTERRUPT_ROUTING |
104 | ||
105 | #ifdef DEBUG_INTERRUPT_ROUTING | |
106 | #define DBG(fmt...) printk(fmt) | |
107 | #else | |
108 | #define DBG(fmt...) | |
109 | #endif | |
110 | ||
111 | static DEFINE_SPINLOCK(iosapic_lock); | |
112 | ||
46cba3dc ST |
113 | /* |
114 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
115 | * vector. | |
116 | */ | |
e1b30a39 YI |
117 | |
118 | #define NO_REF_RTE 0 | |
119 | ||
c5e3f9e5 YI |
120 | static struct iosapic { |
121 | char __iomem *addr; /* base address of IOSAPIC */ | |
122 | unsigned int gsi_base; /* GSI base */ | |
123 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
124 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ | |
125 | #ifdef CONFIG_NUMA | |
126 | unsigned short node; /* numa node association via pxm */ | |
127 | #endif | |
c1726d6f | 128 | spinlock_t lock; /* lock for indirect reg access */ |
c5e3f9e5 | 129 | } iosapic_lists[NR_IOSAPICS]; |
1da177e4 | 130 | |
24eeb568 | 131 | struct iosapic_rte_info { |
c5e3f9e5 | 132 | struct list_head rte_list; /* RTEs sharing the same vector */ |
24eeb568 KK |
133 | char rte_index; /* IOSAPIC RTE index */ |
134 | int refcnt; /* reference counter */ | |
c5e3f9e5 | 135 | struct iosapic *iosapic; |
24eeb568 KK |
136 | } ____cacheline_aligned; |
137 | ||
138 | static struct iosapic_intr_info { | |
46cba3dc ST |
139 | struct list_head rtes; /* RTEs using this vector (empty => |
140 | * not an IOSAPIC interrupt) */ | |
c4c376f7 | 141 | int count; /* # of registered RTEs */ |
46cba3dc ST |
142 | u32 low32; /* current value of low word of |
143 | * Redirection table entry */ | |
24eeb568 | 144 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 145 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
146 | unsigned char polarity: 1; /* interrupt polarity |
147 | * (see iosapic.h) */ | |
1da177e4 | 148 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
4bbdec7a | 149 | } iosapic_intr_info[NR_IRQS]; |
1da177e4 | 150 | |
5b5e76e9 | 151 | static unsigned char pcat_compat; /* 8259 compatibility flag */ |
1da177e4 | 152 | |
c1726d6f YI |
153 | static inline void |
154 | iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) | |
155 | { | |
156 | unsigned long flags; | |
157 | ||
158 | spin_lock_irqsave(&iosapic->lock, flags); | |
159 | __iosapic_write(iosapic->addr, reg, val); | |
160 | spin_unlock_irqrestore(&iosapic->lock, flags); | |
161 | } | |
162 | ||
1da177e4 LT |
163 | /* |
164 | * Find an IOSAPIC associated with a GSI | |
165 | */ | |
166 | static inline int | |
167 | find_iosapic (unsigned int gsi) | |
168 | { | |
169 | int i; | |
170 | ||
0e888adc | 171 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
172 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
173 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
174 | return i; |
175 | } | |
176 | ||
177 | return -1; | |
178 | } | |
179 | ||
4bbdec7a | 180 | static inline int __gsi_to_irq(unsigned int gsi) |
1da177e4 | 181 | { |
4bbdec7a | 182 | int irq; |
1da177e4 | 183 | struct iosapic_intr_info *info; |
24eeb568 | 184 | struct iosapic_rte_info *rte; |
1da177e4 | 185 | |
4bbdec7a YI |
186 | for (irq = 0; irq < NR_IRQS; irq++) { |
187 | info = &iosapic_intr_info[irq]; | |
24eeb568 | 188 | list_for_each_entry(rte, &info->rtes, rte_list) |
c5e3f9e5 | 189 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
4bbdec7a YI |
190 | return irq; |
191 | } | |
1da177e4 LT |
192 | return -1; |
193 | } | |
194 | ||
1da177e4 LT |
195 | int |
196 | gsi_to_irq (unsigned int gsi) | |
197 | { | |
24eeb568 KK |
198 | unsigned long flags; |
199 | int irq; | |
4bbdec7a | 200 | |
24eeb568 | 201 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 202 | irq = __gsi_to_irq(gsi); |
24eeb568 | 203 | spin_unlock_irqrestore(&iosapic_lock, flags); |
24eeb568 KK |
204 | return irq; |
205 | } | |
206 | ||
4bbdec7a | 207 | static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi) |
24eeb568 KK |
208 | { |
209 | struct iosapic_rte_info *rte; | |
210 | ||
4bbdec7a | 211 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 212 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 KK |
213 | return rte; |
214 | return NULL; | |
1da177e4 LT |
215 | } |
216 | ||
217 | static void | |
4bbdec7a | 218 | set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) |
1da177e4 LT |
219 | { |
220 | unsigned long pol, trigger, dmode; | |
221 | u32 low32, high32; | |
1da177e4 LT |
222 | int rte_index; |
223 | char redir; | |
24eeb568 | 224 | struct iosapic_rte_info *rte; |
4bbdec7a | 225 | ia64_vector vector = irq_to_vector(irq); |
1da177e4 LT |
226 | |
227 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
228 | ||
4bbdec7a | 229 | rte = find_rte(irq, gsi); |
24eeb568 | 230 | if (!rte) |
1da177e4 LT |
231 | return; /* not an IOSAPIC interrupt */ |
232 | ||
24eeb568 | 233 | rte_index = rte->rte_index; |
4bbdec7a YI |
234 | pol = iosapic_intr_info[irq].polarity; |
235 | trigger = iosapic_intr_info[irq].trigger; | |
236 | dmode = iosapic_intr_info[irq].dmode; | |
1da177e4 LT |
237 | |
238 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
239 | ||
240 | #ifdef CONFIG_SMP | |
4bbdec7a | 241 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); |
1da177e4 LT |
242 | #endif |
243 | ||
244 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
245 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
246 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
247 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
248 | vector); | |
249 | ||
250 | /* dest contains both id and eid */ | |
251 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
252 | ||
c1726d6f YI |
253 | iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
254 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
4bbdec7a YI |
255 | iosapic_intr_info[irq].low32 = low32; |
256 | iosapic_intr_info[irq].dest = dest; | |
1da177e4 LT |
257 | } |
258 | ||
259 | static void | |
9505ec08 | 260 | iosapic_nop (struct irq_data *data) |
1da177e4 LT |
261 | { |
262 | /* do nothing... */ | |
263 | } | |
264 | ||
a7956113 ZN |
265 | |
266 | #ifdef CONFIG_KEXEC | |
267 | void | |
268 | kexec_disable_iosapic(void) | |
269 | { | |
270 | struct iosapic_intr_info *info; | |
271 | struct iosapic_rte_info *rte; | |
4bbdec7a YI |
272 | ia64_vector vec; |
273 | int irq; | |
274 | ||
275 | for (irq = 0; irq < NR_IRQS; irq++) { | |
276 | info = &iosapic_intr_info[irq]; | |
277 | vec = irq_to_vector(irq); | |
a7956113 ZN |
278 | list_for_each_entry(rte, &info->rtes, |
279 | rte_list) { | |
c1726d6f | 280 | iosapic_write(rte->iosapic, |
a7956113 ZN |
281 | IOSAPIC_RTE_LOW(rte->rte_index), |
282 | IOSAPIC_MASK|vec); | |
c5e3f9e5 | 283 | iosapic_eoi(rte->iosapic->addr, vec); |
a7956113 ZN |
284 | } |
285 | } | |
286 | } | |
287 | #endif | |
288 | ||
1da177e4 | 289 | static void |
8fac171f | 290 | mask_irq (struct irq_data *data) |
1da177e4 | 291 | { |
8fac171f | 292 | unsigned int irq = data->irq; |
1da177e4 LT |
293 | u32 low32; |
294 | int rte_index; | |
24eeb568 | 295 | struct iosapic_rte_info *rte; |
1da177e4 | 296 | |
c4c376f7 | 297 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
298 | return; /* not an IOSAPIC interrupt! */ |
299 | ||
e3a8f7b8 | 300 | /* set only the mask bit */ |
4bbdec7a YI |
301 | low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
302 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 303 | rte_index = rte->rte_index; |
c1726d6f | 304 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 305 | } |
1da177e4 LT |
306 | } |
307 | ||
308 | static void | |
8fac171f | 309 | unmask_irq (struct irq_data *data) |
1da177e4 | 310 | { |
8fac171f | 311 | unsigned int irq = data->irq; |
1da177e4 LT |
312 | u32 low32; |
313 | int rte_index; | |
24eeb568 | 314 | struct iosapic_rte_info *rte; |
1da177e4 | 315 | |
c4c376f7 | 316 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
317 | return; /* not an IOSAPIC interrupt! */ |
318 | ||
4bbdec7a YI |
319 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; |
320 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 321 | rte_index = rte->rte_index; |
c1726d6f | 322 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 323 | } |
1da177e4 LT |
324 | } |
325 | ||
326 | ||
d5dedd45 | 327 | static int |
8fac171f TG |
328 | iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
329 | bool force) | |
1da177e4 LT |
330 | { |
331 | #ifdef CONFIG_SMP | |
8fac171f | 332 | unsigned int irq = data->irq; |
1da177e4 | 333 | u32 high32, low32; |
0de26520 | 334 | int cpu, dest, rte_index; |
1da177e4 | 335 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
24eeb568 | 336 | struct iosapic_rte_info *rte; |
c1726d6f | 337 | struct iosapic *iosapic; |
1da177e4 LT |
338 | |
339 | irq &= (~IA64_IRQ_REDIRECTED); | |
1da177e4 | 340 | |
0de26520 RR |
341 | cpu = cpumask_first_and(cpu_online_mask, mask); |
342 | if (cpu >= nr_cpu_ids) | |
d5dedd45 | 343 | return -1; |
1da177e4 | 344 | |
0de26520 | 345 | if (irq_prepare_move(irq, cpu)) |
d5dedd45 | 346 | return -1; |
cd378f18 | 347 | |
0de26520 | 348 | dest = cpu_physical_id(cpu); |
1da177e4 | 349 | |
c4c376f7 | 350 | if (!iosapic_intr_info[irq].count) |
d5dedd45 | 351 | return -1; /* not an IOSAPIC interrupt */ |
1da177e4 LT |
352 | |
353 | set_irq_affinity_info(irq, dest, redir); | |
354 | ||
355 | /* dest contains both id and eid */ | |
356 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
357 | ||
4bbdec7a | 358 | low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
e3a8f7b8 YI |
359 | if (redir) |
360 | /* change delivery mode to lowest priority */ | |
361 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
362 | else | |
363 | /* change delivery mode to fixed */ | |
364 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
cd378f18 YI |
365 | low32 &= IOSAPIC_VECTOR_MASK; |
366 | low32 |= irq_to_vector(irq); | |
e3a8f7b8 | 367 | |
4bbdec7a YI |
368 | iosapic_intr_info[irq].low32 = low32; |
369 | iosapic_intr_info[irq].dest = dest; | |
370 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
c1726d6f | 371 | iosapic = rte->iosapic; |
e3a8f7b8 | 372 | rte_index = rte->rte_index; |
c1726d6f YI |
373 | iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
374 | iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 375 | } |
d5dedd45 | 376 | |
1da177e4 | 377 | #endif |
d5dedd45 | 378 | return 0; |
1da177e4 LT |
379 | } |
380 | ||
381 | /* | |
382 | * Handlers for level-triggered interrupts. | |
383 | */ | |
384 | ||
385 | static unsigned int | |
8fac171f | 386 | iosapic_startup_level_irq (struct irq_data *data) |
1da177e4 | 387 | { |
8fac171f | 388 | unmask_irq(data); |
1da177e4 LT |
389 | return 0; |
390 | } | |
391 | ||
392 | static void | |
8fac171f | 393 | iosapic_unmask_level_irq (struct irq_data *data) |
1da177e4 | 394 | { |
8fac171f | 395 | unsigned int irq = data->irq; |
1da177e4 | 396 | ia64_vector vec = irq_to_vector(irq); |
24eeb568 | 397 | struct iosapic_rte_info *rte; |
cd378f18 YI |
398 | int do_unmask_irq = 0; |
399 | ||
a6cd6322 | 400 | irq_complete_move(irq); |
91ce72e0 | 401 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
cd378f18 | 402 | do_unmask_irq = 1; |
8fac171f | 403 | mask_irq(data); |
5d4bff94 | 404 | } else |
8fac171f | 405 | unmask_irq(data); |
1da177e4 | 406 | |
4bbdec7a | 407 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 408 | iosapic_eoi(rte->iosapic->addr, vec); |
cd378f18 YI |
409 | |
410 | if (unlikely(do_unmask_irq)) { | |
91ce72e0 | 411 | irq_move_masked_irq(data); |
8fac171f | 412 | unmask_irq(data); |
cd378f18 | 413 | } |
1da177e4 LT |
414 | } |
415 | ||
416 | #define iosapic_shutdown_level_irq mask_irq | |
417 | #define iosapic_enable_level_irq unmask_irq | |
418 | #define iosapic_disable_level_irq mask_irq | |
9505ec08 | 419 | #define iosapic_ack_level_irq iosapic_nop |
1da177e4 | 420 | |
9e004ebd | 421 | static struct irq_chip irq_type_iosapic_level = { |
8fac171f TG |
422 | .name = "IO-SAPIC-level", |
423 | .irq_startup = iosapic_startup_level_irq, | |
424 | .irq_shutdown = iosapic_shutdown_level_irq, | |
425 | .irq_enable = iosapic_enable_level_irq, | |
426 | .irq_disable = iosapic_disable_level_irq, | |
427 | .irq_ack = iosapic_ack_level_irq, | |
428 | .irq_mask = mask_irq, | |
429 | .irq_unmask = iosapic_unmask_level_irq, | |
430 | .irq_set_affinity = iosapic_set_affinity | |
1da177e4 LT |
431 | }; |
432 | ||
433 | /* | |
434 | * Handlers for edge-triggered interrupts. | |
435 | */ | |
436 | ||
437 | static unsigned int | |
8fac171f | 438 | iosapic_startup_edge_irq (struct irq_data *data) |
1da177e4 | 439 | { |
8fac171f | 440 | unmask_irq(data); |
1da177e4 LT |
441 | /* |
442 | * IOSAPIC simply drops interrupts pended while the | |
443 | * corresponding pin was masked, so we can't know if an | |
444 | * interrupt is pending already. Let's hope not... | |
445 | */ | |
446 | return 0; | |
447 | } | |
448 | ||
449 | static void | |
8fac171f | 450 | iosapic_ack_edge_irq (struct irq_data *data) |
1da177e4 | 451 | { |
91ce72e0 TG |
452 | irq_complete_move(data->irq); |
453 | irq_move_irq(data); | |
1da177e4 LT |
454 | } |
455 | ||
456 | #define iosapic_enable_edge_irq unmask_irq | |
9505ec08 | 457 | #define iosapic_disable_edge_irq iosapic_nop |
1da177e4 | 458 | |
9e004ebd | 459 | static struct irq_chip irq_type_iosapic_edge = { |
8fac171f TG |
460 | .name = "IO-SAPIC-edge", |
461 | .irq_startup = iosapic_startup_edge_irq, | |
462 | .irq_shutdown = iosapic_disable_edge_irq, | |
463 | .irq_enable = iosapic_enable_edge_irq, | |
464 | .irq_disable = iosapic_disable_edge_irq, | |
465 | .irq_ack = iosapic_ack_edge_irq, | |
466 | .irq_mask = mask_irq, | |
467 | .irq_unmask = unmask_irq, | |
468 | .irq_set_affinity = iosapic_set_affinity | |
1da177e4 LT |
469 | }; |
470 | ||
9e004ebd | 471 | static unsigned int |
1da177e4 LT |
472 | iosapic_version (char __iomem *addr) |
473 | { | |
474 | /* | |
475 | * IOSAPIC Version Register return 32 bit structure like: | |
476 | * { | |
477 | * unsigned int version : 8; | |
478 | * unsigned int reserved1 : 8; | |
479 | * unsigned int max_redir : 8; | |
480 | * unsigned int reserved2 : 8; | |
481 | * } | |
482 | */ | |
c1726d6f | 483 | return __iosapic_read(addr, IOSAPIC_VERSION); |
1da177e4 LT |
484 | } |
485 | ||
4bbdec7a | 486 | static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol) |
24eeb568 | 487 | { |
4bbdec7a | 488 | int i, irq = -ENOSPC, min_count = -1; |
24eeb568 KK |
489 | struct iosapic_intr_info *info; |
490 | ||
491 | /* | |
492 | * shared vectors for edge-triggered interrupts are not | |
493 | * supported yet | |
494 | */ | |
495 | if (trigger == IOSAPIC_EDGE) | |
40598cbe | 496 | return -EINVAL; |
24eeb568 | 497 | |
5b592397 | 498 | for (i = 0; i < NR_IRQS; i++) { |
24eeb568 KK |
499 | info = &iosapic_intr_info[i]; |
500 | if (info->trigger == trigger && info->polarity == pol && | |
f8c087f3 YI |
501 | (info->dmode == IOSAPIC_FIXED || |
502 | info->dmode == IOSAPIC_LOWEST_PRIORITY) && | |
503 | can_request_irq(i, IRQF_SHARED)) { | |
24eeb568 | 504 | if (min_count == -1 || info->count < min_count) { |
4bbdec7a | 505 | irq = i; |
24eeb568 KK |
506 | min_count = info->count; |
507 | } | |
508 | } | |
509 | } | |
4bbdec7a | 510 | return irq; |
24eeb568 KK |
511 | } |
512 | ||
1da177e4 LT |
513 | /* |
514 | * if the given vector is already owned by other, | |
515 | * assign a new vector for the other and make the vector available | |
516 | */ | |
517 | static void __init | |
4bbdec7a | 518 | iosapic_reassign_vector (int irq) |
1da177e4 | 519 | { |
4bbdec7a | 520 | int new_irq; |
1da177e4 | 521 | |
c4c376f7 | 522 | if (iosapic_intr_info[irq].count) { |
4bbdec7a YI |
523 | new_irq = create_irq(); |
524 | if (new_irq < 0) | |
d4ed8084 | 525 | panic("%s: out of interrupt vectors!\n", __func__); |
46cba3dc | 526 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
4bbdec7a YI |
527 | irq_to_vector(irq), irq_to_vector(new_irq)); |
528 | memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq], | |
1da177e4 | 529 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
530 | INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes); |
531 | list_move(iosapic_intr_info[irq].rtes.next, | |
532 | &iosapic_intr_info[new_irq].rtes); | |
533 | memset(&iosapic_intr_info[irq], 0, | |
46cba3dc | 534 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
535 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; |
536 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); | |
1da177e4 LT |
537 | } |
538 | } | |
539 | ||
4bbdec7a | 540 | static inline int irq_is_shared (int irq) |
24eeb568 | 541 | { |
4bbdec7a | 542 | return (iosapic_intr_info[irq].count > 1); |
24eeb568 KK |
543 | } |
544 | ||
33b39e84 IY |
545 | struct irq_chip* |
546 | ia64_native_iosapic_get_irq_chip(unsigned long trigger) | |
547 | { | |
548 | if (trigger == IOSAPIC_EDGE) | |
549 | return &irq_type_iosapic_edge; | |
550 | else | |
551 | return &irq_type_iosapic_level; | |
552 | } | |
553 | ||
14454a1b | 554 | static int |
4bbdec7a | 555 | register_intr (unsigned int gsi, int irq, unsigned char delivery, |
1da177e4 LT |
556 | unsigned long polarity, unsigned long trigger) |
557 | { | |
dea1078e | 558 | struct irq_chip *chip, *irq_type; |
1da177e4 | 559 | int index; |
24eeb568 | 560 | struct iosapic_rte_info *rte; |
1da177e4 LT |
561 | |
562 | index = find_iosapic(gsi); | |
563 | if (index < 0) { | |
46cba3dc | 564 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
d4ed8084 | 565 | __func__, gsi); |
14454a1b | 566 | return -ENODEV; |
1da177e4 LT |
567 | } |
568 | ||
4bbdec7a | 569 | rte = find_rte(irq, gsi); |
24eeb568 | 570 | if (!rte) { |
4de0a759 | 571 | rte = kzalloc(sizeof (*rte), GFP_ATOMIC); |
24eeb568 | 572 | if (!rte) { |
46cba3dc | 573 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
d4ed8084 | 574 | __func__); |
14454a1b | 575 | return -ENOMEM; |
24eeb568 KK |
576 | } |
577 | ||
c5e3f9e5 YI |
578 | rte->iosapic = &iosapic_lists[index]; |
579 | rte->rte_index = gsi - rte->iosapic->gsi_base; | |
24eeb568 | 580 | rte->refcnt++; |
4bbdec7a YI |
581 | list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes); |
582 | iosapic_intr_info[irq].count++; | |
0e888adc | 583 | iosapic_lists[index].rtes_inuse++; |
24eeb568 | 584 | } |
e1b30a39 | 585 | else if (rte->refcnt == NO_REF_RTE) { |
4bbdec7a | 586 | struct iosapic_intr_info *info = &iosapic_intr_info[irq]; |
e1b30a39 YI |
587 | if (info->count > 0 && |
588 | (info->trigger != trigger || info->polarity != polarity)){ | |
46cba3dc ST |
589 | printk (KERN_WARNING |
590 | "%s: cannot override the interrupt\n", | |
d4ed8084 | 591 | __func__); |
14454a1b | 592 | return -EINVAL; |
24eeb568 | 593 | } |
e1b30a39 YI |
594 | rte->refcnt++; |
595 | iosapic_intr_info[irq].count++; | |
596 | iosapic_lists[index].rtes_inuse++; | |
24eeb568 KK |
597 | } |
598 | ||
4bbdec7a YI |
599 | iosapic_intr_info[irq].polarity = polarity; |
600 | iosapic_intr_info[irq].dmode = delivery; | |
601 | iosapic_intr_info[irq].trigger = trigger; | |
1da177e4 | 602 | |
33b39e84 | 603 | irq_type = iosapic_get_irq_chip(trigger); |
1da177e4 | 604 | |
dea1078e TG |
605 | chip = irq_get_chip(irq); |
606 | if (irq_type != NULL && chip != irq_type) { | |
607 | if (chip != &no_irq_chip) | |
46cba3dc ST |
608 | printk(KERN_WARNING |
609 | "%s: changing vector %d from %s to %s\n", | |
d4ed8084 | 610 | __func__, irq_to_vector(irq), |
dea1078e TG |
611 | chip->name, irq_type->name); |
612 | chip = irq_type; | |
1da177e4 | 613 | } |
59fb3d58 TG |
614 | irq_set_chip_handler_name_locked(irq_get_irq_data(irq), chip, |
615 | trigger == IOSAPIC_EDGE ? handle_edge_irq : handle_level_irq, | |
616 | NULL); | |
14454a1b | 617 | return 0; |
1da177e4 LT |
618 | } |
619 | ||
620 | static unsigned int | |
4bbdec7a | 621 | get_target_cpu (unsigned int gsi, int irq) |
1da177e4 LT |
622 | { |
623 | #ifdef CONFIG_SMP | |
624 | static int cpu = -1; | |
ff741906 | 625 | extern int cpe_vector; |
4994be1b | 626 | cpumask_t domain = irq_to_domain(irq); |
1da177e4 | 627 | |
24eeb568 KK |
628 | /* |
629 | * In case of vector shared by multiple RTEs, all RTEs that | |
630 | * share the vector need to use the same destination CPU. | |
631 | */ | |
c4c376f7 | 632 | if (iosapic_intr_info[irq].count) |
4bbdec7a | 633 | return iosapic_intr_info[irq].dest; |
24eeb568 | 634 | |
1da177e4 LT |
635 | /* |
636 | * If the platform supports redirection via XTP, let it | |
637 | * distribute interrupts. | |
638 | */ | |
639 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
640 | return cpu_physical_id(smp_processor_id()); | |
641 | ||
642 | /* | |
643 | * Some interrupts (ACPI SCI, for instance) are registered | |
644 | * before the BSP is marked as online. | |
645 | */ | |
646 | if (!cpu_online(smp_processor_id())) | |
647 | return cpu_physical_id(smp_processor_id()); | |
648 | ||
ff741906 | 649 | #ifdef CONFIG_ACPI |
4bbdec7a | 650 | if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR) |
b88e9265 | 651 | return get_cpei_target_cpu(); |
ff741906 AR |
652 | #endif |
653 | ||
1da177e4 LT |
654 | #ifdef CONFIG_NUMA |
655 | { | |
656 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
fbb776c3 | 657 | const struct cpumask *cpu_mask; |
1da177e4 LT |
658 | |
659 | iosapic_index = find_iosapic(gsi); | |
660 | if (iosapic_index < 0 || | |
661 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
662 | goto skip_numa_setup; | |
663 | ||
fbb776c3 RR |
664 | cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node); |
665 | num_cpus = 0; | |
666 | for_each_cpu_and(numa_cpu, cpu_mask, &domain) { | |
667 | if (cpu_online(numa_cpu)) | |
668 | num_cpus++; | |
1da177e4 LT |
669 | } |
670 | ||
1da177e4 LT |
671 | if (!num_cpus) |
672 | goto skip_numa_setup; | |
673 | ||
4bbdec7a YI |
674 | /* Use irq assignment to distribute across cpus in node */ |
675 | cpu_index = irq % num_cpus; | |
1da177e4 | 676 | |
fbb776c3 RR |
677 | for_each_cpu_and(numa_cpu, cpu_mask, &domain) |
678 | if (cpu_online(numa_cpu) && i++ >= cpu_index) | |
679 | break; | |
1da177e4 | 680 | |
fbb776c3 | 681 | if (numa_cpu < nr_cpu_ids) |
1da177e4 LT |
682 | return cpu_physical_id(numa_cpu); |
683 | } | |
684 | skip_numa_setup: | |
685 | #endif | |
686 | /* | |
687 | * Otherwise, round-robin interrupt vectors across all the | |
688 | * processors. (It'd be nice if we could be smarter in the | |
689 | * case of NUMA.) | |
690 | */ | |
691 | do { | |
fbb776c3 | 692 | if (++cpu >= nr_cpu_ids) |
1da177e4 | 693 | cpu = 0; |
5d2068da | 694 | } while (!cpu_online(cpu) || !cpumask_test_cpu(cpu, &domain)); |
1da177e4 LT |
695 | |
696 | return cpu_physical_id(cpu); | |
46cba3dc | 697 | #else /* CONFIG_SMP */ |
1da177e4 LT |
698 | return cpu_physical_id(smp_processor_id()); |
699 | #endif | |
700 | } | |
701 | ||
c9d059de KK |
702 | static inline unsigned char choose_dmode(void) |
703 | { | |
704 | #ifdef CONFIG_SMP | |
705 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
706 | return IOSAPIC_LOWEST_PRIORITY; | |
707 | #endif | |
708 | return IOSAPIC_FIXED; | |
709 | } | |
710 | ||
1da177e4 LT |
711 | /* |
712 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
713 | * methods. This provides an interface to register those interrupts and | |
714 | * program the IOSAPIC RTE. | |
715 | */ | |
716 | int | |
717 | iosapic_register_intr (unsigned int gsi, | |
718 | unsigned long polarity, unsigned long trigger) | |
719 | { | |
4bbdec7a | 720 | int irq, mask = 1, err; |
1da177e4 LT |
721 | unsigned int dest; |
722 | unsigned long flags; | |
24eeb568 KK |
723 | struct iosapic_rte_info *rte; |
724 | u32 low32; | |
c9d059de | 725 | unsigned char dmode; |
dea1078e | 726 | struct irq_desc *desc; |
40598cbe | 727 | |
1da177e4 LT |
728 | /* |
729 | * If this GSI has already been registered (i.e., it's a | |
730 | * shared interrupt, or we lost a race to register it), | |
731 | * don't touch the RTE. | |
732 | */ | |
733 | spin_lock_irqsave(&iosapic_lock, flags); | |
4bbdec7a YI |
734 | irq = __gsi_to_irq(gsi); |
735 | if (irq > 0) { | |
736 | rte = find_rte(irq, gsi); | |
e1b30a39 YI |
737 | if(iosapic_intr_info[irq].count == 0) { |
738 | assign_irq_vector(irq); | |
4debd723 | 739 | irq_init_desc(irq); |
e1b30a39 YI |
740 | } else if (rte->refcnt != NO_REF_RTE) { |
741 | rte->refcnt++; | |
742 | goto unlock_iosapic_lock; | |
743 | } | |
744 | } else | |
745 | irq = create_irq(); | |
24eeb568 KK |
746 | |
747 | /* If vector is running out, we try to find a sharable vector */ | |
eb21ab24 | 748 | if (irq < 0) { |
4bbdec7a YI |
749 | irq = iosapic_find_sharable_irq(trigger, polarity); |
750 | if (irq < 0) | |
40598cbe | 751 | goto unlock_iosapic_lock; |
4bbdec7a | 752 | } |
1da177e4 | 753 | |
dea1078e TG |
754 | desc = irq_to_desc(irq); |
755 | raw_spin_lock(&desc->lock); | |
4bbdec7a | 756 | dest = get_target_cpu(gsi, irq); |
c9d059de KK |
757 | dmode = choose_dmode(); |
758 | err = register_intr(gsi, irq, dmode, polarity, trigger); | |
e3a8f7b8 | 759 | if (err < 0) { |
dea1078e | 760 | raw_spin_unlock(&desc->lock); |
4bbdec7a | 761 | irq = err; |
224685c0 | 762 | goto unlock_iosapic_lock; |
1da177e4 | 763 | } |
e3a8f7b8 YI |
764 | |
765 | /* | |
766 | * If the vector is shared and already unmasked for other | |
767 | * interrupt sources, don't mask it. | |
768 | */ | |
4bbdec7a YI |
769 | low32 = iosapic_intr_info[irq].low32; |
770 | if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK)) | |
e3a8f7b8 | 771 | mask = 0; |
4bbdec7a | 772 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
773 | |
774 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
775 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
776 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 777 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
224685c0 | 778 | |
dea1078e | 779 | raw_spin_unlock(&desc->lock); |
40598cbe YI |
780 | unlock_iosapic_lock: |
781 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
4bbdec7a | 782 | return irq; |
1da177e4 LT |
783 | } |
784 | ||
1da177e4 LT |
785 | void |
786 | iosapic_unregister_intr (unsigned int gsi) | |
787 | { | |
788 | unsigned long flags; | |
4bbdec7a | 789 | int irq, index; |
24eeb568 | 790 | u32 low32; |
1da177e4 | 791 | unsigned long trigger, polarity; |
24eeb568 KK |
792 | unsigned int dest; |
793 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
794 | |
795 | /* | |
796 | * If the irq associated with the gsi is not found, | |
797 | * iosapic_unregister_intr() is unbalanced. We need to check | |
798 | * this again after getting locks. | |
799 | */ | |
800 | irq = gsi_to_irq(gsi); | |
801 | if (irq < 0) { | |
46cba3dc ST |
802 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
803 | gsi); | |
1da177e4 LT |
804 | WARN_ON(1); |
805 | return; | |
806 | } | |
1da177e4 | 807 | |
40598cbe | 808 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 809 | if ((rte = find_rte(irq, gsi)) == NULL) { |
e3a8f7b8 YI |
810 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
811 | gsi); | |
812 | WARN_ON(1); | |
813 | goto out; | |
814 | } | |
1da177e4 | 815 | |
e3a8f7b8 YI |
816 | if (--rte->refcnt > 0) |
817 | goto out; | |
1da177e4 | 818 | |
e1b30a39 | 819 | rte->refcnt = NO_REF_RTE; |
40598cbe | 820 | |
e3a8f7b8 | 821 | /* Mask the interrupt */ |
4bbdec7a | 822 | low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK; |
c1726d6f | 823 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32); |
1da177e4 | 824 | |
4bbdec7a | 825 | iosapic_intr_info[irq].count--; |
e3a8f7b8 YI |
826 | index = find_iosapic(gsi); |
827 | iosapic_lists[index].rtes_inuse--; | |
828 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
24eeb568 | 829 | |
4bbdec7a YI |
830 | trigger = iosapic_intr_info[irq].trigger; |
831 | polarity = iosapic_intr_info[irq].polarity; | |
832 | dest = iosapic_intr_info[irq].dest; | |
e3a8f7b8 YI |
833 | printk(KERN_INFO |
834 | "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
835 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
836 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 837 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
24eeb568 | 838 | |
e1b30a39 | 839 | if (iosapic_intr_info[irq].count == 0) { |
451fe00c | 840 | #ifdef CONFIG_SMP |
e3a8f7b8 | 841 | /* Clear affinity */ |
c42574ed | 842 | cpumask_setall(irq_get_affinity_mask(irq)); |
451fe00c | 843 | #endif |
e3a8f7b8 | 844 | /* Clear the interrupt information */ |
e1b30a39 YI |
845 | iosapic_intr_info[irq].dest = 0; |
846 | iosapic_intr_info[irq].dmode = 0; | |
847 | iosapic_intr_info[irq].polarity = 0; | |
848 | iosapic_intr_info[irq].trigger = 0; | |
4bbdec7a | 849 | iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
1da177e4 | 850 | |
e1b30a39 YI |
851 | /* Destroy and reserve IRQ */ |
852 | destroy_and_reserve_irq(irq); | |
1da177e4 | 853 | } |
24eeb568 | 854 | out: |
40598cbe | 855 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 | 856 | } |
1da177e4 LT |
857 | |
858 | /* | |
859 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
860 | */ |
861 | int __init | |
862 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
863 | int iosapic_vector, u16 eid, u16 id, | |
864 | unsigned long polarity, unsigned long trigger) | |
865 | { | |
866 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
867 | unsigned char delivery; | |
eb21ab24 | 868 | int irq, vector, mask = 0; |
1da177e4 LT |
869 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
870 | ||
871 | switch (int_type) { | |
872 | case ACPI_INTERRUPT_PMI: | |
e1b30a39 | 873 | irq = vector = iosapic_vector; |
4994be1b | 874 | bind_irq_vector(irq, vector, CPU_MASK_ALL); |
1da177e4 LT |
875 | /* |
876 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
877 | * we need to make sure the vector is available | |
878 | */ | |
4bbdec7a | 879 | iosapic_reassign_vector(irq); |
1da177e4 LT |
880 | delivery = IOSAPIC_PMI; |
881 | break; | |
882 | case ACPI_INTERRUPT_INIT: | |
eb21ab24 YI |
883 | irq = create_irq(); |
884 | if (irq < 0) | |
d4ed8084 | 885 | panic("%s: out of interrupt vectors!\n", __func__); |
eb21ab24 | 886 | vector = irq_to_vector(irq); |
1da177e4 LT |
887 | delivery = IOSAPIC_INIT; |
888 | break; | |
889 | case ACPI_INTERRUPT_CPEI: | |
e1b30a39 | 890 | irq = vector = IA64_CPE_VECTOR; |
4994be1b | 891 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
aa0ebec9 | 892 | delivery = IOSAPIC_FIXED; |
1da177e4 LT |
893 | mask = 1; |
894 | break; | |
895 | default: | |
d4ed8084 | 896 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__, |
46cba3dc | 897 | int_type); |
1da177e4 LT |
898 | return -1; |
899 | } | |
900 | ||
4bbdec7a | 901 | register_intr(gsi, irq, delivery, polarity, trigger); |
1da177e4 | 902 | |
46cba3dc ST |
903 | printk(KERN_INFO |
904 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
905 | " vector %d\n", | |
1da177e4 LT |
906 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
907 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
908 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
909 | cpu_logical_id(dest), dest, vector); | |
910 | ||
4bbdec7a | 911 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
912 | return vector; |
913 | } | |
914 | ||
1da177e4 LT |
915 | /* |
916 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 | 917 | */ |
5b5e76e9 GKH |
918 | void iosapic_override_isa_irq(unsigned int isa_irq, unsigned int gsi, |
919 | unsigned long polarity, unsigned long trigger) | |
1da177e4 | 920 | { |
4bbdec7a | 921 | int vector, irq; |
1da177e4 | 922 | unsigned int dest = cpu_physical_id(smp_processor_id()); |
c9d059de | 923 | unsigned char dmode; |
1da177e4 | 924 | |
e1b30a39 | 925 | irq = vector = isa_irq_to_vector(isa_irq); |
4994be1b | 926 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
c9d059de KK |
927 | dmode = choose_dmode(); |
928 | register_intr(gsi, irq, dmode, polarity, trigger); | |
1da177e4 LT |
929 | |
930 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
931 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
932 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
933 | cpu_logical_id(dest), dest, vector); | |
934 | ||
4bbdec7a | 935 | set_rte(gsi, irq, dest, 1); |
1da177e4 LT |
936 | } |
937 | ||
33b39e84 IY |
938 | void __init |
939 | ia64_native_iosapic_pcat_compat_init(void) | |
940 | { | |
941 | if (pcat_compat) { | |
942 | /* | |
943 | * Disable the compatibility mode interrupts (8259 style), | |
944 | * needs IN/OUT support enabled. | |
945 | */ | |
946 | printk(KERN_INFO | |
947 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
948 | __func__); | |
949 | outb(0xff, 0xA1); | |
950 | outb(0xff, 0x21); | |
951 | } | |
952 | } | |
953 | ||
1da177e4 LT |
954 | void __init |
955 | iosapic_system_init (int system_pcat_compat) | |
956 | { | |
4bbdec7a | 957 | int irq; |
1da177e4 | 958 | |
4bbdec7a YI |
959 | for (irq = 0; irq < NR_IRQS; ++irq) { |
960 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; | |
46cba3dc | 961 | /* mark as unused */ |
4bbdec7a | 962 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); |
e1b30a39 YI |
963 | |
964 | iosapic_intr_info[irq].count = 0; | |
24eeb568 | 965 | } |
1da177e4 LT |
966 | |
967 | pcat_compat = system_pcat_compat; | |
33b39e84 IY |
968 | if (pcat_compat) |
969 | iosapic_pcat_compat_init(); | |
1da177e4 LT |
970 | } |
971 | ||
0e888adc KK |
972 | static inline int |
973 | iosapic_alloc (void) | |
974 | { | |
975 | int index; | |
976 | ||
977 | for (index = 0; index < NR_IOSAPICS; index++) | |
978 | if (!iosapic_lists[index].addr) | |
979 | return index; | |
980 | ||
d4ed8084 | 981 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__); |
0e888adc KK |
982 | return -1; |
983 | } | |
984 | ||
985 | static inline void | |
986 | iosapic_free (int index) | |
987 | { | |
988 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
989 | } | |
990 | ||
991 | static inline int | |
992 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
993 | { | |
994 | int index; | |
995 | unsigned int gsi_end, base, end; | |
996 | ||
997 | /* check gsi range */ | |
998 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
999 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1000 | if (!iosapic_lists[index].addr) | |
1001 | continue; | |
1002 | ||
1003 | base = iosapic_lists[index].gsi_base; | |
1004 | end = base + iosapic_lists[index].num_rte - 1; | |
1005 | ||
e6d1ba5c | 1006 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1007 | continue; /* OK */ |
1008 | ||
1009 | return -EBUSY; | |
1010 | } | |
1011 | return 0; | |
1012 | } | |
1013 | ||
ffa90955 HG |
1014 | static int |
1015 | iosapic_delete_rte(unsigned int irq, unsigned int gsi) | |
1016 | { | |
1017 | struct iosapic_rte_info *rte, *temp; | |
1018 | ||
1019 | list_for_each_entry_safe(rte, temp, &iosapic_intr_info[irq].rtes, | |
1020 | rte_list) { | |
1021 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) { | |
1022 | if (rte->refcnt) | |
1023 | return -EBUSY; | |
1024 | ||
1025 | list_del(&rte->rte_list); | |
1026 | kfree(rte); | |
1027 | return 0; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | return -EINVAL; | |
1032 | } | |
1033 | ||
5b5e76e9 | 1034 | int iosapic_init(unsigned long phys_addr, unsigned int gsi_base) |
1da177e4 | 1035 | { |
0e888adc | 1036 | int num_rte, err, index; |
1da177e4 LT |
1037 | unsigned int isa_irq, ver; |
1038 | char __iomem *addr; | |
0e888adc KK |
1039 | unsigned long flags; |
1040 | ||
1041 | spin_lock_irqsave(&iosapic_lock, flags); | |
c1726d6f YI |
1042 | index = find_iosapic(gsi_base); |
1043 | if (index >= 0) { | |
1044 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1045 | return -EBUSY; | |
1046 | } | |
1047 | ||
e3a8f7b8 | 1048 | addr = ioremap(phys_addr, 0); |
e7369e01 RK |
1049 | if (addr == NULL) { |
1050 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1051 | return -ENOMEM; | |
1052 | } | |
e3a8f7b8 | 1053 | ver = iosapic_version(addr); |
e3a8f7b8 YI |
1054 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1055 | iounmap(addr); | |
1056 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1057 | return err; | |
1058 | } | |
1da177e4 | 1059 | |
e3a8f7b8 YI |
1060 | /* |
1061 | * The MAX_REDIR register holds the highest input pin number | |
1062 | * (starting from 0). We add 1 so that we can use it for | |
1063 | * number of pins (= RTEs) | |
1064 | */ | |
1065 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1066 | |
e3a8f7b8 YI |
1067 | index = iosapic_alloc(); |
1068 | iosapic_lists[index].addr = addr; | |
1069 | iosapic_lists[index].gsi_base = gsi_base; | |
1070 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1071 | #ifdef CONFIG_NUMA |
e3a8f7b8 | 1072 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1073 | #endif |
c1726d6f | 1074 | spin_lock_init(&iosapic_lists[index].lock); |
0e888adc | 1075 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 LT |
1076 | |
1077 | if ((gsi_base == 0) && pcat_compat) { | |
1078 | /* | |
46cba3dc ST |
1079 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1080 | * these may get reprogrammed later on with data from the ACPI | |
1081 | * Interrupt Source Override table. | |
1da177e4 LT |
1082 | */ |
1083 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1084 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1085 | IOSAPIC_POL_HIGH, | |
1086 | IOSAPIC_EDGE); | |
1da177e4 | 1087 | } |
0e888adc KK |
1088 | return 0; |
1089 | } | |
1090 | ||
5b5e76e9 | 1091 | int iosapic_remove(unsigned int gsi_base) |
0e888adc | 1092 | { |
ffa90955 | 1093 | int i, irq, index, err = 0; |
0e888adc KK |
1094 | unsigned long flags; |
1095 | ||
1096 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
1097 | index = find_iosapic(gsi_base); |
1098 | if (index < 0) { | |
1099 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
d4ed8084 | 1100 | __func__, gsi_base); |
e3a8f7b8 YI |
1101 | goto out; |
1102 | } | |
0e888adc | 1103 | |
e3a8f7b8 YI |
1104 | if (iosapic_lists[index].rtes_inuse) { |
1105 | err = -EBUSY; | |
1106 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
d4ed8084 | 1107 | __func__, gsi_base); |
e3a8f7b8 | 1108 | goto out; |
0e888adc | 1109 | } |
e3a8f7b8 | 1110 | |
ffa90955 HG |
1111 | for (i = gsi_base; i < gsi_base + iosapic_lists[index].num_rte; i++) { |
1112 | irq = __gsi_to_irq(i); | |
1113 | if (irq < 0) | |
1114 | continue; | |
1115 | ||
1116 | err = iosapic_delete_rte(irq, i); | |
1117 | if (err) | |
1118 | goto out; | |
1119 | } | |
1120 | ||
e3a8f7b8 YI |
1121 | iounmap(iosapic_lists[index].addr); |
1122 | iosapic_free(index); | |
0e888adc KK |
1123 | out: |
1124 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1125 | return err; | |
1da177e4 LT |
1126 | } |
1127 | ||
1128 | #ifdef CONFIG_NUMA | |
5b5e76e9 | 1129 | void map_iosapic_to_node(unsigned int gsi_base, int node) |
1da177e4 LT |
1130 | { |
1131 | int index; | |
1132 | ||
1133 | index = find_iosapic(gsi_base); | |
1134 | if (index < 0) { | |
1135 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
d4ed8084 | 1136 | __func__, gsi_base); |
1da177e4 LT |
1137 | return; |
1138 | } | |
1139 | iosapic_lists[index].node = node; | |
1140 | return; | |
1141 | } | |
1142 | #endif |