[mirror_ubuntu-kernels.git] / arch / ia64 / kernel / irq_ia64.c

/*
 * linux/arch/ia64/kernel/irq_ia64.c
 *
 * Copyright (C) 1998-2001 Hewlett-Packard Co
 *	Stephane Eranian <eranian@hpl.hp.com>
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 *  6/10/99: Updated to bring in sync with x86 version to facilitate
 *	     support for SMP and different interrupt controllers.
 *
 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
 *                      PCI to vector allocation routine.
 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
 *						Added CPU Hotplug handling for IPF.
 */

#include <linux/module.h>

#include <linux/jiffies.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel_stat.h>
#include <linux/slab.h>
#include <linux/ptrace.h>
#include <linux/random.h>	/* for rand_initialize_irq() */
#include <linux/signal.h>
#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/bitops.h>
#include <linux/irq.h>

#include <asm/delay.h>
#include <asm/intrinsics.h>
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/machvec.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbflush.h>

#ifdef CONFIG_PERFMON
# include <asm/perfmon.h>
#endif

#define IRQ_DEBUG	0

#define IRQ_VECTOR_UNASSIGNED	(0)

#define IRQ_UNUSED		(0)
#define IRQ_USED		(1)
#define IRQ_RSVD		(2)

/* These can be overridden in platform_irq_init */
int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;

/* default base addr of IPI table */
void __iomem *ipi_base_addr = ((void __iomem *)
			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));

static cpumask_t vector_allocation_domain(int cpu);

/*
 * Legacy IRQ to IA-64 vector translation table.
 */
__u8 isa_irq_to_vector_map[16] = {
	/* 8259 IRQ translation, first 16 entries */
	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
};
EXPORT_SYMBOL(isa_irq_to_vector_map);

DEFINE_SPINLOCK(vector_lock);

struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
	[0 ... NR_IRQS - 1] = {
		.vector = IRQ_VECTOR_UNASSIGNED,
		.domain = CPU_MASK_NONE
	}
};

DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	[0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
};

static cpumask_t vector_table[IA64_MAX_DEVICE_VECTORS] = {
	[0 ... IA64_MAX_DEVICE_VECTORS - 1] = CPU_MASK_NONE
};

static int irq_status[NR_IRQS] = {
	[0 ... NR_IRQS -1] = IRQ_UNUSED
};

int check_irq_used(int irq)
{
	if (irq_status[irq] == IRQ_USED)
		return 1;

	return -1;
}

static void reserve_irq(unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	irq_status[irq] = IRQ_RSVD;
	spin_unlock_irqrestore(&vector_lock, flags);
}

static inline int find_unassigned_irq(void)
{
	int irq;

	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
		if (irq_status[irq] == IRQ_UNUSED)
			return irq;
	return -ENOSPC;
}

static inline int find_unassigned_vector(cpumask_t domain)
{
	cpumask_t mask;
	int pos;

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;

	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
		cpus_and(mask, domain, vector_table[pos]);
		if (!cpus_empty(mask))
			continue;
		return IA64_FIRST_DEVICE_VECTOR + pos;
	}
	return -ENOSPC;
}

static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	cpumask_t mask;
	int cpu, pos;
	struct irq_cfg *cfg = &irq_cfg[irq];

	cpus_and(mask, domain, cpu_online_map);
	if (cpus_empty(mask))
		return -EINVAL;
	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
		return 0;
	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
		return -EBUSY;
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = irq;
	cfg->vector = vector;
	cfg->domain = domain;
	irq_status[irq] = IRQ_USED;
	pos = vector - IA64_FIRST_DEVICE_VECTOR;
	cpus_or(vector_table[pos], vector_table[pos], domain);
	return 0;
}

int bind_irq_vector(int irq, int vector, cpumask_t domain)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __bind_irq_vector(irq, vector, domain);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

static void __clear_irq_vector(int irq)
{
	int vector, cpu, pos;
	cpumask_t mask;
	cpumask_t domain;
	struct irq_cfg *cfg = &irq_cfg[irq];

	BUG_ON((unsigned)irq >= NR_IRQS);
	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	vector = cfg->vector;
	domain = cfg->domain;
	cpus_and(mask, cfg->domain, cpu_online_map);
	for_each_cpu_mask(cpu, mask)
		per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
	cfg->vector = IRQ_VECTOR_UNASSIGNED;
	cfg->domain = CPU_MASK_NONE;
	irq_status[irq] = IRQ_UNUSED;
	pos = vector - IA64_FIRST_DEVICE_VECTOR;
	cpus_andnot(vector_table[pos], vector_table[pos], domain);
}

static void clear_irq_vector(int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&vector_lock, flags);
	__clear_irq_vector(irq);
	spin_unlock_irqrestore(&vector_lock, flags);
}

int
assign_irq_vector (int irq)
{
	unsigned long flags;
	int vector, cpu;
	cpumask_t domain;

	vector = -ENOSPC;

	spin_lock_irqsave(&vector_lock, flags);
	if (irq < 0) {
		goto out;
	}
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	return vector;
}

void
free_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return;
	clear_irq_vector(vector);
}

int
reserve_irq_vector (int vector)
{
	if (vector < IA64_FIRST_DEVICE_VECTOR ||
	    vector > IA64_LAST_DEVICE_VECTOR)
		return -EINVAL;
	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
}

/*
 * Initialize vector_irq on a new cpu. This function must be called
 * with vector_lock held.
 */
void __setup_vector_irq(int cpu)
{
	int irq, vector;

	/* Clear vector_irq */
	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
		per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
	/* Mark the inuse vectors */
	for (irq = 0; irq < NR_IRQS; ++irq) {
		if (!cpu_isset(cpu, irq_cfg[irq].domain))
			continue;
		vector = irq_to_vector(irq);
		per_cpu(vector_irq, cpu)[vector] = irq;
	}
}

#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
static enum vector_domain_type {
	VECTOR_DOMAIN_NONE,
	VECTOR_DOMAIN_PERCPU
} vector_domain_type = VECTOR_DOMAIN_NONE;

static cpumask_t vector_allocation_domain(int cpu)
{
	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
		return cpumask_of_cpu(cpu);
	return CPU_MASK_ALL;
}

static int __init parse_vector_domain(char *arg)
{
	if (!arg)
		return -EINVAL;
	if (!strcmp(arg, "percpu")) {
		vector_domain_type = VECTOR_DOMAIN_PERCPU;
		no_int_routing = 1;
	}
	return 1;
}
early_param("vector", parse_vector_domain);
#else
static cpumask_t vector_allocation_domain(int cpu)
{
	return CPU_MASK_ALL;
}
#endif


void destroy_and_reserve_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);

	clear_irq_vector(irq);
	reserve_irq(irq);
}

static int __reassign_irq_vector(int irq, int cpu)
{
	struct irq_cfg *cfg = &irq_cfg[irq];
	int vector;
	cpumask_t domain;

	if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
		return -EINVAL;
	if (cpu_isset(cpu, cfg->domain))
		return 0;
	domain = vector_allocation_domain(cpu);
	vector = find_unassigned_vector(domain);
	if (vector < 0)
		return -ENOSPC;
	__clear_irq_vector(irq);
	BUG_ON(__bind_irq_vector(irq, vector, domain));
	return 0;
}

int reassign_irq_vector(int irq, int cpu)
{
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&vector_lock, flags);
	ret = __reassign_irq_vector(irq, cpu);
	spin_unlock_irqrestore(&vector_lock, flags);
	return ret;
}

/*
 * Dynamic irq allocate and deallocation for MSI
 */
int create_irq(void)
{
	unsigned long flags;
	int irq, vector, cpu;
	cpumask_t domain;

	irq = vector = -ENOSPC;
	spin_lock_irqsave(&vector_lock, flags);
	for_each_online_cpu(cpu) {
		domain = vector_allocation_domain(cpu);
		vector = find_unassigned_vector(domain);
		if (vector >= 0)
			break;
	}
	if (vector < 0)
		goto out;
	irq = find_unassigned_irq();
	if (irq < 0)
		goto out;
	BUG_ON(__bind_irq_vector(irq, vector, domain));
 out:
	spin_unlock_irqrestore(&vector_lock, flags);
	if (irq >= 0)
		dynamic_irq_init(irq);
	return irq;
}

void destroy_irq(unsigned int irq)
{
	dynamic_irq_cleanup(irq);
	clear_irq_vector(irq);
}

#ifdef CONFIG_SMP
#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
#	define IS_LOCAL_TLB_FLUSH(vec)	(vec == IA64_IPI_LOCAL_TLB_FLUSH)
#else
#	define IS_RESCHEDULE(vec)	(0)
#	define IS_LOCAL_TLB_FLUSH(vec)	(0)
#endif
/*
 * That's where the IVT branches when we get an external
 * interrupt. This branches to the correct hardware IRQ handler via
 * function ptr.
 */
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	unsigned long saved_tpr;

#if IRQ_DEBUG
	{
		unsigned long bsp, sp;

		/*
		 * Note: if the interrupt happened while executing in
		 * the context switch routine (ia64_switch_to), we may
		 * get a spurious stack overflow here.  This is
		 * because the register and the memory stack are not
		 * switched atomically.
		 */
		bsp = ia64_getreg(_IA64_REG_AR_BSP);
		sp = ia64_getreg(_IA64_REG_SP);

		if ((sp - bsp) < 1024) {
			static unsigned char count;
			static long last_time;

			if (jiffies - last_time > 5*HZ)
				count = 0;
			if (++count < 5) {
				last_time = jiffies;
				printk("ia64_handle_irq: DANGER: less than "
				       "1KB of free stack space!!\n"
				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
			}
		}
	}
#endif /* IRQ_DEBUG */

	/*
	 * Always set TPR to limit maximum interrupt nesting depth to
	 * 16 (without this, it would be ~240, which could easily lead
	 * to kernel stack overflows).
	 */
	irq_enter();
	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	ia64_srlz_d();
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			generic_handle_irq(local_vector_to_irq(vector));

			/*
			 * Disable interrupts and send EOI:
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	/*
	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
	 * handler needs to be able to wait for further keyboard interrupts, which can't
	 * come through until ia64_eoi() has been done.
	 */
	irq_exit();
	set_irq_regs(old_regs);
}

#ifdef CONFIG_HOTPLUG_CPU
/*
 * This function emulates a interrupt processing when a cpu is about to be
 * brought down.
 */
void ia64_process_pending_intr(void)
{
	ia64_vector vector;
	unsigned long saved_tpr;
	extern unsigned int vectors_in_migration[NR_IRQS];

	vector = ia64_get_ivr();

	 irq_enter();
	 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	 ia64_srlz_d();

	 /*
	  * Perform normal interrupt style processing
	  */
	while (vector != IA64_SPURIOUS_INT_VECTOR) {
		if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
			smp_local_flush_tlb();
			kstat_this_cpu.irqs[vector]++;
		} else if (unlikely(IS_RESCHEDULE(vector)))
			kstat_this_cpu.irqs[vector]++;
		else {
			struct pt_regs *old_regs = set_irq_regs(NULL);

			ia64_setreg(_IA64_REG_CR_TPR, vector);
			ia64_srlz_d();

			/*
			 * Now try calling normal ia64_handle_irq as it would have got called
			 * from a real intr handler. Try passing null for pt_regs, hopefully
			 * it will work. I hope it works!.
			 * Probably could shared code.
			 */
			vectors_in_migration[local_vector_to_irq(vector)]=0;
			generic_handle_irq(local_vector_to_irq(vector));
			set_irq_regs(old_regs);

			/*
			 * Disable interrupts and send EOI
			 */
			local_irq_disable();
			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
		}
		ia64_eoi();
		vector = ia64_get_ivr();
	}
	irq_exit();
}
#endif


#ifdef CONFIG_SMP

static irqreturn_t dummy_handler (int irq, void *dev_id)
{
	BUG();
}
extern irqreturn_t handle_IPI (int irq, void *dev_id);

static struct irqaction ipi_irqaction = {
	.handler =	handle_IPI,
	.flags =	IRQF_DISABLED,
	.name =		"IPI"
};

static struct irqaction resched_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"resched"
};

static struct irqaction tlb_irqaction = {
	.handler =	dummy_handler,
	.flags =	IRQF_DISABLED,
	.name =		"tlb_flush"
};

#endif

void
register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
	irq_desc_t *desc;
	unsigned int irq;

	irq = vec;
	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
	desc = irq_desc + irq;
	desc->status |= IRQ_PER_CPU;
	desc->chip = &irq_type_ia64_lsapic;
	if (action)
		setup_irq(irq, action);
}

void __init
init_IRQ (void)
{
	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
#ifdef CONFIG_SMP
	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
#endif
#ifdef CONFIG_PERFMON
	pfm_init_percpu();
#endif
	platform_irq_init();
}

void
ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
{
	void __iomem *ipi_addr;
	unsigned long ipi_data;
	unsigned long phys_cpu_id;

#ifdef CONFIG_SMP
	phys_cpu_id = cpu_physical_id(cpu);
#else
	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
#endif

	/*
	 * cpu number is in 8bit ID and 8bit EID
	 */

	ipi_data = (delivery_mode << 8) | (vector & 0xff);
	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));

	writeq(ipi_data, ipi_addr);
}
Commit	Line	Data
1da177e4	1	/*
f30c2269	2	* linux/arch/ia64/kernel/irq_ia64.c
1da177e4 LT	3	*
	4	* Copyright (C) 1998-2001 Hewlett-Packard Co
	5	* Stephane Eranian <eranian@hpl.hp.com>
	6	* David Mosberger-Tang <davidm@hpl.hp.com>
	7	*
	8	* 6/10/99: Updated to bring in sync with x86 version to facilitate
	9	* support for SMP and different interrupt controllers.
	10	*
	11	* 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
	12	* PCI to vector allocation routine.
	13	* 04/14/2004 Ashok Raj <ashok.raj@intel.com>
	14	* Added CPU Hotplug handling for IPF.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18
	19	#include <linux/jiffies.h>
	20	#include <linux/errno.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/ioport.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/slab.h>
	26	#include <linux/ptrace.h>
	27	#include <linux/random.h> /* for rand_initialize_irq() */
	28	#include <linux/signal.h>
	29	#include <linux/smp.h>
1da177e4 LT	30	#include <linux/threads.h>
1da177e4 LT	31	#include <linux/bitops.h>
b6cf2583	32	#include <linux/irq.h>
1da177e4 LT	33
	34	#include <asm/delay.h>
	35	#include <asm/intrinsics.h>
	36	#include <asm/io.h>
	37	#include <asm/hw_irq.h>
	38	#include <asm/machvec.h>
	39	#include <asm/pgtable.h>
	40	#include <asm/system.h>
3be44b9c	41	#include <asm/tlbflush.h>
1da177e4 LT	42
	43	#ifdef CONFIG_PERFMON
	44	# include <asm/perfmon.h>
	45	#endif
	46
	47	#define IRQ_DEBUG 0
	48
e1b30a39 YI	49	#define IRQ_VECTOR_UNASSIGNED (0)
	50
	51	#define IRQ_UNUSED (0)
	52	#define IRQ_USED (1)
	53	#define IRQ_RSVD (2)
	54
10083072 MM	55	/* These can be overridden in platform_irq_init */
	56	int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
	57	int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
	58
1da177e4 LT	59	/* default base addr of IPI table */
	60	void __iomem ipi_base_addr = ((void __iomem )
	61	(__IA64_UNCACHED_OFFSET \| IA64_IPI_DEFAULT_BASE_ADDR));
	62
4994be1b YI	63	static cpumask_t vector_allocation_domain(int cpu);
4994be1b YI	64
1da177e4 LT	65	/*
	66	* Legacy IRQ to IA-64 vector translation table.
	67	*/
	68	__u8 isa_irq_to_vector_map[16] = {
	69	/* 8259 IRQ translation, first 16 entries */
	70	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
	71	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
	72	};
	73	EXPORT_SYMBOL(isa_irq_to_vector_map);
	74
e1b30a39 YI	75	DEFINE_SPINLOCK(vector_lock);
	76
	77	struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
4994be1b YI	78	[0 ... NR_IRQS - 1] = {
	79	.vector = IRQ_VECTOR_UNASSIGNED,
	80	.domain = CPU_MASK_NONE
	81	}
e1b30a39 YI	82	};
	83
	84	DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
	85	[0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
	86	};
	87
4994be1b YI	88	static cpumask_t vector_table[IA64_MAX_DEVICE_VECTORS] = {
	89	[0 ... IA64_MAX_DEVICE_VECTORS - 1] = CPU_MASK_NONE
	90	};
	91
e1b30a39 YI	92	static int irq_status[NR_IRQS] = {
	93	[0 ... NR_IRQS -1] = IRQ_UNUSED
	94	};
	95
	96	int check_irq_used(int irq)
	97	{
	98	if (irq_status[irq] == IRQ_USED)
	99	return 1;
	100
	101	return -1;
	102	}
	103
	104	static void reserve_irq(unsigned int irq)
	105	{
	106	unsigned long flags;
	107
	108	spin_lock_irqsave(&vector_lock, flags);
	109	irq_status[irq] = IRQ_RSVD;
	110	spin_unlock_irqrestore(&vector_lock, flags);
	111	}
	112
	113	static inline int find_unassigned_irq(void)
	114	{
	115	int irq;
	116
	117	for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
	118	if (irq_status[irq] == IRQ_UNUSED)
	119	return irq;
	120	return -ENOSPC;
	121	}
	122
4994be1b	123	static inline int find_unassigned_vector(cpumask_t domain)
e1b30a39	124	{
4994be1b YI	125	cpumask_t mask;
	126	int pos;
	127
	128	cpus_and(mask, domain, cpu_online_map);
	129	if (cpus_empty(mask))
	130	return -EINVAL;
e1b30a39	131
4994be1b YI	132	for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
	133	cpus_and(mask, domain, vector_table[pos]);
	134	if (!cpus_empty(mask))
	135	continue;
	136	return IA64_FIRST_DEVICE_VECTOR + pos;
	137	}
e1b30a39 YI	138	return -ENOSPC;
	139	}
	140
4994be1b	141	static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39	142	{
4994be1b YI	143	cpumask_t mask;
	144	int cpu, pos;
	145	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	146
4994be1b YI	147	cpus_and(mask, domain, cpu_online_map);
	148	if (cpus_empty(mask))
	149	return -EINVAL;
	150	if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
e1b30a39	151	return 0;
4994be1b	152	if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
e1b30a39	153	return -EBUSY;
4994be1b	154	for_each_cpu_mask(cpu, mask)
e1b30a39	155	per_cpu(vector_irq, cpu)[vector] = irq;
4994be1b YI	156	cfg->vector = vector;
4994be1b YI	157	cfg->domain = domain;
e1b30a39	158	irq_status[irq] = IRQ_USED;
4994be1b YI	159	pos = vector - IA64_FIRST_DEVICE_VECTOR;
4994be1b YI	160	cpus_or(vector_table[pos], vector_table[pos], domain);
e1b30a39 YI	161	return 0;
	162	}
	163
4994be1b	164	int bind_irq_vector(int irq, int vector, cpumask_t domain)
e1b30a39 YI	165	{
	166	unsigned long flags;
	167	int ret;
	168
	169	spin_lock_irqsave(&vector_lock, flags);
4994be1b	170	ret = __bind_irq_vector(irq, vector, domain);
e1b30a39 YI	171	spin_unlock_irqrestore(&vector_lock, flags);
	172	return ret;
	173	}
	174
cd378f18	175	static void __clear_irq_vector(int irq)
e1b30a39	176	{
4994be1b YI	177	int vector, cpu, pos;
	178	cpumask_t mask;
	179	cpumask_t domain;
	180	struct irq_cfg *cfg = &irq_cfg[irq];
e1b30a39	181
e1b30a39	182	BUG_ON((unsigned)irq >= NR_IRQS);
4994be1b YI	183	BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
	184	vector = cfg->vector;
	185	domain = cfg->domain;
	186	cpus_and(mask, cfg->domain, cpu_online_map);
	187	for_each_cpu_mask(cpu, mask)
e1b30a39	188	per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
4994be1b YI	189	cfg->vector = IRQ_VECTOR_UNASSIGNED;
4994be1b YI	190	cfg->domain = CPU_MASK_NONE;
e1b30a39	191	irq_status[irq] = IRQ_UNUSED;
4994be1b YI	192	pos = vector - IA64_FIRST_DEVICE_VECTOR;
4994be1b YI	193	cpus_andnot(vector_table[pos], vector_table[pos], domain);
cd378f18 YI	194	}
	195
	196	static void clear_irq_vector(int irq)
	197	{
	198	unsigned long flags;
	199
	200	spin_lock_irqsave(&vector_lock, flags);
	201	__clear_irq_vector(irq);
e1b30a39 YI	202	spin_unlock_irqrestore(&vector_lock, flags);
e1b30a39 YI	203	}
1da177e4 LT	204
1da177e4 LT	205	int
3b5cc090	206	assign_irq_vector (int irq)
1da177e4	207	{
e1b30a39	208	unsigned long flags;
4994be1b YI	209	int vector, cpu;
	210	cpumask_t domain;
	211
	212	vector = -ENOSPC;
e1b30a39	213
4994be1b	214	spin_lock_irqsave(&vector_lock, flags);
e1b30a39 YI	215	if (irq < 0) {
	216	goto out;
	217	}
4994be1b YI	218	for_each_online_cpu(cpu) {
	219	domain = vector_allocation_domain(cpu);
	220	vector = find_unassigned_vector(domain);
	221	if (vector >= 0)
	222	break;
	223	}
e1b30a39 YI	224	if (vector < 0)
e1b30a39 YI	225	goto out;
4994be1b	226	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39	227	out:
4994be1b	228	spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 LT	229	return vector;
	230	}
	231
	232	void
	233	free_irq_vector (int vector)
	234	{
e1b30a39 YI	235	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
e1b30a39 YI	236	vector > IA64_LAST_DEVICE_VECTOR)
1da177e4	237	return;
e1b30a39	238	clear_irq_vector(vector);
1da177e4 LT	239	}
1da177e4 LT	240
10083072 MM	241	int
	242	reserve_irq_vector (int vector)
	243	{
10083072 MM	244	if (vector < IA64_FIRST_DEVICE_VECTOR \|\|
	245	vector > IA64_LAST_DEVICE_VECTOR)
	246	return -EINVAL;
4994be1b	247	return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
e1b30a39	248	}
10083072	249
e1b30a39 YI	250	/*
	251	* Initialize vector_irq on a new cpu. This function must be called
	252	* with vector_lock held.
	253	*/
	254	void __setup_vector_irq(int cpu)
	255	{
	256	int irq, vector;
	257
	258	/* Clear vector_irq */
	259	for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
	260	per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
	261	/* Mark the inuse vectors */
	262	for (irq = 0; irq < NR_IRQS; ++irq) {
4994be1b YI	263	if (!cpu_isset(cpu, irq_cfg[irq].domain))
	264	continue;
	265	vector = irq_to_vector(irq);
	266	per_cpu(vector_irq, cpu)[vector] = irq;
e1b30a39 YI	267	}
	268	}
	269
e5bd762b	270	#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) \|\| defined(CONFIG_IA64_DIG))
d080d397 YI	271	static enum vector_domain_type {
	272	VECTOR_DOMAIN_NONE,
	273	VECTOR_DOMAIN_PERCPU
	274	} vector_domain_type = VECTOR_DOMAIN_NONE;
	275
4994be1b YI	276	static cpumask_t vector_allocation_domain(int cpu)
4994be1b YI	277	{
d080d397 YI	278	if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
d080d397 YI	279	return cpumask_of_cpu(cpu);
4994be1b YI	280	return CPU_MASK_ALL;
	281	}
	282
d080d397 YI	283	static int __init parse_vector_domain(char *arg)
	284	{
	285	if (!arg)
	286	return -EINVAL;
	287	if (!strcmp(arg, "percpu")) {
	288	vector_domain_type = VECTOR_DOMAIN_PERCPU;
	289	no_int_routing = 1;
	290	}
	291	return 1;
	292	}
	293	early_param("vector", parse_vector_domain);
	294	#else
	295	static cpumask_t vector_allocation_domain(int cpu)
	296	{
	297	return CPU_MASK_ALL;
	298	}
	299	#endif
	300
4994be1b	301
e1b30a39 YI	302	void destroy_and_reserve_irq(unsigned int irq)
	303	{
	304	dynamic_irq_cleanup(irq);
	305
	306	clear_irq_vector(irq);
	307	reserve_irq(irq);
10083072 MM	308	}
10083072 MM	309
cd378f18 YI	310	static int __reassign_irq_vector(int irq, int cpu)
	311	{
	312	struct irq_cfg *cfg = &irq_cfg[irq];
	313	int vector;
	314	cpumask_t domain;
	315
	316	if (cfg->vector == IRQ_VECTOR_UNASSIGNED \|\| !cpu_online(cpu))
	317	return -EINVAL;
	318	if (cpu_isset(cpu, cfg->domain))
	319	return 0;
	320	domain = vector_allocation_domain(cpu);
	321	vector = find_unassigned_vector(domain);
	322	if (vector < 0)
	323	return -ENOSPC;
	324	__clear_irq_vector(irq);
	325	BUG_ON(__bind_irq_vector(irq, vector, domain));
	326	return 0;
	327	}
	328
	329	int reassign_irq_vector(int irq, int cpu)
	330	{
	331	unsigned long flags;
	332	int ret;
	333
	334	spin_lock_irqsave(&vector_lock, flags);
	335	ret = __reassign_irq_vector(irq, cpu);
	336	spin_unlock_irqrestore(&vector_lock, flags);
	337	return ret;
	338	}
	339
b6cf2583 EB	340	/*
	341	* Dynamic irq allocate and deallocation for MSI
	342	*/
	343	int create_irq(void)
	344	{
e1b30a39	345	unsigned long flags;
4994be1b YI	346	int irq, vector, cpu;
4994be1b YI	347	cpumask_t domain;
e1b30a39	348
4994be1b	349	irq = vector = -ENOSPC;
e1b30a39	350	spin_lock_irqsave(&vector_lock, flags);
4994be1b YI	351	for_each_online_cpu(cpu) {
	352	domain = vector_allocation_domain(cpu);
	353	vector = find_unassigned_vector(domain);
	354	if (vector >= 0)
	355	break;
	356	}
e1b30a39 YI	357	if (vector < 0)
	358	goto out;
	359	irq = find_unassigned_irq();
	360	if (irq < 0)
	361	goto out;
4994be1b	362	BUG_ON(__bind_irq_vector(irq, vector, domain));
e1b30a39 YI	363	out:
	364	spin_unlock_irqrestore(&vector_lock, flags);
	365	if (irq >= 0)
	366	dynamic_irq_init(irq);
	367	return irq;
b6cf2583 EB	368	}
	369
	370	void destroy_irq(unsigned int irq)
	371	{
	372	dynamic_irq_cleanup(irq);
e1b30a39	373	clear_irq_vector(irq);
b6cf2583 EB	374	}
b6cf2583 EB	375
1da177e4 LT	376	#ifdef CONFIG_SMP
1da177e4 LT	377	# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
3be44b9c	378	# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
1da177e4 LT	379	#else
1da177e4 LT	380	# define IS_RESCHEDULE(vec) (0)
3be44b9c	381	# define IS_LOCAL_TLB_FLUSH(vec) (0)
1da177e4 LT	382	#endif
	383	/*
	384	* That's where the IVT branches when we get an external
	385	* interrupt. This branches to the correct hardware IRQ handler via
	386	* function ptr.
	387	*/
	388	void
	389	ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
	390	{
7d12e780	391	struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 LT	392	unsigned long saved_tpr;
	393
	394	#if IRQ_DEBUG
	395	{
	396	unsigned long bsp, sp;
	397
	398	/*
	399	* Note: if the interrupt happened while executing in
	400	* the context switch routine (ia64_switch_to), we may
	401	* get a spurious stack overflow here. This is
	402	* because the register and the memory stack are not
	403	* switched atomically.
	404	*/
	405	bsp = ia64_getreg(_IA64_REG_AR_BSP);
	406	sp = ia64_getreg(_IA64_REG_SP);
	407
	408	if ((sp - bsp) < 1024) {
	409	static unsigned char count;
	410	static long last_time;
	411
	412	if (jiffies - last_time > 5*HZ)
	413	count = 0;
	414	if (++count < 5) {
	415	last_time = jiffies;
	416	printk("ia64_handle_irq: DANGER: less than "
	417	"1KB of free stack space!!\n"
	418	"(bsp=0x%lx, sp=%lx)\n", bsp, sp);
	419	}
	420	}
	421	}
	422	#endif /* IRQ_DEBUG */
	423
	424	/*
	425	* Always set TPR to limit maximum interrupt nesting depth to
	426	* 16 (without this, it would be ~240, which could easily lead
	427	* to kernel stack overflows).
	428	*/
	429	irq_enter();
	430	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	431	ia64_srlz_d();
	432	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	433	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	434	smp_local_flush_tlb();
	435	kstat_this_cpu.irqs[vector]++;
	436	} else if (unlikely(IS_RESCHEDULE(vector)))
	437	kstat_this_cpu.irqs[vector]++;
9b3377f9	438	else {
1da177e4 LT	439	ia64_setreg(_IA64_REG_CR_TPR, vector);
	440	ia64_srlz_d();
	441
5fbb004a	442	generic_handle_irq(local_vector_to_irq(vector));
1da177e4 LT	443
	444	/*
	445	* Disable interrupts and send EOI:
	446	*/
	447	local_irq_disable();
	448	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	449	}
	450	ia64_eoi();
	451	vector = ia64_get_ivr();
	452	}
	453	/*
	454	* This must be done after the ia64_eoi(). For example, the keyboard softirq
	455	* handler needs to be able to wait for further keyboard interrupts, which can't
	456	* come through until ia64_eoi() has been done.
	457	*/
	458	irq_exit();
7d12e780	459	set_irq_regs(old_regs);
1da177e4 LT	460	}
	461
	462	#ifdef CONFIG_HOTPLUG_CPU
	463	/*
	464	* This function emulates a interrupt processing when a cpu is about to be
	465	* brought down.
	466	*/
	467	void ia64_process_pending_intr(void)
	468	{
	469	ia64_vector vector;
	470	unsigned long saved_tpr;
	471	extern unsigned int vectors_in_migration[NR_IRQS];
	472
	473	vector = ia64_get_ivr();
	474
	475	irq_enter();
	476	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
	477	ia64_srlz_d();
	478
	479	/*
	480	* Perform normal interrupt style processing
	481	*/
	482	while (vector != IA64_SPURIOUS_INT_VECTOR) {
3be44b9c JS	483	if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
	484	smp_local_flush_tlb();
	485	kstat_this_cpu.irqs[vector]++;
	486	} else if (unlikely(IS_RESCHEDULE(vector)))
	487	kstat_this_cpu.irqs[vector]++;
9b3377f9	488	else {
8c1addbc TL	489	struct pt_regs *old_regs = set_irq_regs(NULL);
8c1addbc TL	490
1da177e4 LT	491	ia64_setreg(_IA64_REG_CR_TPR, vector);
	492	ia64_srlz_d();
	493
	494	/*
	495	* Now try calling normal ia64_handle_irq as it would have got called
	496	* from a real intr handler. Try passing null for pt_regs, hopefully
	497	* it will work. I hope it works!.
	498	* Probably could shared code.
	499	*/
	500	vectors_in_migration[local_vector_to_irq(vector)]=0;
5fbb004a	501	generic_handle_irq(local_vector_to_irq(vector));
8c1addbc	502	set_irq_regs(old_regs);
1da177e4 LT	503
	504	/*
	505	* Disable interrupts and send EOI
	506	*/
	507	local_irq_disable();
	508	ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
	509	}
	510	ia64_eoi();
	511	vector = ia64_get_ivr();
	512	}
	513	irq_exit();
	514	}
	515	#endif
	516
	517
	518	#ifdef CONFIG_SMP
1da177e4	519
9b3377f9 JS	520	static irqreturn_t dummy_handler (int irq, void *dev_id)
	521	{
	522	BUG();
	523	}
3be44b9c	524	extern irqreturn_t handle_IPI (int irq, void *dev_id);
9b3377f9	525
1da177e4 LT	526	static struct irqaction ipi_irqaction = {
1da177e4 LT	527	.handler = handle_IPI,
121a4226	528	.flags = IRQF_DISABLED,
1da177e4 LT	529	.name = "IPI"
1da177e4 LT	530	};
9b3377f9 JS	531
	532	static struct irqaction resched_irqaction = {
	533	.handler = dummy_handler,
38515e90	534	.flags = IRQF_DISABLED,
9b3377f9 JS	535	.name = "resched"
9b3377f9 JS	536	};
3be44b9c JS	537
	538	static struct irqaction tlb_irqaction = {
	539	.handler = dummy_handler,
5329571b	540	.flags = IRQF_DISABLED,
3be44b9c JS	541	.name = "tlb_flush"
	542	};
	543
1da177e4 LT	544	#endif
	545
	546	void
	547	register_percpu_irq (ia64_vector vec, struct irqaction *action)
	548	{
	549	irq_desc_t *desc;
	550	unsigned int irq;
	551
e1b30a39	552	irq = vec;
4994be1b	553	BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
e1b30a39 YI	554	desc = irq_desc + irq;
	555	desc->status \|= IRQ_PER_CPU;
	556	desc->chip = &irq_type_ia64_lsapic;
	557	if (action)
	558	setup_irq(irq, action);
1da177e4 LT	559	}
	560
	561	void __init
	562	init_IRQ (void)
	563	{
	564	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
	565	#ifdef CONFIG_SMP
	566	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
9b3377f9	567	register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
3be44b9c	568	register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
1da177e4 LT	569	#endif
	570	#ifdef CONFIG_PERFMON
	571	pfm_init_percpu();
	572	#endif
	573	platform_irq_init();
	574	}
	575
	576	void
	577	ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
	578	{
	579	void __iomem *ipi_addr;
	580	unsigned long ipi_data;
	581	unsigned long phys_cpu_id;
	582
	583	#ifdef CONFIG_SMP
	584	phys_cpu_id = cpu_physical_id(cpu);
	585	#else
	586	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
	587	#endif
	588
	589	/*
	590	* cpu number is in 8bit ID and 8bit EID
	591	*/
	592
	593	ipi_data = (delivery_mode << 8) \| (vector & 0xff);
	594	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) \| ((redirect & 1) << 3));
	595
	596	writeq(ipi_data, ipi_addr);
	597	}